From 57e5401d954d46fea45ca3eaafa8ae655659da39 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Fri, 9 May 2014 18:58:50 -0400
Subject: [PATCH] stats: Bump stats for the fixes, and mostly DRAM controller
 changes

---
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 3701 +++++++++--------
 .../ref/alpha/linux/tsunami-o3/stats.txt      | 2010 ++++-----
 .../linux/tsunami-switcheroo-full/stats.txt   | 2789 +++++++------
 .../arm/linux/realview-o3-checker/stats.txt   | 1977 ++++-----
 .../ref/arm/linux/realview-o3-dual/stats.txt  | 3553 ++++++++--------
 .../ref/arm/linux/realview-o3/stats.txt       | 1951 ++++-----
 .../linux/realview-switcheroo-full/stats.txt  | 2868 ++++++-------
 .../linux/realview-switcheroo-o3/stats.txt    | 3293 +++++++--------
 .../realview-switcheroo-timing/stats.txt      | 2031 ++++-----
 .../ref/x86/linux/pc-o3-timing/stats.txt      | 2410 +++++------
 .../stats.txt                                 |  348 +-
 .../x86/linux/pc-switcheroo-full/stats.txt    | 2920 ++++++-------
 .../10.mcf/ref/arm/linux/o3-timing/stats.txt  | 1295 +++---
 .../ref/arm/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   45 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   45 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   45 +-
 .../10.mcf/ref/x86/linux/o3-timing/stats.txt  | 1337 +++---
 .../ref/x86/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   45 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1593 +++----
 .../ref/arm/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   45 +-
 .../ref/x86/linux/o3-timing/stats.txt         | 1587 +++----
 .../ref/x86/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   45 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  510 +--
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1249 +++---
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   45 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   45 +-
 .../30.eon/ref/arm/linux/o3-timing/stats.txt  | 1353 +++---
 .../ref/arm/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   45 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1331 +++---
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   45 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   45 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1461 +++----
 .../ref/arm/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   45 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  772 ++--
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1522 +++----
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   45 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   45 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1590 +++----
 .../ref/arm/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   45 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   45 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   45 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  | 1030 +++--
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1533 +++----
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   45 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   45 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1488 +++----
 .../ref/arm/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   45 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   45 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  496 +--
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1289 +++---
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   45 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   45 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1255 +++---
 .../ref/arm/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   45 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   45 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   45 +-
 .../ref/x86/linux/o3-timing/stats.txt         | 1347 +++---
 .../ref/x86/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   45 +-
 .../tsunami-simple-atomic-dual/stats.txt      |   80 +-
 .../linux/tsunami-simple-atomic/stats.txt     |   45 +-
 .../tsunami-simple-timing-dual/stats.txt      | 2585 ++++++------
 .../linux/tsunami-simple-timing/stats.txt     | 1478 +++----
 .../realview-simple-atomic-dual/stats.txt     |  116 +-
 .../linux/realview-simple-atomic/stats.txt    |   45 +-
 .../realview-simple-timing-dual/stats.txt     | 2502 +++++------
 .../linux/realview-simple-timing/stats.txt    | 1395 ++++---
 .../realview-switcheroo-atomic/stats.txt      |  344 +-
 .../ref/x86/linux/pc-simple-atomic/stats.txt  |   45 +-
 .../ref/x86/linux/pc-simple-timing/stats.txt  | 1841 ++++----
 .../twosys-tsunami-simple-atomic/stats.txt    |  160 +-
 .../ref/alpha/linux/inorder-timing/stats.txt  |  295 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |  683 +--
 .../ref/alpha/linux/simple-atomic/stats.txt   |   45 +-
 .../stats.txt                                 |   45 +-
 .../stats.txt                                 |   45 +-
 .../stats.txt                                 |   45 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |   45 +-
 .../alpha/linux/simple-timing-ruby/stats.txt  |   45 +-
 .../ref/alpha/linux/simple-timing/stats.txt   |   45 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  467 ++-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   45 +-
 .../stats.txt                                 |   45 +-
 .../stats.txt                                 |   45 +-
 .../stats.txt                                 |   45 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |   45 +-
 .../alpha/tru64/simple-timing-ruby/stats.txt  |   45 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   45 +-
 .../ref/arm/linux/o3-timing-checker/stats.txt |  487 ++-
 .../ref/arm/linux/o3-timing/stats.txt         |  485 ++-
 .../simple-atomic-dummychecker/stats.txt      |   45 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   45 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   45 +-
 .../ref/mips/linux/inorder-timing/stats.txt   |  358 +-
 .../ref/mips/linux/o3-timing/stats.txt        |  448 +-
 .../ref/mips/linux/simple-atomic/stats.txt    |   45 +-
 .../mips/linux/simple-timing-ruby/stats.txt   |   45 +-
 .../ref/mips/linux/simple-timing/stats.txt    |   45 +-
 .../ref/power/linux/o3-timing/stats.txt       |  495 ++-
 .../ref/power/linux/simple-atomic/stats.txt   |   45 +-
 .../ref/sparc/linux/inorder-timing/stats.txt  |  368 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   45 +-
 .../sparc/linux/simple-timing-ruby/stats.txt  |   45 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   45 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  701 ++--
 .../ref/x86/linux/simple-atomic/stats.txt     |   45 +-
 .../x86/linux/simple-timing-ruby/stats.txt    |   45 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   45 +-
 .../ref/alpha/linux/o3-timing/stats.txt       | 1407 ++++---
 .../ref/sparc/linux/inorder-timing/stats.txt  |  369 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |  660 +--
 .../ref/sparc/linux/simple-atomic/stats.txt   |   45 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   45 +-
 .../ref/sparc/linux/o3-timing-mp/stats.txt    | 2352 ++++++-----
 .../sparc/linux/simple-atomic-mp/stats.txt    |  150 +-
 .../sparc/linux/simple-timing-mp/stats.txt    |  150 +-
 .../ref/null/none/tgen-dram-ctrl/stats.txt    |  804 ++--
 127 files changed, 41619 insertions(+), 36600 deletions(-)

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index bc7291548..9c4d04cdf 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.905240                       # Number of seconds simulated
-sim_ticks                                1905239522500                       # Number of ticks simulated
-final_tick                               1905239522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.905651                       # Number of seconds simulated
+sim_ticks                                1905651402000                       # Number of ticks simulated
+final_tick                               1905651402000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125426                       # Simulator instruction rate (inst/s)
-host_op_rate                                   125426                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4213194084                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 351852                       # Number of bytes of host memory used
-host_seconds                                   452.21                       # Real time elapsed on the host
-sim_insts                                    56718526                       # Number of instructions simulated
-sim_ops                                      56718526                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 124387                       # Simulator instruction rate (inst/s)
+host_op_rate                                   124387                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4179760275                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 352908                       # Number of bytes of host memory used
+host_seconds                                   455.92                       # Real time elapsed on the host
+sim_insts                                    56710998                       # Number of instructions simulated
+sim_ops                                      56710998                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           764480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24384256                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2649344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           214080                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           925440                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28937600                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       764480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       214080                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          978560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7885248                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7885248                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             11945                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            381004                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41396                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3345                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             14460                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                452150                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          123207                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123207                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              401251                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12798525                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1390557                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              112364                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              485734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15188432                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         401251                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         112364                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             513615                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4138717                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4138717                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4138717                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             401251                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12798525                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1390557                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             112364                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             485734                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19327149                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        452150                       # Number of read requests accepted
-system.physmem.writeReqs                       123207                       # Number of write requests accepted
-system.physmem.readBursts                      452150                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     123207                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28929984                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7616                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7883136                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28937600                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7885248                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      119                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu0.inst           897600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24800576                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2649600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            78720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           431296                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28857792                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       897600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        78720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          976320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7816896                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7816896                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             14025                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            387509                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41400                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1230                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              6739                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                450903                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          122139                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               122139                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              471020                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            13014225                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1390391                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               41309                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              226325                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15143269                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         471020                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          41309                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             512329                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4101955                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4101955                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4101955                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             471020                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           13014225                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1390391                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              41309                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             226325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19245224                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        450903                       # Number of read requests accepted
+system.physmem.writeReqs                       122139                       # Number of write requests accepted
+system.physmem.readBursts                      450903                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     122139                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28848704                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9088                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7815360                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28857792                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7816896                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      142                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           5017                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28700                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28863                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29008                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               28541                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               28135                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               28059                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               27918                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               27861                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27885                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               28003                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27955                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              28030                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              28165                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28514                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28239                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28155                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8383                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8222                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8291                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7900                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7506                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7518                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7426                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7231                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7193                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7295                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7315                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7381                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7680                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8142                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8013                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7678                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           4858                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               28020                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               28240                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               28746                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               28309                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27973                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               28180                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               28116                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               27456                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               27700                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               28070                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              27744                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              28151                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              28476                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              28764                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28477                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              28339                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7807                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7750                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8222                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7743                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7390                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7636                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7609                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6913                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6944                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7275                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7157                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7547                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7916                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8234                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8082                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7890                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1905235063000                       # Total gap between requests
+system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1905651381000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  452150                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  450903                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 123207                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    319865                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     54341                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     31702                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9495                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1181                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4300                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3776                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3798                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3977                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2606                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2173                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2035                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1927                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1842                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1542                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1515                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     1493                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                     1685                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                     1253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 122139                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    319686                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     41704                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     44614                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8998                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      2006                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4380                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3959                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3971                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      2562                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2247                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2201                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2095                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1646                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1635                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1944                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1926                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     2121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                     1207                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      949                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      885                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                       11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -158,360 +158,358 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      778                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2374                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3618                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5880                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6580                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6554                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3796                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2487                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1093                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1523                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1618                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1796                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1868                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1849                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1824                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1698                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1470                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      893                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        51367                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      630.908404                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     404.510586                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     424.248985                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           9707     18.90%     18.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         6974     13.58%     32.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3124      6.08%     38.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1892      3.68%     42.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1518      2.96%     45.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          943      1.84%     47.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          823      1.60%     48.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          886      1.72%     50.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        25500     49.64%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          51367                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7232                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        62.502074                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2469.163441                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           7229     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3733                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4487                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5553                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5837                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7038                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6522                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6544                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      950                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      961                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      906                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1002                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      986                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1094                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1000                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1407                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1831                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     2000                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1833                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1809                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1834                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1598                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       11                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        66611                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      550.416718                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     337.147598                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     420.487836                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14710     22.08%     22.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11156     16.75%     38.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5022      7.54%     46.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2851      4.28%     50.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2435      3.66%     54.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1624      2.44%     56.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1521      2.28%     59.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1728      2.59%     61.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        25564     38.38%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          66611                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7169                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        62.875994                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2479.971838                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           7166     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7232                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7232                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.031803                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.787924                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.763450                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6148     85.01%     85.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 35      0.48%     85.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 69      0.95%     86.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                422      5.84%     92.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                144      1.99%     94.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 50      0.69%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 33      0.46%     95.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 29      0.40%     95.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 50      0.69%     96.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 33      0.46%     96.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 22      0.30%     97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 30      0.41%     97.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 23      0.32%     98.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 33      0.46%     98.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  3      0.04%     98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 10      0.14%     98.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  7      0.10%     98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  5      0.07%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  2      0.03%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  3      0.04%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  4      0.06%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  3      0.04%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  4      0.06%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  6      0.08%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  7      0.10%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  2      0.03%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  5      0.07%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  4      0.06%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  2      0.03%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  2      0.03%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  2      0.03%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  9      0.12%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  8      0.11%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  6      0.08%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  1      0.01%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  4      0.06%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  3      0.04%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  2      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54                  1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55                  4      0.06%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7232                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    10473139750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               18209837250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2260155000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  5476542500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       23169.07                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    12115.41                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            7169                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7169                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.033756                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.809188                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.694603                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               5699     79.50%     79.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 43      0.60%     80.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                713      9.95%     90.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                256      3.57%     93.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                102      1.42%     95.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 22      0.31%     95.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 28      0.39%     95.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 86      1.20%     96.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 18      0.25%     97.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 42      0.59%     97.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 15      0.21%     97.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 21      0.29%     98.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 11      0.15%     98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 10      0.14%     98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  3      0.04%     98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 26      0.36%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  2      0.03%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  2      0.03%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  2      0.03%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  1      0.01%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  1      0.01%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  4      0.06%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  3      0.04%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  6      0.08%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  2      0.03%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  1      0.01%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  3      0.04%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  5      0.07%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                 11      0.15%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  5      0.07%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  4      0.06%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  1      0.01%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  1      0.01%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55                  1      0.01%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  7      0.10%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57                 11      0.15%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7169                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8930594750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               17382363500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2253805000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19812.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  40284.49                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.18                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.14                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.19                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.14                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  38562.26                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.14                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.10                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.14                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.10                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.83                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.68                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     407908                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     99848                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.24                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.04                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3311396.34                       # Average gap between requests
-system.physmem.pageHitRate                      88.27                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.40                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     19386335                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              296672                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296448                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13044                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13044                       # Transaction distribution
-system.membus.trans_dist::Writeback            123207                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             9628                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           5545                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            5017                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            163957                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           163513                       # Transaction distribution
-system.membus.trans_dist::BadAddressError          224                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40492                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       924104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          448                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       965044                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124646                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124646                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1089690                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        73787                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31516032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     31589819                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5306816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5306816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36896635                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36896635                       # Total data (bytes)
-system.membus.snoop_data_through_bus            38976                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            37949499                       # Layer occupancy (ticks)
+system.physmem.avgRdQLen                         1.86                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.90                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     407659                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     98604                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.44                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.73                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3325500.37                       # Average gap between requests
+system.physmem.pageHitRate                      88.37                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1804524317000                       # Time in different power states
+system.physmem.memoryStateTime::REF       63633700000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       37488657000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     19303809                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              296468                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296393                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13039                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13039                       # Transaction distribution
+system.membus.trans_dist::Writeback            122139                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             9699                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           5540                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4861                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            162690                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           162297                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           75                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40466                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       920381                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          150                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       960997                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124647                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124647                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1085644                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        73690                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31367808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     31441498                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5306880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      5306880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            36748378                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               36748378                       # Total data (bytes)
+system.membus.snoop_data_through_bus            37952                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            37884500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1621348498                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1609423248                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              283500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               94500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3837196476                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3824980631                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376708248                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          376652994                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   345233                       # number of replacements
-system.l2c.tags.tagsinuse                65245.285653                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2551644                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   410415                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.217229                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7106352750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53519.548176                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4149.494238                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5612.081999                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1358.843164                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      605.318076                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.816643                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.063316                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.085634                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.020734                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.009236                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995564                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65182                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         2472                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5440                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5794                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        51245                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994598                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 26808140                       # Number of tag accesses
-system.l2c.tags.data_accesses                26808140                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             890534                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             623023                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             181208                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             171976                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1866741                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          807199                       # number of Writeback hits
-system.l2c.Writeback_hits::total               807199                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             179                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             196                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 375                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            42                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            30                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                72                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           156975                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            15152                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               172127                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              890534                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              779998                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              181208                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              187128                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2038868                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             890534                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             779998                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             181208                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             187128                       # number of overall hits
-system.l2c.overall_hits::total                2038868                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            11953                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           272223                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             3356                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             1782                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               289314                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          3186                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           726                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3912                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          379                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          428                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             807                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         109189                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          13070                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             122259                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             11953                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            381412                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3356                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             14852                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                411573                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            11953                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           381412                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3356                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            14852                       # number of overall misses
-system.l2c.overall_misses::total               411573                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst    917004250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  17843471250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    269423486                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    137552496                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    19167451482                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      1326945                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       933461                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      2260406                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       265489                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2039412                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      2304901                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   9056624622                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1307071580                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  10363696202                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    917004250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  26900095872                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    269423486                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1444624076                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     29531147684                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    917004250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  26900095872                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    269423486                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1444624076                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    29531147684                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         902487                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         895246                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         184564                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         173758                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2156055                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       807199                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           807199                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3365                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          922                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4287                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          421                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.tags.replacements                   343977                       # number of replacements
+system.l2c.tags.tagsinuse                65252.773158                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2582565                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   408968                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.314834                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               7103141750                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   53523.190376                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5304.878115                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6147.677864                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      207.477812                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       69.548991                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.816699                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.080946                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.093806                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.003166                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.001061                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995678                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64991                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          227                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         3387                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         4556                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4338                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52483                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.991684                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 27108862                       # Number of tag accesses
+system.l2c.tags.data_accesses                27108862                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             867616                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             736617                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             210128                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              67910                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1882271                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          822208                       # number of Writeback hits
+system.l2c.Writeback_hits::total               822208                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             169                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             261                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 430                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            49                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                73                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           154436                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            25581                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               180017                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              867616                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              891053                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              210128                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               93491                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2062288                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             867616                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             891053                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             210128                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              93491                       # number of overall hits
+system.l2c.overall_hits::total                2062288                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            14035                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           273392                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             1238                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data              452                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               289117                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2673                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1056                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3729                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          406                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          434                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             840                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         114695                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           6342                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             121037                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             14035                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            388087                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1238                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              6794                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                410154                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            14035                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           388087                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1238                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             6794                       # number of overall misses
+system.l2c.overall_misses::total               410154                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst   1067454245                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  17881620237                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst     96862500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     35356999                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    19081293981                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data       964468                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      4567794                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      5532262                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       972461                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       114995                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      1087456                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   9393947733                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    639497214                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  10033444947                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1067454245                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  27275567970                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     96862500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    674854213                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     29114738928                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   1067454245                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  27275567970                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst     96862500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    674854213                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    29114738928                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         881651                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data        1010009                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         211366                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          68362                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2171388                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       822208                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           822208                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2842                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1317                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            4159                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          455                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data          458                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           879                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       266164                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        28222                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           294386                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          902487                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1161410                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          184564                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          201980                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2450441                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         902487                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1161410                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         184564                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         201980                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2450441                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.013245                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.304076                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.018183                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.010256                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.134187                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.946805                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.787419                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.912526                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.900238                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.934498                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.918089                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.410232                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.463114                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.415302                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.013245                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.328404                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.018183                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.073532                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.167959                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.013245                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.328404                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.018183                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.073532                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.167959                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76717.497699                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 65547.258130                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80281.134088                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77189.952862                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 66251.379062                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   416.492467                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1285.758953                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   577.813395                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   700.498681                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4764.981308                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  2856.135068                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82944.478125                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100005.476664                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 84768.370443                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 76717.497699                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 70527.660042                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 80281.134088                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 97267.982494                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 71751.907156                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 76717.497699                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 70527.660042                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 80281.134088                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 97267.982494                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 71751.907156                       # average overall miss latency
+system.l2c.SCUpgradeReq_accesses::total           913                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       269131                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        31923                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           301054                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          881651                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1279140                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          211366                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          100285                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2472442                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         881651                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1279140                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         211366                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         100285                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2472442                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.015919                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.270683                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.005857                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.006612                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.133148                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.940535                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.801822                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.896610                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.892308                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.947598                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.920044                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.426168                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.198666                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.402044                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.015919                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.303397                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005857                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.067747                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.165890                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.015919                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.303397                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005857                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.067747                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.165890                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76056.590310                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 65406.523369                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78241.114701                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 78223.449115                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 65998.519565                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   360.818556                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4325.562500                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1483.577903                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2395.224138                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   264.965438                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1294.590476                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81903.724949                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100835.259224                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 82895.684353                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 76056.590310                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 70282.096463                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 78241.114701                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 99330.911540                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 70984.895742                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 76056.590310                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 70282.096463                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 78241.114701                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 99330.911540                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 70984.895742                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -520,125 +518,125 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               81684                       # number of writebacks
-system.l2c.writebacks::total                    81684                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                19                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        11946                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       272222                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         3345                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         1782                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          289295                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         3186                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          726                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         3912                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          379                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          428                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          807                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       109189                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        13070                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        122259                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        11946                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       381411                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         3345                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        14852                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           411554                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        11946                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       381411                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         3345                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        14852                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          411554                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    765862000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14447057750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    226574764                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    136795504                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  15576290018                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     31921141                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7272722                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     39193863                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3803378                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4284427                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      8087805                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7721269876                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1146179920                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8867449796                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    765862000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  22168327626                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    226574764                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1282975424                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  24443739814                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    765862000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  22168327626                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    226574764                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1282975424                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  24443739814                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    936599500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    454544000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1391143500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1663713500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    943761500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2607475000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2600313000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1398305500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   3998618500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013237                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.304075                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018124                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.010256                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.134178                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.946805                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.787419                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.912526                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.900238                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.934498                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.918089                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.410232                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.463114                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.415302                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013237                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.328403                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018124                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.073532                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.167951                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013237                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.328403                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018124                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.073532                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.167951                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64110.329818                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53070.867711                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67735.355456                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76765.153760                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 53842.237225                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10019.190521                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.523416                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10018.881135                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.298153                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.343458                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.063197                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70714.722875                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 87695.479725                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72530.037020                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64110.329818                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58121.888530                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67735.355456                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86384.017237                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59393.760756                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64110.329818                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58121.888530                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67735.355456                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86384.017237                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59393.760756                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks               80619                       # number of writebacks
+system.l2c.writebacks::total                    80619                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             9                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.inst        14026                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       273392                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         1230                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data          451                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          289099                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2673                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1056                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3729                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          406                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          434                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          840                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       114695                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         6342                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        121037                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        14026                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       388087                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1230                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         6793                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           410136                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        14026                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       388087                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1230                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         6793                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          410136                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    890067005                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14473617763                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     80840000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     29712501                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  15474237269                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     26950129                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     10569046                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     37519175                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      4153902                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4341434                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      8495336                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7989750261                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    560973786                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8550724047                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    890067005                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  22463368024                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     80840000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    590686287                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  24024961316                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    890067005                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  22463368024                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     80840000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    590686287                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  24024961316                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1367392500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     22035500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1389428000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2022747000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    583651500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2606398500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3390139500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    605687000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3995826500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015909                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.270683                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005819                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.006597                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.133140                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.940535                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.801822                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.896610                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.892308                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.947598                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.920044                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.426168                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.198666                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.402044                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015909                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.303397                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005819                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.067737                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.165883                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015909                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.303397                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005819                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.067737                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.165883                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63458.363397                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52940.897184                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65723.577236                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65881.376940                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 53525.737789                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.352787                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.566288                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.457495                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10231.285714                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.304147                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10113.495238                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69660.841894                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 88453.766320                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 70645.538530                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63458.363397                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57882.299649                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65723.577236                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86955.143088                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 58578.035861                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63458.363397                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57882.299649                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65723.577236                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86955.143088                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 58578.035861                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -649,15 +647,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                41698                       # number of replacements
-system.iocache.tags.tagsinuse                0.475429                       # Cycle average of tags in use
+system.iocache.tags.replacements                41695                       # number of replacements
+system.iocache.tags.tagsinuse                0.491978                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41714                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1712299730000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.475429                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.029714                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.029714                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1712295759000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.491978                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.030749                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.030749                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -671,14 +669,14 @@ system.iocache.demand_misses::tsunami.ide        41727                       # n
 system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41727                       # number of overall misses
 system.iocache.overall_misses::total            41727                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21363133                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21363133                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  13166015946                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  13166015946                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  13187379079                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  13187379079                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  13187379079                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  13187379079                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21492883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21492883                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide  12499299192                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  12499299192                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide  12520792075                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  12520792075                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide  12520792075                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  12520792075                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -695,24 +693,24 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122075.045714                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122075.045714                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316856.371438                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 316856.371438                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 316039.472739                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 316039.472739                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 316039.472739                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 316039.472739                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        391077                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122816.474286                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122816.474286                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 300811.012514                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 300811.012514                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 300064.516380                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 300064.516380                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 300064.516380                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 300064.516380                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        367481                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28468                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                28552                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.737424                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.870587                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41523                       # number of writebacks
-system.iocache.writebacks::total                41523                       # number of writebacks
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
@@ -721,14 +719,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41727
 system.iocache.demand_mshr_misses::total        41727                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41727                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41727                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12262133                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12262133                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  11002982450                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  11002982450                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  11015244583                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  11015244583                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  11015244583                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  11015244583                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12390883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12390883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10336377204                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  10336377204                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide  10348768087                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  10348768087                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide  10348768087                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  10348768087                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -737,14 +735,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70069.331429                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70069.331429                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264800.309251                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 264800.309251                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263983.621708                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 263983.621708                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263983.621708                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 263983.621708                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 248011.313706                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 248011.313706                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -758,35 +756,35 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               12197818                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         10301308                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           323625                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             8091894                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                5160475                       # Number of BTB hits
+system.cpu0.branchPred.lookups               12477942                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         10513633                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           331474                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             8127728                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                5283638                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            63.773389                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 773216                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             29770                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            65.007564                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 797741                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             28790                       # Number of incorrect RAS predictions.
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     8724392                       # DTB read hits
-system.cpu0.dtb.read_misses                     30821                       # DTB read misses
-system.cpu0.dtb.read_acv                          561                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  667825                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5867379                       # DTB write hits
-system.cpu0.dtb.write_misses                     8333                       # DTB write misses
-system.cpu0.dtb.write_acv                         362                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 233878                       # DTB write accesses
-system.cpu0.dtb.data_hits                    14591771                       # DTB hits
-system.cpu0.dtb.data_misses                     39154                       # DTB misses
-system.cpu0.dtb.data_acv                          923                       # DTB access violations
-system.cpu0.dtb.data_accesses                  901703                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1047253                       # ITB hits
-system.cpu0.itb.fetch_misses                    31067                       # ITB misses
-system.cpu0.itb.fetch_acv                         998                       # ITB acv
-system.cpu0.itb.fetch_accesses                1078320                       # ITB accesses
+system.cpu0.dtb.read_hits                     8879185                       # DTB read hits
+system.cpu0.dtb.read_misses                     30734                       # DTB read misses
+system.cpu0.dtb.read_acv                          556                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  627584                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5815647                       # DTB write hits
+system.cpu0.dtb.write_misses                     8173                       # DTB write misses
+system.cpu0.dtb.write_acv                         357                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 210225                       # DTB write accesses
+system.cpu0.dtb.data_hits                    14694832                       # DTB hits
+system.cpu0.dtb.data_misses                     38907                       # DTB misses
+system.cpu0.dtb.data_acv                          913                       # DTB access violations
+system.cpu0.dtb.data_accesses                  837809                       # DTB accesses
+system.cpu0.itb.fetch_hits                     998260                       # ITB hits
+system.cpu0.itb.fetch_misses                    27519                       # ITB misses
+system.cpu0.itb.fetch_acv                         894                       # ITB acv
+system.cpu0.itb.fetch_accesses                1025779                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -799,269 +797,304 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       112262549                       # number of cpu cycles simulated
+system.cpu0.numCycles                       116074371                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          25337690                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      62232975                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   12197818                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           5933691                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     11660813                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1669062                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles              34963299                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles               31852                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       204835                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       245581                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          284                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  7519019                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               220862                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples          73507816                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.846617                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.186991                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          25123779                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      63882467                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   12477942                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           6081379                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     12010156                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1699076                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles              37307525                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles               31946                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       195411                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       352959                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          191                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  7722540                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               223615                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples          76113904                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.839301                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.177052                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                61847003     84.14%     84.14% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  769960      1.05%     85.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1463561      1.99%     87.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  676221      0.92%     88.10% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2490968      3.39%     91.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  505392      0.69%     92.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  543861      0.74%     92.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  933568      1.27%     94.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4277282      5.82%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                64103748     84.22%     84.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  767865      1.01%     85.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1567652      2.06%     87.29% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  704812      0.93%     88.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2586726      3.40%     91.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  521075      0.68%     92.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  575522      0.76%     93.05% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  832581      1.09%     94.15% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4453923      5.85%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            73507816                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.108654                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.554352                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                26369028                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             34601594                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 10599753                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               908827                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1028613                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              489342                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                35202                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              61098455                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               108348                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1028613                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                27370799                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               12650473                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      18559497                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9975684                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              3922748                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              57686354                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 6807                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                465136                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1446625                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands           38461887                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             70023385                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        69867874                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           145011                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             33864047                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4597832                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1504040                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        221397                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 10820518                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             9135753                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6149920                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1079808                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          706714                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  51077926                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1853906                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 49994907                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           110749                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        5661802                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      2962344                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1252355                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     73507816                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.680130                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.328001                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            76113904                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.107500                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.550358                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26378411                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             36826325                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 10921760                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               930988                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1056419                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              512680                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                35852                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              62713959                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               107463                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1056419                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                27400432                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               14971568                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      18343259                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 10229394                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              4112830                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              59339079                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 7155                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                639099                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1437135                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands           39727133                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             72236857                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        72098194                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           129082                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             34929896                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 4797229                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1458801                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        212309                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 11241570                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9288070                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6084553                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1139915                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          737819                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  52640864                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1816659                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 51478960                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            92665                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        5869250                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      3045578                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1230018                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     76113904                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.676341                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.327493                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           51188064     69.64%     69.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10233888     13.92%     83.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            4604901      6.26%     89.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2962380      4.03%     93.85% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2331848      3.17%     97.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1189595      1.62%     98.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             642601      0.87%     99.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             303208      0.41%     99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              51331      0.07%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           53257398     69.97%     69.97% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10376788     13.63%     83.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            4704231      6.18%     89.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            3091331      4.06%     93.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2445214      3.21%     97.06% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1217468      1.60%     98.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             651050      0.86%     99.51% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             318171      0.42%     99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              52253      0.07%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       73507816                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       76113904                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  67972     10.01%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                320913     47.27%     57.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               290070     42.72%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  82049     12.02%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     12.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                319124     46.77%     58.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               281213     41.21%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             3770      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             34052559     68.11%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               53588      0.11%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              16727      0.03%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9088781     18.18%     86.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5934753     11.87%     98.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            842846      1.69%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             3785      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             35464091     68.89%     68.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               56550      0.11%     69.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              15746      0.03%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1879      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9235082     17.94%     86.98% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5882526     11.43%     98.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            819301      1.59%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              49994907                       # Type of FU issued
-system.cpu0.iq.rate                          0.445339                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     678955                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.013580                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         173664474                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         58303886                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     48932524                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             622859                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            301167                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       293964                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              50344041                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 326051                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          531595                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              51478960                       # Type of FU issued
+system.cpu0.iq.rate                          0.443500                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     682386                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.013256                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         179291609                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         60070073                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     50439032                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             555265                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            269219                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       261959                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              51867113                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 290448                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          544569                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1104780                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2697                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        11676                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       443054                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1116578                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         3845                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        12782                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       445374                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        13921                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       147330                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18457                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       142389                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1028613                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                8821962                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               743484                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           56052726                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           628552                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              9135753                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6149920                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1633160                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                601804                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 5465                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         11676                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        157790                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       354691                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              512481                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             49615767                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              8780349                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           379139                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1056419                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               10732956                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               797506                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           57687159                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           618379                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9288070                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6084553                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1600267                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                582946                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 5458                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         12782                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        164537                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       351989                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              516526                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             51092894                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              8933351                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           386065                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3120894                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    14670742                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 7826693                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5890393                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.441962                       # Inst execution rate
-system.cpu0.iew.wb_sent                      49317778                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     49226488                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 24274382                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 32670143                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3229636                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    14770817                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 8136394                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5837466                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.440174                       # Inst execution rate
+system.cpu0.iew.wb_sent                      50791046                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     50700991                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 25278333                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 34060542                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.438494                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.743014                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.436797                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.742159                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        6126865                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         601551                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           478401                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     72479203                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.687487                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.606917                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        6334928                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         586641                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           480870                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     75057485                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.682787                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.597640                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     53761554     74.18%     74.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7891628     10.89%     85.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      4152119      5.73%     90.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2321486      3.20%     93.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1304265      1.80%     95.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       530677      0.73%     96.53% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       447192      0.62%     97.14% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       447640      0.62%     97.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1622642      2.24%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     55774455     74.31%     74.31% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      8026658     10.69%     85.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      4417430      5.89%     90.89% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2392691      3.19%     94.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1323184      1.76%     95.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       562724      0.75%     96.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       473653      0.63%     97.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       433129      0.58%     97.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1653561      2.20%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     72479203                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            49828537                       # Number of instructions committed
-system.cpu0.commit.committedOps              49828537                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     75057485                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            51248256                       # Number of instructions committed
+system.cpu0.commit.committedOps              51248256                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      13737839                       # Number of memory references committed
-system.cpu0.commit.loads                      8030973                       # Number of loads committed
-system.cpu0.commit.membars                     204358                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7461649                       # Number of branches committed
-system.cpu0.commit.fp_insts                    291974                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 46136165                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              636945                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1622642                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      13810671                       # Number of memory references committed
+system.cpu0.commit.loads                      8171492                       # Number of loads committed
+system.cpu0.commit.membars                     199624                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7741114                       # Number of branches committed
+system.cpu0.commit.fp_insts                    259898                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 47457125                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              657479                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2951389      5.76%      5.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        33388118     65.15%     70.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55525      0.11%     71.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         15746      0.03%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv          1879      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        8371116     16.33%     87.39% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5645183     11.02%     98.40% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       819300      1.60%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::total         51248256                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1653561                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   126610557                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  112939421                       # The number of ROB writes
-system.cpu0.timesIdled                        1039659                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       38754733                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3698211471                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   46979170                       # Number of Instructions Simulated
-system.cpu0.committedOps                     46979170                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             46979170                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.389624                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.389624                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.418476                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.418476                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                65113755                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               35503571                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   144629                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  146446                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1885764                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                851290                       # number of misc regfile writes
+system.cpu0.rob.rob_reads                   130790454                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  116222813                       # The number of ROB writes
+system.cpu0.timesIdled                        1101169                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       39960467                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3695221845                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   48300626                       # Number of Instructions Simulated
+system.cpu0.committedOps                     48300626                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             48300626                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.403165                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.403165                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.416118                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.416118                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                67219449                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               36695614                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   128632                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  130173                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1801385                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                820377                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1093,83 +1126,83 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   110236199                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2184890                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2184651                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13044                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13044                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           807199                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            9705                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          5617                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          15322                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           337408                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295861                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError          224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1805066                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3017885                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       369158                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       600045                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5792154                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     57759168                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    115626954                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     11812096                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23360753                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          208558971                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             208548411                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         1477952                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4893610631                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   111416521                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2199115                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2199023                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13039                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13039                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           822208                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            9837                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          5613                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          15450                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           343877                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302328                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           75                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1763397                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3369225                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       422759                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       294489                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5849870                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     56425664                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    130205428                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     13527424                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     10778278                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          210936794                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             210926490                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         1394560                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4971595549                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           742500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           724500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4065813860                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        3972568555                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        5358512161                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        5889953047                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         831641640                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         951834487                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         971081953                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
-system.iobus.throughput                       1435731                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq                 7377                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7377                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               54596                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              54596                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11886                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.respLayer3.occupancy         507907991                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
+system.iobus.throughput                       1435370                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq                 7369                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7369                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               54591                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              54591                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11870                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        40492                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        40466                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  123946                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        47544                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  123920                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        47480                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        73787                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        73690                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2735411                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2735411                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             11236000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total              2735314                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2735314                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy             11225000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1181,7 +1214,7 @@ system.iobus.reqLayer23.occupancy            13505000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2450000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5167000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
@@ -1189,267 +1222,268 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           379995831                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           380163081                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            27448000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            27427000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43184752                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            43193006                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           901902                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.676111                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            6573395                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           902414                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             7.284234                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      26905725250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.676111                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995461                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.995461                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          8421597                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         8421597                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      6573395                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        6573395                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      6573395                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         6573395                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      6573395                       # number of overall hits
-system.cpu0.icache.overall_hits::total        6573395                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       945623                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       945623                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       945623                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        945623                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       945623                       # number of overall misses
-system.cpu0.icache.overall_misses::total       945623                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13224491137                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13224491137                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13224491137                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13224491137                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13224491137                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13224491137                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      7519018                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7519018                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      7519018                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7519018                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      7519018                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7519018                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125764                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.125764                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125764                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.125764                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125764                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.125764                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13984.950807                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13984.950807                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13984.950807                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13984.950807                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13984.950807                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13984.950807                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         3461                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          139                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              144                       # number of cycles access was blocked
+system.cpu0.icache.tags.replacements           881127                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.683312                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            6795719                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           881636                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             7.708078                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      26872936250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.683312                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995475                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.995475                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          417                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses          8604286                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         8604286                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      6795719                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6795719                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      6795719                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         6795719                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      6795719                       # number of overall hits
+system.cpu0.icache.overall_hits::total        6795719                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       926821                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       926821                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       926821                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        926821                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       926821                       # number of overall misses
+system.cpu0.icache.overall_misses::total       926821                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13137729759                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13137729759                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13137729759                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13137729759                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13137729759                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13137729759                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      7722540                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7722540                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      7722540                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      7722540                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      7722540                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      7722540                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.120015                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.120015                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.120015                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.120015                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.120015                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.120015                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14175.045407                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14175.045407                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         3568                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets           70                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              151                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.034722                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          139                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.629139                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets           70                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43044                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        43044                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        43044                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        43044                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        43044                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        43044                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       902579                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       902579                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       902579                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       902579                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       902579                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       902579                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10909532635                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10909532635                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10909532635                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10909532635                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10909532635                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10909532635                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.120039                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.120039                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.120039                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.120039                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.120039                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.120039                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12087.066766                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12087.066766                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12087.066766                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12087.066766                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12087.066766                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12087.066766                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        45075                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        45075                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        45075                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        45075                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        45075                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        45075                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       881746                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       881746                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       881746                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       881746                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       881746                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       881746                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10814665187                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10814665187                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10814665187                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10814665187                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10814665187                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10814665187                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.114178                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.114178                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.114178                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.114178                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.114178                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.114178                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1164537                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          498.695388                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10555909                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1165049                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.060485                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         26173000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   498.695388                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.974014                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.974014                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements          1281204                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.636705                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10489009                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1281716                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.183567                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         26139000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.636705                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.987572                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.987572                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          222                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          228                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           45                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         56283368                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        56283368                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6422745                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6422745                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3752316                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3752316                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       172180                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       172180                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       196241                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       196241                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10175061                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10175061                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10175061                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10175061                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1468970                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1468970                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1742020                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1742020                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20433                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        20433                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2875                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         2875                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3210990                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3210990                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3210990                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3210990                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  38326965830                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  38326965830                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  76755016444                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  76755016444                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    286872989                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    286872989                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     20380878                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     20380878                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 115081982274                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 115081982274                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 115081982274                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 115081982274                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7891715                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7891715                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5494336                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5494336                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       192613                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       192613                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       199116                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199116                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13386051                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     13386051                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13386051                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     13386051                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.186141                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.186141                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.317057                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.317057                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.106083                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.106083                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.014439                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.014439                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.239876                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.239876                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.239876                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.239876                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26091.047353                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 26091.047353                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44060.927225                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44060.927225                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14039.690158                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14039.690158                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7089.001043                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7089.001043                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35840.031353                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 35840.031353                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35840.031353                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 35840.031353                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      2903843                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets          789                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            48428                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         56677841                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        56677841                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6448265                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6448265                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3678309                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3678309                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       163487                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       163487                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       188240                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       188240                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10126574                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10126574                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10126574                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10126574                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1590441                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1590441                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1755180                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1755180                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20486                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        20486                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2716                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         2716                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3345621                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3345621                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3345621                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3345621                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  40624107085                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  40624107085                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  78713383276                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  78713383276                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    300049994                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    300049994                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     20153405                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     20153405                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 119337490361                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 119337490361                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8038706                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8038706                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5433489                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5433489                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183973                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       183973                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       190956                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       190956                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13472195                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     13472195                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13472195                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     13472195                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197848                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.197848                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.323030                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.323030                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.111353                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.111353                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.014223                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.014223                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248335                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.248335                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248335                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.248335                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7420.252209                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7420.252209                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 35669.757681                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 35669.757681                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      2966485                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets          566                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            48680                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    59.962067                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   112.714286                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    60.938476                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    80.857143                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       644423                       # number of writebacks
-system.cpu0.dcache.writebacks::total           644423                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       578811                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       578811                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1469624                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1469624                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4269                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4269                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      2048435                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      2048435                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      2048435                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      2048435                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       890159                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       890159                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       272396                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       272396                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16164                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16164                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2875                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         2875                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1162555                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1162555                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1162555                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1162555                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25660783347                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25660783347                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11256320137                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11256320137                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    175450760                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    175450760                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     14630122                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     14630122                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  36917103484                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  36917103484                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  36917103484                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  36917103484                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    999097000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    999097000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1765340999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1765340999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2764437999                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2764437999                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.112797                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.112797                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049578                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049578                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.083920                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.083920                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.014439                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.014439                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086848                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.086848                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086848                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.086848                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28827.190813                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28827.190813                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41323.367953                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41323.367953                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10854.414749                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10854.414749                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5088.738087                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5088.738087                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31755.145764                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31755.145764                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31755.145764                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31755.145764                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       754427                       # number of writebacks
+system.cpu0.dcache.writebacks::total           754427                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       586151                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       586151                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1480465                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1480465                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4562                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4562                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2066616                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      2066616                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2066616                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      2066616                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1004290                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1004290                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       274715                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       274715                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15924                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15924                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2716                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         2716                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1279005                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1279005                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1279005                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1279005                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27273016452                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27273016452                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11562486348                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11562486348                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    175781505                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    175781505                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     14720595                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     14720595                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38835502800                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  38835502800                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38835502800                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  38835502800                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1459363000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1459363000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2145424499                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2145424499                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3604787499                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3604787499                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.124932                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.124932                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050560                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050560                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086556                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086556                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.014223                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.014223                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094937                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.094937                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094937                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.094937                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5419.953976                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5419.953976                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1457,35 +1491,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                2770041                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          2267711                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect            80921                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             1482926                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                 969002                       # Number of BTB hits
+system.cpu1.branchPred.lookups                2485884                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2055798                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect            72106                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             1444173                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                 831190                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            65.343921                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 198874                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              6522                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            57.554739                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 170291                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              7410                       # Number of incorrect RAS predictions.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2016743                       # DTB read hits
-system.cpu1.dtb.read_misses                      9789                       # DTB read misses
-system.cpu1.dtb.read_acv                            6                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  278621                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1132288                       # DTB write hits
-system.cpu1.dtb.write_misses                     1938                       # DTB write misses
-system.cpu1.dtb.write_acv                          37                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 105909                       # DTB write accesses
-system.cpu1.dtb.data_hits                     3149031                       # DTB hits
-system.cpu1.dtb.data_misses                     11727                       # DTB misses
-system.cpu1.dtb.data_acv                           43                       # DTB access violations
-system.cpu1.dtb.data_accesses                  384530                       # DTB accesses
-system.cpu1.itb.fetch_hits                     369710                       # ITB hits
-system.cpu1.itb.fetch_misses                     5636                       # ITB misses
-system.cpu1.itb.fetch_acv                         119                       # ITB acv
-system.cpu1.itb.fetch_accesses                 375346                       # ITB accesses
+system.cpu1.dtb.read_hits                     1846757                       # DTB read hits
+system.cpu1.dtb.read_misses                     10485                       # DTB read misses
+system.cpu1.dtb.read_acv                           25                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  320297                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1188866                       # DTB write hits
+system.cpu1.dtb.write_misses                     1998                       # DTB write misses
+system.cpu1.dtb.write_acv                          67                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 130212                       # DTB write accesses
+system.cpu1.dtb.data_hits                     3035623                       # DTB hits
+system.cpu1.dtb.data_misses                     12483                       # DTB misses
+system.cpu1.dtb.data_acv                           92                       # DTB access violations
+system.cpu1.dtb.data_accesses                  450509                       # DTB accesses
+system.cpu1.itb.fetch_hits                     420713                       # ITB hits
+system.cpu1.itb.fetch_misses                     6600                       # ITB misses
+system.cpu1.itb.fetch_acv                         223                       # ITB acv
+system.cpu1.itb.fetch_accesses                 427313                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1498,519 +1532,553 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        18798992                       # number of cpu cycles simulated
+system.cpu1.numCycles                        14964653                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           5357256                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      13511342                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    2770041                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1167876                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      2476292                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 427198                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles               8263333                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles               26082                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        54640                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       162618                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           35                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1630522                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                50477                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          16624070                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.812758                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.170685                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           5680448                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      11756636                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    2485884                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1001481                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      2105616                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 381271                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles               5937724                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles               25803                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        62153                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        48156                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           23                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1420733                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                48517                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          14103634                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.833589                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.209447                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                14147778     85.10%     85.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  131100      0.79%     85.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  332329      2.00%     87.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  198517      1.19%     89.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  395957      2.38%     91.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  132924      0.80%     92.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  159356      0.96%     93.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                   93423      0.56%     93.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1032686      6.21%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                11998018     85.07%     85.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  134082      0.95%     86.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  225201      1.60%     87.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  169062      1.20%     88.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  292225      2.07%     90.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  115066      0.82%     91.70% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  124219      0.88%     92.59% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  190666      1.35%     93.94% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                  855095      6.06%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            16624070                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.147351                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.718727                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 5556172                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              8353280                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  2307081                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               131115                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                276421                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              130911                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 7501                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              13245951                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                18855                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                276421                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 5775463                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2664230                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       4961239                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  2147700                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               799015                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              12421307                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  241                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                220838                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents               145988                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands            8355946                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             15113763                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        15073339                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            35607                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              7070748                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1285198                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            385003                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         30758                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2314294                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2123178                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1208247                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           244787                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          150121                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  10996175                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             428151                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 10636944                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            28046                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1617836                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       831016                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        312637                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     16624070                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.639852                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.326685                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            14103634                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.166117                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.785627                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 5621005                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              6169812                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  1969307                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               106628                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                236881                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              108171                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 6940                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              11535490                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                20476                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                236881                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 5819966                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 414819                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       5141752                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  1873919                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               616295                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              10688130                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                   72                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 55241                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents               150444                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands            7038513                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             12788456                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        12730882                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            51827                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              5999158                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1039355                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            430985                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         39680                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  1897434                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             1953635                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1261748                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           176061                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           98445                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                   9382355                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             465021                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                  9121330                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            28823                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1378008                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       697882                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        334259                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     14103634                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.646736                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.322598                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           12087523     72.71%     72.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            1967089     11.83%     84.54% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             877391      5.28%     89.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             655455      3.94%     93.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             567827      3.42%     97.18% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             232884      1.40%     98.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             149324      0.90%     99.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              75580      0.45%     99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              10997      0.07%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           10102268     71.63%     71.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            1834449     13.01%     84.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             778460      5.52%     90.16% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             526095      3.73%     93.89% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             451675      3.20%     97.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             203961      1.45%     98.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             130101      0.92%     99.46% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              68435      0.49%     99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8               8190      0.06%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       16624070                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       14103634                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  16676      8.84%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                 99378     52.65%     61.49% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                72683     38.51%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                   3122      1.64%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                102805     54.10%     55.74% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                84113     44.26%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             3518      0.03%      0.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              7118581     66.92%     66.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               18880      0.18%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd               9739      0.09%     67.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2093745     19.68%     86.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1155572     10.86%     97.79% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            235150      2.21%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             3526      0.04%      0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              5686452     62.34%     62.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               15839      0.17%     62.55% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.55% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              10725      0.12%     62.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1763      0.02%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             1931464     21.18%     83.87% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1211908     13.29%     97.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            259653      2.85%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              10636944                       # Type of FU issued
-system.cpu1.iq.rate                          0.565825                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     188737                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.017744                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          37986289                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         12982235                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     10383881                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             128452                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes             62754                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses        61527                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              10755461                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                  66702                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          101929                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total               9121330                       # Type of FU issued
+system.cpu1.iq.rate                          0.609525                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     190040                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.020835                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          32366807                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         11130082                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses      8856102                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             198350                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes             96900                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses        93876                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses               9204439                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 103405                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           88797                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       306426                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          815                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         2923                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       138344                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       277499                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         1209                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         1676                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       126244                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads         4845                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        18286                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          334                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        13648                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                276421                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                2089253                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                85247                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           12015910                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           137996                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2123178                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1208247                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            388932                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 10076                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 1666                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          2923                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         39900                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect        91880                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              131780                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             10541126                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2031671                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts            95818                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                236881                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 252351                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                39276                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           10330457                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           142523                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              1953635                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1261748                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            421576                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 32385                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 1813                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          1676                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         32559                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        96048                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              128607                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts              9031900                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              1864128                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts            89430                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       591584                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     3170643                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1658996                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1138972                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.560728                       # Inst execution rate
-system.cpu1.iew.wb_sent                      10475567                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     10445408                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  5214693                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  7314185                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       483081                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     3060773                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1345265                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1196645                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.603549                       # Inst execution rate
+system.cpu1.iew.wb_sent                       8976284                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                      8949978                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  4203498                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  5915948                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.555637                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.712956                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.598075                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.710537                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        1685534                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         115514                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           123376                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     16347649                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.627728                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.542862                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        1403439                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         130762                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           120016                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     13866753                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.637072                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.578145                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     12457643     76.20%     76.20% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      1697144     10.38%     86.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       844179      5.16%     91.75% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       419187      2.56%     94.31% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       268727      1.64%     95.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       133453      0.82%     96.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       126834      0.78%     97.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7        88227      0.54%     98.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       312255      1.91%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     10553407     76.11%     76.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1550482     11.18%     87.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       573583      4.14%     91.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       351937      2.54%     93.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       252477      1.82%     95.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        99182      0.72%     96.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       104002      0.75%     97.25% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       102635      0.74%     97.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       279048      2.01%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     16347649                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            10261869                       # Number of instructions committed
-system.cpu1.commit.committedOps              10261869                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     13866753                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts             8834118                       # Number of instructions committed
+system.cpu1.commit.committedOps               8834118                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       2886655                       # Number of memory references committed
-system.cpu1.commit.loads                      1816752                       # Number of loads committed
-system.cpu1.commit.membars                      36648                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1542101                       # Number of branches committed
-system.cpu1.commit.fp_insts                     60269                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                  9518406                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              159983                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events               312255                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                       2811640                       # Number of memory references committed
+system.cpu1.commit.loads                      1676136                       # Number of loads committed
+system.cpu1.commit.membars                      41495                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1262292                       # Number of branches committed
+system.cpu1.commit.fp_insts                     92546                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  8189363                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              139415                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass       427272      4.84%      4.84% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu         5265448     59.60%     64.44% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          15610      0.18%     64.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         10725      0.12%     64.74% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.74% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.74% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.74% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv          1763      0.02%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        1717631     19.44%     84.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       1136016     12.86%     97.06% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       259653      2.94%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::total          8834118                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               279048                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                    27899142                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   24169847                       # The number of ROB writes
-system.cpu1.timesIdled                         181051                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        2174922                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3790987217                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                    9739356                       # Number of Instructions Simulated
-system.cpu1.committedOps                      9739356                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total              9739356                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.930209                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.930209                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.518079                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.518079                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                13792462                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                7586165                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    35303                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   34737                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 829246                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                174995                       # number of misc regfile writes
-system.cpu1.icache.tags.replacements           184023                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          502.144736                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1436916                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           184535                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             7.786685                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1712232500000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   502.144736                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980751                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.980751                       # Average percentage of cache occupancy
+system.cpu1.rob.rob_reads                    23736453                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   20710450                       # The number of ROB writes
+system.cpu1.timesIdled                         126022                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         861019                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3795679739                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    8410372                       # Number of Instructions Simulated
+system.cpu1.committedOps                      8410372                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total              8410372                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.779309                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.779309                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.562016                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.562016                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                11653751                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                6367365                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    51509                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   51143                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 926936                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                206554                       # number of misc regfile writes
+system.cpu1.icache.tags.replacements           210820                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          470.468430                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            1201520                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           211332                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             5.685462                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1879665276250                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   470.468430                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.918884                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.918884                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          511                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          1815116                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         1815116                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1436916                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1436916                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1436916                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1436916                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1436916                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1436916                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       193606                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       193606                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       193606                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        193606                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       193606                       # number of overall misses
-system.cpu1.icache.overall_misses::total       193606                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   2794361223                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   2794361223                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   2794361223                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   2794361223                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   2794361223                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   2794361223                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1630522                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1630522                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1630522                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1630522                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1630522                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1630522                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.118739                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.118739                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.118739                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.118739                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.118739                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.118739                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14433.236692                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14433.236692                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14433.236692                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14433.236692                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14433.236692                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14433.236692                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs         1663                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses          1632124                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         1632124                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1201520                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1201520                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1201520                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1201520                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1201520                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1201520                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       219211                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       219211                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       219211                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        219211                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       219211                       # number of overall misses
+system.cpu1.icache.overall_misses::total       219211                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   2949137410                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   2949137410                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   2949137410                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   2949137410                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   2949137410                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   2949137410                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1420731                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1420731                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1420731                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1420731                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1420731                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1420731                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.154295                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.154295                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.154295                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.154295                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.154295                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.154295                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.418898                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.418898                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.418898                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13453.418898                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.418898                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13453.418898                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          428                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               63                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               21                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    26.396825                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    20.380952                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         9012                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total         9012                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst         9012                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total         9012                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst         9012                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total         9012                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       184594                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       184594                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       184594                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       184594                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       184594                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       184594                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2304763360                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   2304763360                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2304763360                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   2304763360                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2304763360                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   2304763360                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.113212                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.113212                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.113212                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.113212                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.113212                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.113212                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12485.581113                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12485.581113                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12485.581113                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12485.581113                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12485.581113                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12485.581113                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         7818                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total         7818                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst         7818                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total         7818                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst         7818                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total         7818                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       211393                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       211393                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       211393                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       211393                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       211393                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       211393                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2447786762                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   2447786762                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2447786762                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   2447786762                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2447786762                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   2447786762                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.148792                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.148792                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.148792                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.148792                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.148792                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.148792                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           203792                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          491.930753                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            2483389                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           204116                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            12.166557                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      43808643250                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   491.930753                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.960802                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.960802                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          324                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.632812                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         12059624                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        12059624                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1586410                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1586410                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       857564                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        857564                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        22125                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        22125                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        21120                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        21120                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      2443974                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         2443974                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      2443974                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        2443974                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       285731                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       285731                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       181299                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       181299                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4484                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         4484                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2742                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         2742                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       467030                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        467030                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       467030                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       467030                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   4578373047                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   4578373047                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10436073649                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  10436073649                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     56388497                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     56388497                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     20553927                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     20553927                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  15014446696                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  15014446696                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  15014446696                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  15014446696                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      1872141                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1872141                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1038863                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1038863                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        26609                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        26609                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        23862                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        23862                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      2911004                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      2911004                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      2911004                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      2911004                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.152623                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.152623                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.174517                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.174517                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.168514                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.168514                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.114911                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.114911                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.160436                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.160436                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.160436                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.160436                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16023.368297                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16023.368297                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 57562.775575                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 57562.775575                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12575.489964                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12575.489964                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7495.961707                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7495.961707                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32148.784224                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 32148.784224                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32148.784224                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 32148.784224                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       370227                       # number of cycles access was blocked
+system.cpu1.dcache.tags.replacements           102235                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          491.253867                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            2477501                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           102637                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            24.138478                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      45814117000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   491.253867                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.959480                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.959480                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          402                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         11642464                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        11642464                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1521331                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1521331                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       890954                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        890954                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        30283                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        30283                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        29173                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        29173                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      2412285                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         2412285                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      2412285                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        2412285                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       196472                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       196472                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       206616                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       206616                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5011                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         5011                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2898                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         2898                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       403088                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        403088                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       403088                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       403088                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2745758970                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2745758970                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6806020354                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   6806020354                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     50048997                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     50048997                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     21170434                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     21170434                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   9551779324                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   9551779324                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   9551779324                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   9551779324                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1717803                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1717803                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1097570                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1097570                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        35294                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        35294                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        32071                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        32071                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      2815373                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      2815373                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      2815373                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      2815373                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.114374                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.114374                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.188249                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.188249                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.141979                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.141979                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.090362                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.090362                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.143174                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.143174                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.143174                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.143174                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13975.319486                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13975.319486                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32940.432270                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 32940.432270                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9987.826182                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9987.826182                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7305.187716                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7305.187716                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23696.511243                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 23696.511243                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23696.511243                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 23696.511243                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       206242                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             6127                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             3728                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    60.425494                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    55.322425                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       162776                       # number of writebacks
-system.cpu1.dcache.writebacks::total           162776                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       104604                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       104604                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       148843                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       148843                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          899                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          899                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       253447                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       253447                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       253447                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       253447                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       181127                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       181127                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        32456                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        32456                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         3585                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         3585                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2742                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         2742                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       213583                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       213583                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       213583                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       213583                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2418933900                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2418933900                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1545787184                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1545787184                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     26756251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     26756251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     15069073                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     15069073                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3964721084                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3964721084                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3964721084                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   3964721084                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    485705000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    485705000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    998872003                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    998872003                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1484577003                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1484577003                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.096749                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.096749                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.031242                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.031242                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.134729                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.134729                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.114911                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.114911                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.073371                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.073371                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.073371                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.073371                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13354.905122                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13354.905122                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47627.162435                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47627.162435                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7463.389400                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7463.389400                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5495.650255                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5495.650255                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18562.905681                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18562.905681                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18562.905681                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18562.905681                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks        67781                       # number of writebacks
+system.cpu1.dcache.writebacks::total            67781                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       121809                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       121809                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       169922                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       169922                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          539                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          539                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       291731                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       291731                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       291731                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       291731                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        74663                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        74663                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        36694                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        36694                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4472                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4472                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2897                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         2897                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       111357                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       111357                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       111357                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       111357                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    836811454                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total    836811454                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    998585721                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total    998585721                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     34130252                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     34130252                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     15375566                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     15375566                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1835397175                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   1835397175                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1835397175                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   1835397175                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     23621500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     23621500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    617644004                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    617644004                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    641265504                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    641265504                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.043464                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.043464                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033432                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.033432                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.126707                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.126707                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.090331                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.090331                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.039553                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.039553                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.039553                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.039553                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7631.988372                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7631.988372                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5307.409734                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5307.409734                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2019,161 +2087,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5026                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    189626                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   66604     40.25%     40.25% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    133      0.08%     40.33% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1926      1.16%     41.49% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    191      0.12%     41.61% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  96634     58.39%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              165488                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    65244     49.22%     49.22% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     133      0.10%     49.32% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1926      1.45%     50.78% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     191      0.14%     50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   65055     49.08%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               132549                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1865394285500     97.91%     97.91% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               63356500      0.00%     97.91% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              573165000      0.03%     97.94% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               85999500      0.00%     97.95% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            39121861000      2.05%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1905238667500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.979581                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6589                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    184914                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   65370     40.53%     40.53% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.08%     40.61% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1926      1.19%     41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    186      0.12%     41.92% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  93691     58.08%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              161304                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    64362     49.21%     49.21% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.10%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1926      1.47%     50.79% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     186      0.14%     50.93% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   64176     49.07%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               130781                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1863832959500     97.81%     97.81% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               63684000      0.00%     97.81% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              569763500      0.03%     97.84% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               89287000      0.00%     97.84% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            41094897500      2.16%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1905650591500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.984580                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.673210                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.800958                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      3.45%      3.45% # number of syscalls executed
-system.cpu0.kern.syscall::3                        20      8.62%     12.07% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.72%     13.79% # number of syscalls executed
-system.cpu0.kern.syscall::6                        33     14.22%     28.02% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.43%     28.45% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      3.88%     32.33% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.31%     36.64% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.59%     39.22% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.43%     39.66% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.29%     40.95% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.02%     43.97% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.86%     44.83% # number of syscalls executed
-system.cpu0.kern.syscall::45                       39     16.81%     61.64% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.29%     62.93% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.31%     67.24% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.31%     71.55% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.43%     71.98% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.59%     74.57% # number of syscalls executed
-system.cpu0.kern.syscall::71                       27     11.64%     86.21% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.29%     87.50% # number of syscalls executed
-system.cpu0.kern.syscall::74                        7      3.02%     90.52% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.43%     90.95% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.29%     92.24% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      3.88%     96.12% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.86%     96.98% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.86%     97.84% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.43%     98.28% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.86%     99.14% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.86%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   232                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.684975                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.810773                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         7      3.32%      3.32% # number of syscalls executed
+system.cpu0.kern.syscall::3                        17      8.06%     11.37% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      1.90%     13.27% # number of syscalls executed
+system.cpu0.kern.syscall::6                        29     13.74%     27.01% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.47%     27.49% # number of syscalls executed
+system.cpu0.kern.syscall::17                       10      4.74%     32.23% # number of syscalls executed
+system.cpu0.kern.syscall::19                        7      3.32%     35.55% # number of syscalls executed
+system.cpu0.kern.syscall::20                        4      1.90%     37.44% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.47%     37.91% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.42%     39.34% # number of syscalls executed
+system.cpu0.kern.syscall::33                        8      3.79%     43.13% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.95%     44.08% # number of syscalls executed
+system.cpu0.kern.syscall::45                       37     17.54%     61.61% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.42%     63.03% # number of syscalls executed
+system.cpu0.kern.syscall::48                        8      3.79%     66.82% # number of syscalls executed
+system.cpu0.kern.syscall::54                        9      4.27%     71.09% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.47%     71.56% # number of syscalls executed
+system.cpu0.kern.syscall::59                        5      2.37%     73.93% # number of syscalls executed
+system.cpu0.kern.syscall::71                       27     12.80%     86.73% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.42%     88.15% # number of syscalls executed
+system.cpu0.kern.syscall::74                        7      3.32%     91.47% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.47%     91.94% # number of syscalls executed
+system.cpu0.kern.syscall::90                        2      0.95%     92.89% # number of syscalls executed
+system.cpu0.kern.syscall::92                        7      3.32%     96.21% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.95%     97.16% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.95%     98.10% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.47%     98.58% # number of syscalls executed
+system.cpu0.kern.syscall::144                       1      0.47%     99.05% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.95%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   211                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  273      0.16%      0.16% # number of callpals executed
+system.cpu0.kern.callpal::wripir                  277      0.16%      0.16% # number of callpals executed
 system.cpu0.kern.callpal::wrmces                    1      0.00%      0.16% # number of callpals executed
 system.cpu0.kern.callpal::wrfen                     1      0.00%      0.16% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.16% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3846      2.21%      2.37% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      50      0.03%      2.39% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.40% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               158278     90.80%     93.20% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6346      3.64%     96.84% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.84% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     96.84% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.85% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.85% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4961      2.85%     99.70% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 391      0.22%     99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb                     138      0.08%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                174309                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7462                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1354                       # number of protection mode switches
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.17% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3529      2.08%      2.24% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      48      0.03%      2.27% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.27% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               154533     90.92%     93.20% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6537      3.85%     97.04% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.04% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     4      0.00%     97.05% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     8      0.00%     97.05% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.05% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4527      2.66%     99.72% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 345      0.20%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     137      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                169959                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7072                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1287                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1353                      
-system.cpu0.kern.mode_good::user                 1354                      
+system.cpu0.kern.mode_good::kernel               1286                      
+system.cpu0.kern.mode_good::user                 1287                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.181319                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.181844                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.307055                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1903211741000     99.89%     99.89% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2026918500      0.11%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.307812                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1903707301000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1943282500      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3847                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3530                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    3999                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     49848                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   15658     37.06%     37.06% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1924      4.55%     41.62% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    273      0.65%     42.26% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  24392     57.74%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               42247                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    15641     47.10%     47.10% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1924      5.79%     52.90% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     273      0.82%     53.72% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   15369     46.28%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                33207                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1871713408000     98.26%     98.26% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              533048500      0.03%     98.29% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              128777500      0.01%     98.29% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            32519855000      1.71%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1904895089000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.998914                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2439                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     54740                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   16948     36.40%     36.40% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1925      4.13%     40.53% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    277      0.59%     41.13% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  27412     58.87%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               46562                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    16579     47.26%     47.26% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1925      5.49%     52.74% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     277      0.79%     53.53% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   16302     46.47%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                35083                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1874130150000     98.36%     98.36% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              532183000      0.03%     98.39% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              125676500      0.01%     98.40% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            30535391000      1.60%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1905323400500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.978228                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.630084                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.786020                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3                        10     10.64%     10.64% # number of syscalls executed
-system.cpu1.kern.syscall::6                         9      9.57%     20.21% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      1.06%     21.28% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      6.38%     27.66% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      3.19%     30.85% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      3.19%     34.04% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      4.26%     38.30% # number of syscalls executed
-system.cpu1.kern.syscall::45                       15     15.96%     54.26% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      3.19%     57.45% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      1.06%     58.51% # number of syscalls executed
-system.cpu1.kern.syscall::71                       27     28.72%     87.23% # number of syscalls executed
-system.cpu1.kern.syscall::74                        9      9.57%     96.81% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      3.19%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                    94                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.594703                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.753468                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2                         1      0.87%      0.87% # number of syscalls executed
+system.cpu1.kern.syscall::3                        13     11.30%     12.17% # number of syscalls executed
+system.cpu1.kern.syscall::6                        13     11.30%     23.48% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.87%     24.35% # number of syscalls executed
+system.cpu1.kern.syscall::17                        5      4.35%     28.70% # number of syscalls executed
+system.cpu1.kern.syscall::19                        3      2.61%     31.30% # number of syscalls executed
+system.cpu1.kern.syscall::20                        2      1.74%     33.04% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.61%     35.65% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.61%     38.26% # number of syscalls executed
+system.cpu1.kern.syscall::33                        3      2.61%     40.87% # number of syscalls executed
+system.cpu1.kern.syscall::45                       17     14.78%     55.65% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.61%     58.26% # number of syscalls executed
+system.cpu1.kern.syscall::48                        2      1.74%     60.00% # number of syscalls executed
+system.cpu1.kern.syscall::54                        1      0.87%     60.87% # number of syscalls executed
+system.cpu1.kern.syscall::59                        2      1.74%     62.61% # number of syscalls executed
+system.cpu1.kern.syscall::71                       27     23.48%     86.09% # number of syscalls executed
+system.cpu1.kern.syscall::74                        9      7.83%     93.91% # number of syscalls executed
+system.cpu1.kern.syscall::90                        1      0.87%     94.78% # number of syscalls executed
+system.cpu1.kern.syscall::92                        2      1.74%     96.52% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.61%     99.13% # number of syscalls executed
+system.cpu1.kern.syscall::144                       1      0.87%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   115                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  191      0.44%      0.44% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.44% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.45% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                  742      1.70%      2.15% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.01%      2.15% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.02%      2.17% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                37463     85.96%     88.13% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2409      5.53%     93.66% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.66% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     93.67% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     93.68% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2587      5.94%     99.62% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 124      0.28%     99.90% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.10%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  186      0.39%      0.39% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.39% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.39% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1067      2.22%      2.61% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       6      0.01%      2.63% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      2.64% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                41329     85.97%     88.61% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2224      4.63%     93.23% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.23% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     3      0.01%     93.24% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     1      0.00%     93.24% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.25% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3030      6.30%     99.55% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 172      0.36%     99.91% # number of callpals executed
+system.cpu1.kern.callpal::imb                      43      0.09%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 43580                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel              937                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                383                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2395                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                617                      
-system.cpu1.kern.mode_good::user                  383                      
-system.cpu1.kern.mode_good::idle                  234                      
-system.cpu1.kern.mode_switch_good::kernel     0.658485                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 48076                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1341                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                460                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2398                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                662                      
+system.cpu1.kern.mode_good::user                  460                      
+system.cpu1.kern.mode_good::idle                  202                      
+system.cpu1.kern.mode_switch_good::kernel     0.493661                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.097704                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.332167                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       34875641000      1.83%      1.83% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           708299500      0.04%      1.87% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1868990228500     98.13%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     743                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.084237                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.315313                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        4271038500      0.22%      0.22% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           809340000      0.04%      0.27% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1900232555000     99.73%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1068                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 0b1609ec3..272c07d73 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,128 +1,128 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.860192                       # Number of seconds simulated
-sim_ticks                                1860191785500                       # Number of ticks simulated
-final_tick                               1860191785500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.860188                       # Number of seconds simulated
+sim_ticks                                1860187818000                       # Number of ticks simulated
+final_tick                               1860187818000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128947                       # Simulator instruction rate (inst/s)
-host_op_rate                                   128947                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4527634915                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 347764                       # Number of bytes of host memory used
-host_seconds                                   410.85                       # Real time elapsed on the host
-sim_insts                                    52978349                       # Number of instructions simulated
-sim_ops                                      52978349                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 129673                       # Simulator instruction rate (inst/s)
+host_op_rate                                   129673                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4553007725                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 348812                       # Number of bytes of host memory used
+host_seconds                                   408.56                       # Real time elapsed on the host
+sim_insts                                    52979638                       # Number of instructions simulated
+sim_ops                                      52979638                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            963264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24877248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            963200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24881344                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28492800                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       963264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          963264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7515392                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7515392                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15051                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388707                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             28496832                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       963200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          963200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7516608                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7516608                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15050                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388771                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                445200                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117428                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117428                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               517830                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13373486                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1425814                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15317130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          517830                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             517830                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4040117                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4040117                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4040117                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              517830                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13373486                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1425814                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19357247                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        445200                       # Number of read requests accepted
-system.physmem.writeReqs                       117428                       # Number of write requests accepted
-system.physmem.readBursts                      445200                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117428                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28485504                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7296                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7513728                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28492800                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7515392                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      114                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                445263                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117447                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117447                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               517797                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13375716                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1425817                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15319331                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          517797                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             517797                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4040779                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4040779                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4040779                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              517797                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13375716                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1425817                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19360110                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        445263                       # Number of read requests accepted
+system.physmem.writeReqs                       117447                       # Number of write requests accepted
+system.physmem.readBursts                      445263                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     117447                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28490624                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6208                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7515520                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28496832                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7516608                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       97                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            178                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28210                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               27995                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28357                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               27829                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27761                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27267                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               27371                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               27375                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27696                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27269                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              28017                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            171                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               28211                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               27992                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               28433                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               27987                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27796                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               27217                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               27269                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               27319                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               27690                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               27272                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              28021                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              27509                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27546                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28232                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28342                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28310                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7920                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7516                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7873                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7373                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7309                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6720                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6881                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6774                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7136                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6679                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7411                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6967                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7107                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7877                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8064                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7795                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              27548                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              28237                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28335                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              28330                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7921                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7511                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7946                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7492                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7346                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6678                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6778                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6711                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7130                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6681                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7414                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6966                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7109                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7879                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8056                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7812                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1860186344000                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1860182401000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  445200                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  445263                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117428                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    322906                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     56729                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     22897                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      5869                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4278                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3757                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3842                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3993                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2551                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2136                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2038                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1891                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1835                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1567                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1541                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     1538                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1552                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                     1725                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                     1258                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       16                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                       10                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117447                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    316668                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     59729                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     27667                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      5430                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      2043                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4389                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3993                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3992                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      2540                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2192                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2171                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2086                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1617                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1588                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1906                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1882                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     2139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                     1226                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      986                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      905                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -148,132 +148,129 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4688                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4816                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5562                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5401                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1823                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       22                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        48603                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      651.388927                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     428.580055                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     419.495686                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           8350     17.18%     17.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         6347     13.06%     30.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         2940      6.05%     36.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1813      3.73%     40.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1501      3.09%     43.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          899      1.85%     44.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          723      1.49%     46.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          886      1.82%     48.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        25144     51.73%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          48603                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6893                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        64.568403                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2543.170744                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           6890     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3501                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4755                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4765                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4891                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5082                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5526                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5836                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6071                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5967                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      924                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      938                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      935                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      998                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1592                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1859                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     2023                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1831                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1731                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1870                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1643                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      821                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      354                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       17                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        63749                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      564.805095                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     351.189585                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     419.649920                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13350     20.94%     20.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10335     16.21%     37.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4789      7.51%     44.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2797      4.39%     49.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2437      3.82%     52.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1576      2.47%     55.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1469      2.30%     57.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1613      2.53%     60.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        25383     39.82%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63749                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6887                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        64.637723                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       16.523346                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2544.314640                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           6884     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6893                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6893                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.032062                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.789521                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.768510                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               5850     84.87%     84.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 28      0.41%     85.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 70      1.02%     86.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                418      6.06%     92.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                134      1.94%     94.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 49      0.71%     95.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 24      0.35%     95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 22      0.32%     95.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 53      0.77%     96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 38      0.55%     97.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 20      0.29%     97.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 34      0.49%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 19      0.28%     98.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 34      0.49%     98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  7      0.10%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 10      0.15%     98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  2      0.03%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  2      0.03%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  3      0.04%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  6      0.09%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  5      0.07%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  5      0.07%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  8      0.12%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  4      0.06%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  2      0.03%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  1      0.01%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  2      0.03%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  5      0.07%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  2      0.03%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  6      0.09%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  6      0.09%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  4      0.06%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  2      0.03%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  1      0.01%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  2      0.03%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  2      0.03%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54                  3      0.04%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55                  1      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  6      0.09%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                  1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58                  2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6893                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    10196532000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               17805650750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2225430000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  5383688750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       22909.13                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    12095.84                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            6887                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6887                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.050966                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.814496                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.834643                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               5493     79.76%     79.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 28      0.41%     80.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                690     10.02%     90.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                216      3.14%     93.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                116      1.68%     95.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 20      0.29%     95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 25      0.36%     95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 93      1.35%     97.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 19      0.28%     97.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 44      0.64%     97.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 11      0.16%     98.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  7      0.10%     98.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  8      0.12%     98.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 16      0.23%     98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  2      0.03%     98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 14      0.20%     98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  9      0.13%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.01%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.01%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  3      0.04%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  2      0.03%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  1      0.01%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  1      0.01%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  2      0.03%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  7      0.10%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  4      0.06%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  2      0.03%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  3      0.04%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  1      0.01%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  4      0.06%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  3      0.04%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  3      0.04%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  7      0.10%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  4      0.06%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  1      0.01%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53                  1      0.01%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54                  1      0.01%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  7      0.10%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57                 17      0.25%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6887                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8647566500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16994429000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2225830000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19425.49                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  40004.97                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.31                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  38175.49                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.32                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       15.32                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
@@ -281,60 +278,64 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.54                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.57                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     402462                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96189                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.42                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.91                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3306245.59                       # Average gap between requests
-system.physmem.pageHitRate                      88.65                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.41                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     19400105                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              295926                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295846                       # Transaction distribution
+system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.02                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     403062                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95784                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.54                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.56                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3305756.79                       # Average gap between requests
+system.physmem.pageHitRate                      88.67                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1761433244000                       # Time in different power states
+system.physmem.memoryStateTime::REF       62115560000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       36633312250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     19402968                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              295944                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295866                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
-system.membus.trans_dist::Writeback            117428                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              181                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             181                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            156840                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           156840                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           80                       # Transaction distribution
+system.membus.trans_dist::Writeback            117447                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              174                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             174                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            156883                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           156883                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           78                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884064                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917278                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884195                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          156                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917405                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124679                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124679                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1041957                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1042084                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30699136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30743276                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30704384                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30748524                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309056                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total      5309056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36052332                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36052332                       # Total data (bytes)
+system.membus.tot_pkt_size::total            36057580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               36057580                       # Total data (bytes)
 system.membus.snoop_data_through_bus            35584                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            29929000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            29864500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1552530249                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1548275500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              100500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               98000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3767548549                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3770327047                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376726994                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          376611244                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.261130                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.261115                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1710337661000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.261130                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078821                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078821                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1710335896000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.261115                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078820                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078820                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -348,14 +349,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21133883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21133883                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  13194182648                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  13194182648                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  13215316531                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  13215316531                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  13215316531                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  13215316531                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21272883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21272883                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide  12456693929                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  12456693929                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide  12477966812                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  12477966812                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide  12477966812                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  12477966812                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -372,19 +373,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122161.173410                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 317534.237774                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 316724.182888                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 316724.182888                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        393531                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122964.641618                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 299785.664445                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 299052.529946                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 299052.529946                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        365915                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28535                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                28370                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.791169                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.897956                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -398,14 +399,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12136883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  11031075660                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  11031075660                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  11043212543                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  11043212543                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  11043212543                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  11043212543                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12274883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12274883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10293819441                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  10293819441                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide  10306094324                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  10306094324                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide  10306094324                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  10306094324                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -414,14 +415,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 264666.567837                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 264666.567837                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 247000.463128                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 247000.463128                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -435,36 +436,36 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                13847711                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11622265                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            397151                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9355929                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5809145                       # Number of BTB hits
+system.cpu.branchPred.lookups                13846630                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11622667                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            398238                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9513264                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5817388                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             62.090520                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  903416                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              38861                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             61.150284                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  900921                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              39034                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9926060                       # DTB read hits
-system.cpu.dtb.read_misses                      41229                       # DTB read misses
-system.cpu.dtb.read_acv                           545                       # DTB read access violations
-system.cpu.dtb.read_accesses                   943227                       # DTB read accesses
-system.cpu.dtb.write_hits                     6592681                       # DTB write hits
-system.cpu.dtb.write_misses                     10567                       # DTB write misses
-system.cpu.dtb.write_acv                          408                       # DTB write access violations
-system.cpu.dtb.write_accesses                  338977                       # DTB write accesses
-system.cpu.dtb.data_hits                     16518741                       # DTB hits
-system.cpu.dtb.data_misses                      51796                       # DTB misses
-system.cpu.dtb.data_acv                           953                       # DTB access violations
-system.cpu.dtb.data_accesses                  1282204                       # DTB accesses
-system.cpu.itb.fetch_hits                     1307907                       # ITB hits
-system.cpu.itb.fetch_misses                     36763                       # ITB misses
-system.cpu.itb.fetch_acv                         1058                       # ITB acv
-system.cpu.itb.fetch_accesses                 1344670                       # ITB accesses
+system.cpu.dtb.read_hits                      9912884                       # DTB read hits
+system.cpu.dtb.read_misses                      41215                       # DTB read misses
+system.cpu.dtb.read_acv                           553                       # DTB read access violations
+system.cpu.dtb.read_accesses                   941108                       # DTB read accesses
+system.cpu.dtb.write_hits                     6599017                       # DTB write hits
+system.cpu.dtb.write_misses                     10339                       # DTB write misses
+system.cpu.dtb.write_acv                          401                       # DTB write access violations
+system.cpu.dtb.write_accesses                  338138                       # DTB write accesses
+system.cpu.dtb.data_hits                     16511901                       # DTB hits
+system.cpu.dtb.data_misses                      51554                       # DTB misses
+system.cpu.dtb.data_acv                           954                       # DTB access violations
+system.cpu.dtb.data_accesses                  1279246                       # DTB accesses
+system.cpu.itb.fetch_hits                     1308304                       # ITB hits
+system.cpu.itb.fetch_misses                     36786                       # ITB misses
+system.cpu.itb.fetch_acv                         1079                       # ITB acv
+system.cpu.itb.fetch_accesses                 1345090                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -477,269 +478,304 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        122133073                       # number of cpu cycles simulated
+system.cpu.numCycles                        121969353                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           28029052                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       70711644                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    13847711                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6712561                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      13244944                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1986135                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               38034896                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                32174                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        253831                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       364385                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          294                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8541461                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                263003                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           81242947                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.870373                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.213979                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           28022459                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       70674133                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    13846630                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6718309                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      13243332                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1983249                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               37995640                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                32164                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        254581                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       364654                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          235                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8542175                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                264688                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           81194854                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.870426                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.213908                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 67998003     83.70%     83.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   851901      1.05%     84.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1695578      2.09%     86.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   822984      1.01%     87.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2755109      3.39%     91.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   560259      0.69%     91.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   643349      0.79%     92.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1008302      1.24%     93.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4907462      6.04%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 67951522     83.69%     83.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   854853      1.05%     84.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1698258      2.09%     86.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   823227      1.01%     87.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2753963      3.39%     91.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   558188      0.69%     91.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   642929      0.79%     92.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1006595      1.24%     93.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4905319      6.04%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             81242947                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.113382                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.578972                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 29204589                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              37726390                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  12112827                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                958015                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1241125                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               582779                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 42656                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               69393384                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                129440                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1241125                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 30348079                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                14012797                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20034433                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  11321379                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4285132                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               65602946                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  7156                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 505213                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1511728                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            43797820                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              79654521                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79475437                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            166633                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38179156                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  5618656                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1682920                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         240154                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12205182                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10434201                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6904424                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1321264                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           860087                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58162225                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2049609                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  56784496                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            110090                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         6876207                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3554384                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1388666                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      81242947                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.698947                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.361354                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             81194854                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.113525                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.579442                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 29206421                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              37679452                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  12104138                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                965352                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1239490                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               585042                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 42720                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               69357398                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                129450                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1239490                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 30354385                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                13996332                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       19984766                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  11324382                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4295497                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               65588313                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  7118                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 505148                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1530678                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            43795306                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              79617271                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79438234                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            166586                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38180209                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  5615089                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1682372                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         239607                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12205686                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10422971                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6895231                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1319326                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           854507                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58152614                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2049745                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  56795087                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             97937                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         6861282                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3503589                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1388801                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      81194854                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.699491                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.361721                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            56591956     69.66%     69.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10816248     13.31%     82.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5164366      6.36%     89.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3390360      4.17%     93.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2636798      3.25%     96.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1463129      1.80%     98.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6              751413      0.92%     99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              332295      0.41%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               96382      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            56519522     69.61%     69.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10856431     13.37%     82.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5145956      6.34%     89.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3402319      4.19%     93.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2626681      3.24%     96.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1459376      1.80%     98.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              753323      0.93%     99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              333723      0.41%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               97523      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        81242947                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        81194854                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   91428     11.57%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 372699     47.16%     58.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                326088     41.27%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   92642     11.69%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 372744     47.05%     58.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                326922     41.26%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              38710597     68.17%     68.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61705      0.11%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10355398     18.24%     86.58% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6671255     11.75%     98.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              38726894     68.19%     68.20% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61723      0.11%     68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10344006     18.21%     86.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6676923     11.76%     98.33% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess             949012      1.67%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               56784496                       # Type of FU issued
-system.cpu.iq.rate                           0.464940                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      790215                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013916                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          195020122                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          66766340                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55549754                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              692121                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             335594                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       327937                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               57205980                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  361445                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           599867                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               56795087                       # Type of FU issued
+system.cpu.iq.rate                           0.465650                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      792308                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013950                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          194982001                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          66741051                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55566428                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              693271                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             336387                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       327889                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               57217918                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  362191                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           598643                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1342082                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         3325                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14250                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       526611                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1330641                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3245                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14147                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       517313                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        17915                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        172386                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        17932                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        166827                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1241125                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                10205447                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                698563                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            63733516                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            684669                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10434201                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6904424                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1805473                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 512478                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 17546                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14250                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         200257                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       411476                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               611733                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56321962                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts               9995488                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            462533                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1239490                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                10213175                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                697716                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            63724678                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            681593                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10422971                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6895231                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1805950                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 512370                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 16905                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14147                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         202448                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       409860                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               612308                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              56329043                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts               9982328                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            466043                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3521682                       # number of nop insts executed
-system.cpu.iew.exec_refs                     16613940                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8922207                       # Number of branches executed
-system.cpu.iew.exec_stores                    6618452                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.461152                       # Inst execution rate
-system.cpu.iew.wb_sent                       55993079                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      55877691                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  27722224                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  37565081                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3522319                       # number of nop insts executed
+system.cpu.iew.exec_refs                     16606918                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8922931                       # Number of branches executed
+system.cpu.iew.exec_stores                    6624590                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.461829                       # Inst execution rate
+system.cpu.iew.wb_sent                       56008659                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      55894317                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  27713107                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  37520284                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.457515                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.737979                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.458265                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.738617                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7447390                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          660943                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            565908                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     80001822                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.702098                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.631989                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7436889                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          660944                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            566942                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     79955364                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.702522                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.631936                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     59240837     74.05%     74.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8588333     10.74%     84.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4609463      5.76%     90.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2533581      3.17%     93.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1517845      1.90%     95.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       611107      0.76%     96.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       522353      0.65%     97.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       526375      0.66%     97.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1851928      2.31%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     59166975     74.00%     74.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8627079     10.79%     84.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4603678      5.76%     90.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2536989      3.17%     93.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1507337      1.89%     95.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       611638      0.76%     96.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       523619      0.65%     97.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       528614      0.66%     97.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1849435      2.31%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     80001822                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56169084                       # Number of instructions committed
-system.cpu.commit.committedOps               56169084                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total     79955364                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56170432                       # Number of instructions committed
+system.cpu.commit.committedOps               56170432                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15469932                       # Number of memory references committed
-system.cpu.commit.loads                       9092119                       # Number of loads committed
-system.cpu.commit.membars                      226344                       # Number of memory barriers committed
-system.cpu.commit.branches                    8439731                       # Number of branches committed
+system.cpu.commit.refs                       15470248                       # Number of memory references committed
+system.cpu.commit.loads                       9092330                       # Number of loads committed
+system.cpu.commit.membars                      226348                       # Number of memory barriers committed
+system.cpu.commit.branches                    8439871                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52018783                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740550                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               1851928                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  52020070                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               740568                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3198067      5.69%      5.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36230888     64.50%     70.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60673      0.11%     70.30% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.30% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd          25607      0.05%     70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv           3636      0.01%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9318678     16.59%     86.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6383871     11.37%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        949012      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total          56170432                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1849435                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    141516799                       # The number of ROB reads
-system.cpu.rob.rob_writes                   128475885                       # The number of ROB writes
-system.cpu.timesIdled                         1198400                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        40890126                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3598244060                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52978349                       # Number of Instructions Simulated
-system.cpu.committedOps                      52978349                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              52978349                       # Number of Instructions Simulated
-system.cpu.cpi                               2.305339                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.305339                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.433776                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.433776                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 73853807                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40298046                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166062                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167446                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2027357                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 938942                       # number of misc regfile writes
+system.cpu.rob.rob_reads                    141463709                       # The number of ROB reads
+system.cpu.rob.rob_writes                   128455843                       # The number of ROB writes
+system.cpu.timesIdled                         1197783                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        40774499                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3598399845                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52979638                       # Number of Instructions Simulated
+system.cpu.committedOps                      52979638                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              52979638                       # Number of Instructions Simulated
+system.cpu.cpi                               2.302193                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.302193                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.434368                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.434368                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 73867254                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40307997                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166020                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167441                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2027897                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 938938                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -771,7 +807,7 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.throughput                       1454553                       # Throughput (bytes/s)
+system.iobus.throughput                       1454556                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               51149                       # Transaction distribution
@@ -831,241 +867,241 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           380111537                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           380172568                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43192006                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            43172756                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.throughput               111856774                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2116112                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2116015                       # Transaction distribution
+system.cpu.toL2Bus.throughput               111944057                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2118154                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2118059                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       840541                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       840946                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           62                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           63                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       342408                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       300857                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           80                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2017437                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3676056                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5693493                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64554304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143513388                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      208067692                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         208057644                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        17408                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2478840496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           64                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       342489                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       300938                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           78                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2020220                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3677927                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5698147                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64643392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143586284                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      208229676                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         208219628                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus        17344                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2480508998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1516414125                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1518532368                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2186111163                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2189805164                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.icache.tags.replacements           1008048                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.665585                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7476650                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1008556                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.413222                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       26682759250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.665585                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.995441                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.995441                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1009436                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.668112                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7476172                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1009944                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.402561                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       26651967250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.668112                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.995446                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.995446                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          314                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           9550236                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          9550236                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7476651                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7476651                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7476651                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7476651                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7476651                       # number of overall hits
-system.cpu.icache.overall_hits::total         7476651                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1064809                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1064809                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1064809                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1064809                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1064809                       # number of overall misses
-system.cpu.icache.overall_misses::total       1064809                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14791038698                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14791038698                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14791038698                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14791038698                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14791038698                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14791038698                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8541460                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8541460                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8541460                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8541460                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8541460                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8541460                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124664                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.124664                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.124664                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.124664                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.124664                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.124664                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13890.790459                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13890.790459                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13890.790459                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13890.790459                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13890.790459                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13890.790459                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         5929                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          286                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses           9552342                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          9552342                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7476173                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7476173                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7476173                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7476173                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7476173                       # number of overall hits
+system.cpu.icache.overall_hits::total         7476173                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1066002                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1066002                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1066002                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1066002                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1066002                       # number of overall misses
+system.cpu.icache.overall_misses::total       1066002                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14786308436                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14786308436                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14786308436                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14786308436                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14786308436                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14786308436                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8542175                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8542175                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8542175                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8542175                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8542175                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8542175                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124793                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.124793                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.124793                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.124793                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.124793                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.124793                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13870.807406                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13870.807406                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13870.807406                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13870.807406                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13870.807406                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13870.807406                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         4221                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs               183                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    32.398907                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          286                       # average number of cycles each access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    23.065574                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        56033                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        56033                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        56033                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        56033                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        56033                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        56033                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1008776                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1008776                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1008776                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1008776                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1008776                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1008776                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12131918870                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12131918870                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12131918870                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12131918870                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12131918870                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12131918870                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.118103                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.118103                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.118103                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.118103                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.118103                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.118103                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.375399                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.375399                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.375399                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.375399                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.375399                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.375399                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        55835                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        55835                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        55835                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        55835                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        55835                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        55835                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1010167                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1010167                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1010167                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1010167                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1010167                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1010167                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12133097628                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12133097628                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12133097628                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12133097628                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12133097628                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12133097628                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.118256                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.118256                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.118256                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.118256                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.118256                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.118256                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12010.981974                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12010.981974                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12010.981974                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12010.981974                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12010.981974                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12010.981974                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           338266                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65338.058683                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2543929                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403433                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.305704                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5551710750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53796.698722                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5304.345669                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6237.014293                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.820872                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080938                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.095169                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996980                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          492                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3493                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3306                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           338321                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65341.789916                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2546336                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           403490                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.310778                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5544203750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 53907.448463                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5292.784095                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6141.557358                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.822562                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080761                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.093713                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997037                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65169                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          493                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3494                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3325                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2414                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55462                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26707389                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26707389                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       993608                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       826462                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1820070                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       840541                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       840541                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           20                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           20                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            1                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       185429                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       185429                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       993608                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1011891                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2005499                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       993608                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1011891                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2005499                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        15053                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       273771                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       288824                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           42                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           42                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       115427                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       115427                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        15053                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       389198                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        404251                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        15053                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       389198                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       404251                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1161439993                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17964720233                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  19126160226                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       262498                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       262498                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9625411610                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9625411610                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1161439993                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  27590131843                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  28751571836                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1161439993                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  27590131843                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  28751571836                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1008661                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1100233                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2108894                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       840541                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       840541                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55443                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994400                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         26727783                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        26727783                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       995001                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       827094                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1822095                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       840946                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       840946                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           27                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           27                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       185467                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       185467                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       995001                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1012561                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2007562                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       995001                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1012561                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2007562                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        15052                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       273790                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       288842                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           35                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           35                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       115470                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       115470                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        15052                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       389260                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        404312                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        15052                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       389260                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       404312                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1147195743                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17910681229                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  19057876972                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       262998                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       262998                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9445420357                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9445420357                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1147195743                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  27356101586                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  28503297329                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1147195743                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  27356101586                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  28503297329                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1010053                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1100884                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2110937                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       840946                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       840946                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           62                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           62                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       300856                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       300856                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1008661                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1401089                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2409750                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1008661                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1401089                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2409750                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014924                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248830                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.136955                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.677419                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.677419                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383662                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383662                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014924                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.277782                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.167756                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014924                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.277782                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.167756                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77156.712483                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65619.514971                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 66220.813457                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  6249.952381                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  6249.952381                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83389.602173                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83389.602173                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77156.712483                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70889.706121                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71123.069172                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77156.712483                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70889.706121                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71123.069172                       # average overall miss latency
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       300937                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       300937                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1010053                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1401821                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2411874                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1010053                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1401821                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2411874                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014902                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248700                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.136831                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.564516                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.564516                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383702                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383702                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014902                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.277682                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.167634                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014902                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.277682                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.167634                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76215.502458                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65417.587308                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 65980.283241                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  7514.228571                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  7514.228571                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81799.777925                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81799.777925                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76215.502458                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70277.196696                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70498.271951                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76215.502458                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70277.196696                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70498.271951                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1074,72 +1110,72 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        75916                       # number of writebacks
-system.cpu.l2cache.writebacks::total            75916                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        75935                       # number of writebacks
+system.cpu.l2cache.writebacks::total            75935                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15052                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273771                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       288823                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           42                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           42                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115427                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       115427                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        15052                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       389198                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       404250                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15052                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       389198                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       404250                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    971628757                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14552447267                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15524076024                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       573037                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       573037                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8203174390                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8203174390                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    971628757                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22755621657                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  23727250414                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    971628757                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22755621657                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  23727250414                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334007000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334007000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882413000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882413000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216420000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216420000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014923                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248830                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136955                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.677419                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.677419                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383662                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383662                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014923                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277782                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.167756                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014923                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277782                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.167756                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64551.472030                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53155.547034                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53749.445245                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13643.738095                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13643.738095                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71068.072375                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71068.072375                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64551.472030                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58467.981996                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58694.497004                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64551.472030                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58467.981996                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58694.497004                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15051                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273790                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       288841                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           35                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           35                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115470                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       115470                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15051                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       389260                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       404311                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15051                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389260                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       404311                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    957328507                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14497719271                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15455047778                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       500032                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       500032                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8018115143                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8018115143                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    957328507                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22515834414                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  23473162921                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    957328507                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22515834414                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  23473162921                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333977500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333977500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882390000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882390000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216367500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216367500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014901                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248700                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136831                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.564516                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.564516                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383702                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383702                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014901                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277682                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.167634                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014901                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277682                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.167634                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63605.641286                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52951.967826                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53507.112141                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14286.628571                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14286.628571                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69438.946419                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69438.946419                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63605.641286                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57842.661496                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58057.195874                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63605.641286                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57842.661496                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58057.195874                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1147,168 +1183,168 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1400496                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.994513                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            11811358                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1401008                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.430614                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          25856000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.994513                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements           1401230                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994514                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            11803041                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1401742                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.420266                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          25812000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994514                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          417                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63734677                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63734677                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7206132                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7206132                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4203012                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4203012                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       186466                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       186466                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215515                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215515                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11409144                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11409144                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11409144                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11409144                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1805019                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1805019                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1944584                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1944584                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22688                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22688                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3749603                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3749603                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3749603                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3749603                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  40356893890                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  40356893890                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  77719104532                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  77719104532                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    321753501                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    321753501                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        13000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 118075998422                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 118075998422                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 118075998422                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 118075998422                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9011151                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9011151                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6147596                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6147596                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209154                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       209154                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215516                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215516                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15158747                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15158747                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15158747                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15158747                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200309                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.200309                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316316                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.316316                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108475                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108475                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000005                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.247356                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.247356                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.247356                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.247356                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22358.154618                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22358.154618                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39966.956702                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39966.956702                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14181.659952                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14181.659952                       # average LoadLockedReq miss latency
+system.cpu.dcache.tags.tag_accesses          63715251                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63715251                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7198260                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7198260                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4203038                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4203038                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       186010                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       186010                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215511                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215511                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11401298                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11401298                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11401298                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11401298                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1808147                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1808147                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1944666                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1944666                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22743                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22743                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3752813                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3752813                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3752813                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3752813                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  40323855155                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  40323855155                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  76523868035                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  76523868035                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    322545000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    322545000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        26000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 116847723190                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 116847723190                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 116847723190                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 116847723190                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9006407                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9006407                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6147704                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6147704                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       208753                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       208753                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215513                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215513                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15154111                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15154111                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15154111                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15154111                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200762                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.200762                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316324                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.316324                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108947                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108947                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.247643                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.247643                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.247643                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.247643                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        13000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31490.266682                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31490.266682                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      3050951                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          663                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             86776                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31136.036672                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31136.036672                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      3013190                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          829                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             80012                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    35.158926                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    94.714286                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    37.659226                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   118.428571                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       840541                       # number of writebacks
-system.cpu.dcache.writebacks::total            840541                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       721694                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       721694                       # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       840946                       # number of writebacks
+system.cpu.dcache.writebacks::total            840946                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       724204                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       724204                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1644324                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total      1644324                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5123                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5123                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2366018                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2366018                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2366018                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2366018                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083325                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1083325                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300260                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       300260                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17565                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17565                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1383585                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1383585                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1383585                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1383585                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27323478009                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27323478009                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11844407335                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11844407335                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    200869499                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    200869499                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        11000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39167885344                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  39167885344                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39167885344                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  39167885344                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424097000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424097000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997590998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997590998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421687998                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421687998                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120220                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120220                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048842                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048842                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083981                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083981                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000005                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091273                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091273                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091273                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091273                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5146                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5146                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2368528                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2368528                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2368528                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2368528                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083943                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1083943                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300342                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       300342                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17597                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17597                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1384285                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1384285                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1384285                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1384285                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27275514507                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  27275514507                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11674414609                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11674414609                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    201282500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    201282500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  38949929116                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  38949929116                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  38949929116                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  38949929116                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424067500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424067500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997567998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997567998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421635498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421635498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120352                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120352                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048854                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048854                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.084296                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.084296                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091347                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091347                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091347                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091347                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1329,11 +1365,11 @@ system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # nu
 system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73294     49.32%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                148598                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1817851866500     97.72%     97.72% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                64172000      0.00%     97.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               559556500      0.03%     97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             41715361500      2.24%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1860190956500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1817873983000     97.73%     97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                64184500      0.00%     97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               553817500      0.03%     97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             41694992500      2.24%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1860186977500                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
@@ -1387,19 +1423,19 @@ system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # nu
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
 system.cpu.kern.callpal::total                 191963                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
+system.cpu.kern.mode_switch::kernel              5852                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
 system.cpu.kern.mode_good::kernel                1910                      
 system.cpu.kern.mode_good::user                  1740                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326440                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326384                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle       0.081184                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::total      0.394384                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29573655500      1.59%      1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2713841000      0.15%      1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1827903452000     98.26%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel        29561208000      1.59%      1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2704677000      0.15%      1.73% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1827921084500     98.27%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index d0170b803..14b9e6b0f 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,146 +1,146 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.842694                       # Number of seconds simulated
-sim_ticks                                1842693728000                       # Number of ticks simulated
-final_tick                               1842693728000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.843672                       # Number of seconds simulated
+sim_ticks                                1843672389000                       # Number of ticks simulated
+final_tick                               1843672389000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 239111                       # Simulator instruction rate (inst/s)
-host_op_rate                                   239111                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5964368765                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 346744                       # Number of bytes of host memory used
-host_seconds                                   308.95                       # Real time elapsed on the host
-sim_insts                                    73873335                       # Number of instructions simulated
-sim_ops                                      73873335                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 195444                       # Simulator instruction rate (inst/s)
+host_op_rate                                   195444                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4916161077                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347768                       # Number of bytes of host memory used
+host_seconds                                   375.02                       # Real time elapsed on the host
+sim_insts                                    73296119                       # Number of instructions simulated
+sim_ops                                      73296119                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           489024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20126208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           488384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20120896                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           143680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2232768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           285376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2509376                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28438784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       489024                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       143680                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       285376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           147840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2228608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           281856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2520448                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28440384                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       488384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       147840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       281856                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          918080                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7463104                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7463104                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7641                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            314472                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::writebacks      7465920                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7465920                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7631                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            314389                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2245                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             34887                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4459                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             39209                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                444356                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116611                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116611                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              265385                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            10922167                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1439388                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               77973                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1211687                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              154869                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1361798                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15433267                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         265385                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          77973                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         154869                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             498227                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4050105                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4050105                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4050105                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             265385                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10922167                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1439388                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              77973                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1211687                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             154869                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1361798                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19483372                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         97691                       # Number of read requests accepted
-system.physmem.writeReqs                        44282                       # Number of write requests accepted
-system.physmem.readBursts                       97691                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      44282                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  6250944                       # Total number of bytes read from DRAM
+system.physmem.num_reads::cpu1.inst              2310                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             34822                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4404                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             39382                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                444381                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116655                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116655                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              264897                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            10913488                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1438624                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               80188                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1208787                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              152877                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1367080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15425942                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         264897                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          80188                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         152877                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             497963                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4049483                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4049483                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4049483                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             264897                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10913488                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1438624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              80188                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1208787                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             152877                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1367080                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19475425                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         98065                       # Number of read requests accepted
+system.physmem.writeReqs                        44647                       # Number of write requests accepted
+system.physmem.readBursts                       98065                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      44647                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  6274880                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                      1280                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2832576                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   6252224                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2834048                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   2856000                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   6276160                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                2857408                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                       20                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             39                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                6114                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5899                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                6060                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                6276                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5549                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                6233                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                6082                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                6075                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6372                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                6119                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               6443                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5953                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5846                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs             43                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                6107                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5922                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                6220                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                6321                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5635                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                6235                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5931                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                6044                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6533                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                6108                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               6507                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5966                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5866                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               6273                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6335                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6042                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2746                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2526                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2727                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3010                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                2533                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                2968                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                2994                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2697                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3092                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2617                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               2969                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2522                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2428                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               2745                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6336                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               6041                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2748                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2555                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2839                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                3065                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                2620                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                2963                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                2854                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2670                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                3259                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2627                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               3029                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2539                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               2431                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               2744                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               2948                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2737                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2734                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1841681402500                       # Total gap between requests
+system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1842660063500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   97691                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   98065                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  44282                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     65712                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      9632                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5477                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1935                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       488                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      1780                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1567                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1574                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1624                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1032                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      859                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      829                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      762                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      744                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      617                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      601                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      609                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      699                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      495                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  44647                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     65397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7824                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      8078                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      2035                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       831                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      1795                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      1629                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1651                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1059                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       913                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      873                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      850                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      660                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      661                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      817                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      795                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      896                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      513                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      393                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      373                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -153,13 +153,13 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        77                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                        52                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        44                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        43                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        42                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        41                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        38                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                        36                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                        36                       # What write queue length does an incoming req see
@@ -168,376 +168,368 @@ system.physmem.wrQLenPdf::11                       35                       # Wh
 system.physmem.wrQLenPdf::12                       35                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                       35                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      523                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      562                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     1375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     1510                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     1616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     1649                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     1665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     1674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     1985                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     1867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     1882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     2065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     2008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      918                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      462                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      508                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      598                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      690                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      719                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      789                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      770                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      717                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       10                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        15110                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      511.250298                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     300.938727                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     421.415256                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           3831     25.35%     25.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         2740     18.13%     43.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1074      7.11%     50.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          703      4.65%     55.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          520      3.44%     58.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          360      2.38%     61.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          225      1.49%     62.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          226      1.50%     64.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         5431     35.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          15110                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          2571                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        37.985220                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      914.533013                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           2569     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                      569                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     1573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     1674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     1688                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     1720                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     1786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     1841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     1914                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     2036                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     2069                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     2187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     2080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     2119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     2107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     2073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      302                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      393                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      364                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      505                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      827                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      929                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      863                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      793                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      814                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        21868                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      417.545272                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     236.447646                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     397.078129                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           6878     31.45%     31.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4663     21.32%     52.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1715      7.84%     60.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          976      4.46%     65.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          897      4.10%     69.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          495      2.26%     71.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          365      1.67%     73.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          382      1.75%     74.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5497     25.14%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          21868                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2618                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        37.446906                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      907.093650                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           2616     99.92%     99.92% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.04%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.04%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            2571                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          2571                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.214702                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.506808                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        4.396297                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1                  28      1.09%      1.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2                   8      0.31%      1.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3                   1      0.04%      1.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4                   1      0.04%      1.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5                   1      0.04%      1.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6                   1      0.04%      1.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7                   2      0.08%      1.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8                   2      0.08%      1.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10                  1      0.04%      1.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15                  1      0.04%      1.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               1798     69.93%     71.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 69      2.68%     74.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 74      2.88%     77.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                370     14.39%     91.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 34      1.32%     93.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 19      0.74%     93.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 12      0.47%     94.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  7      0.27%     94.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 34      1.32%     95.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 15      0.58%     96.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  5      0.19%     96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 15      0.58%     97.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 11      0.43%     97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 14      0.54%     98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.16%     98.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  5      0.19%     98.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  6      0.23%     98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  3      0.12%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.04%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.04%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  2      0.08%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  2      0.08%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  3      0.12%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  4      0.16%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  3      0.12%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  5      0.19%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  2      0.08%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  1      0.04%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  2      0.08%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  2      0.08%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  2      0.08%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            2571                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3372876000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5050468500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    488355000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1189237500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       34533.03                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    12175.95                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            2618                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2618                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.045455                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.392541                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        4.534822                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-1                25      0.95%      0.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2-3                 9      0.34%      1.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-5                 2      0.08%      1.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6-7                 3      0.11%      1.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-9                 2      0.08%      1.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10-11               1      0.04%      1.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14-15               1      0.04%      1.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            1908     72.88%     74.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19             472     18.03%     92.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              41      1.57%     94.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              56      2.14%     96.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              26      0.99%     97.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              16      0.61%     97.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              10      0.38%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31              14      0.53%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               7      0.27%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               1      0.04%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39               1      0.04%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41               3      0.11%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               4      0.15%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               1      0.04%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               1      0.04%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57              11      0.42%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59               1      0.04%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               1      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-65               1      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2618                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2942753000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4781096750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    490225000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       30014.31                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  51708.99                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.39                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.54                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.39                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.54                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  48764.31                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.40                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.55                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.40                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.55                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         4.13                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      85060                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     35225                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         4.22                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      85384                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     35418                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   87.09                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.55                       # Row buffer hit rate for writes
-system.physmem.avgGap                     12972053.86                       # Average gap between requests
-system.physmem.pageHitRate                      84.74                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.21                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     19527312                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               44337                       # Transaction distribution
-system.membus.trans_dist::ReadResp              44306                       # Transaction distribution
-system.membus.trans_dist::WriteReq               3779                       # Transaction distribution
-system.membus.trans_dist::WriteResp              3779                       # Transaction distribution
-system.membus.trans_dist::Writeback             44282                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               42                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              42                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             56476                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            56476                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           31                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        13428                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       189189                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           62                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       202679                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        50712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        50712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 253391                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        15748                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      6926464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total      6942212                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2159808                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      2159808                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total             9102020                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               35972872                       # Total data (bytes)
-system.membus.snoop_data_through_bus             9984                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            12574500                       # Layer occupancy (ticks)
+system.physmem.writeRowHitRate                  79.33                       # Row buffer hit rate for writes
+system.physmem.avgGap                     12911738.77                       # Average gap between requests
+system.physmem.pageHitRate                      84.66                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1768578867000                       # Time in different power states
+system.physmem.memoryStateTime::REF       61564100000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       13524513000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     19519346                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               44419                       # Transaction distribution
+system.membus.trans_dist::ReadResp              44389                       # Transaction distribution
+system.membus.trans_dist::WriteReq               3765                       # Transaction distribution
+system.membus.trans_dist::WriteResp              3765                       # Transaction distribution
+system.membus.trans_dist::Writeback             44647                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               46                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              46                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             56746                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            56746                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           30                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        13356                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       189542                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           60                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       202958                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        51481                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        51481                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 254439                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        15715                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      6940992                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total      6956707                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2192576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      2192576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total             9149283                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               35977232                       # Total data (bytes)
+system.membus.snoop_data_through_bus            10048                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            12506000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           513408250                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           516947250                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               40000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               37500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          761373958                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          762242703                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          153163000                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          155440000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   337430                       # number of replacements
-system.l2c.tags.tagsinuse                65422.148259                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2473441                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402593                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.143775                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   337456                       # number of replacements
+system.l2c.tags.tagsinuse                65422.465864                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2473240                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   402619                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.142879                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54880.563920                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2458.853214                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2711.613848                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      517.416897                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      618.305247                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2161.633442                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     2073.761691                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.837411                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.037519                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.041376                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.007895                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.009435                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.032984                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.031643                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998263                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   54816.531838                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2443.286445                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2722.487240                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      580.950396                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      624.587700                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2109.099829                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     2125.522416                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.836434                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.037282                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.041542                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.008865                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.009530                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.032182                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.032433                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.998268                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1047                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5588                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2973                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55387                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         1026                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5608                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2978                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55383                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 26153114                       # Number of tag accesses
-system.l2c.tags.data_accesses                26153114                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             521024                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             493028                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             125251                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              84722                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             291154                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             239311                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1754490                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          836107                       # number of Writeback hits
-system.l2c.Writeback_hits::total               836107                       # number of Writeback hits
+system.l2c.tags.tag_accesses                 26151122                       # Number of tag accesses
+system.l2c.tags.data_accesses                26151122                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             519486                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             493287                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             124779                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              84464                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             292648                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             239510                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1754174                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          836240                       # number of Writeback hits
+system.l2c.Writeback_hits::total               836240                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu2.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   7                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu2.data             1                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            93137                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            26426                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            67420                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               186983                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              521024                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              586165                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              125251                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              111148                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              291154                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              306731                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1941473                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             521024                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             586165                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             125251                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             111148                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             291154                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             306731                       # number of overall hits
-system.l2c.overall_hits::total                1941473                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst             7641                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           238596                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             2245                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data            16796                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             4459                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data            17833                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               287570                       # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu0.data            92910                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            26171                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            67815                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               186896                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              519486                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              586197                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              124779                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              110635                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              292648                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              307325                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1941070                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             519486                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             586197                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             124779                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             110635                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             292648                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             307325                       # number of overall hits
+system.l2c.overall_hits::total                1941070                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst             7631                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           238513                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2310                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data            16826                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst             4404                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data            17896                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               287580                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data             9                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                17                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          76153                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          18140                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          21473                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115766                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst              7641                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            314749                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2245                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             34936                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              4459                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             39306                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                403336                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst             7641                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           314749                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2245                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            34936                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             4459                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            39306                       # number of overall misses
-system.l2c.overall_misses::total               403336                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst    162937747                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data   1122716750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst    340229750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data   1192796250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2818680497                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data       286997                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       286997                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1236065740                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   1785443227                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   3021508967                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    162937747                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   2358782490                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    340229750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   2978239477                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      5840189464                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    162937747                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   2358782490                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    340229750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   2978239477                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     5840189464                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         528665                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         731624                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         127496                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         101518                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst         295613                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data         257144                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2042060                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       836107                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           836107                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_misses::cpu2.data            12                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                20                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          76151                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          18045                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          21583                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             115779                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst              7631                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            314664                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2310                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             34871                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              4404                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             39479                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                403359                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst             7631                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           314664                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2310                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            34871                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             4404                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            39479                       # number of overall misses
+system.l2c.overall_misses::total               403359                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.inst    168327497                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data   1121769250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    335079500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data   1193124499                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2818300746                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data       318496                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       318496                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1237365240                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   1750671726                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2988036966                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    168327497                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   2359134490                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    335079500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   2943796225                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      5806337712                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    168327497                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   2359134490                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    335079500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   2943796225                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     5806337712                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         527117                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         731800                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         127089                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         101290                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst         297052                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data         257406                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2041754                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       836240                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           836240                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data           11                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           12                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              24                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           15                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              27                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu2.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       169290                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        44566                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        88893                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           302749                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          528665                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          900914                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          127496                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          146084                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          295613                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          346037                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2344809                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         528665                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         900914                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         127496                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         146084                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         295613                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         346037                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2344809                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014453                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.326118                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.017608                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.165448                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.015084                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.069350                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.140823                       # miss rate for ReadReq accesses
+system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       169061                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        44216                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        89398                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           302675                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          527117                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          900861                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          127089                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          145506                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          297052                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          346804                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2344429                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         527117                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         900861                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         127089                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         145506                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         297052                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         346804                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2344429                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014477                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.325926                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.018176                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.166117                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.014826                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.069524                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.140849                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.727273                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.750000                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.708333                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.449838                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.407037                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.241560                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.382383                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014453                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.349366                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.017608                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.239150                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.015084                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.113589                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.172012                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014453                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.349366                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.017608                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.239150                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.015084                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.113589                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.172012                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72578.061024                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 66844.293284                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76301.805338                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 66887.021253                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total  9801.719571                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 31888.555556                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 16882.176471                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68140.338479                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83148.289806                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 26100.141380                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72578.061024                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 67517.245535                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 76301.805338                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 75770.606956                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 14479.712855                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72578.061024                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 67517.245535                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 76301.805338                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 75770.606956                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 14479.712855                       # average overall miss latency
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.800000                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.740741                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.450435                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.408110                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.241426                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.382519                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014477                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.349293                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.018176                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.239653                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.014826                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.113837                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.172050                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014477                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.349293                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.018176                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.239653                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.014826                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.113837                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.172050                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72869.046320                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 66668.801260                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76085.263397                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 66669.898245                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total  9800.058231                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26541.333333                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 15924.800000                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68571.085619                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81113.456239                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 25808.108258                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 72869.046320                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 67653.192911                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 76085.263397                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 74566.129461                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 14394.962582                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 72869.046320                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 67653.192911                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 76085.263397                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 74566.129461                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 14394.962582                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -546,97 +538,97 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               75099                       # number of writebacks
-system.l2c.writebacks::total                    75099                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2245                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data        16796                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         4459                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data        17833                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           41333                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data            9                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total            9                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        18140                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        21473                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         39613                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2245                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        34936                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         4459                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        39306                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            80946                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2245                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        34936                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         4459                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        39306                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           80946                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    134357753                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    912417250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    284084750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data    973268750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   2304128503                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       241006                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       241006                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1008170260                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1522069773                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   2530240033                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    134357753                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1920587510                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    284084750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   2495338523                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   4834368536                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    134357753                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1920587510                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    284084750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   2495338523                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   4834368536                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    279416000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    295991000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    575407000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    345820000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    406371500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total    752191500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    625236000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data    702362500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1327598500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.017608                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.165448                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.015084                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.069350                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.020241                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.750000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.375000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.407037                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.241560                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.130844                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017608                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.239150                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.015084                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.113589                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.034521                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017608                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.239150                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.015084                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.113589                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.034521                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59847.551448                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54323.484758                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63710.417134                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54576.837885                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 55745.493988                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26778.444444                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26778.444444                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55577.191841                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70882.958739                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63873.981597                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59847.551448                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 54974.453572                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63710.417134                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63484.926551                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59723.377758                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59847.551448                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 54974.453572                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63710.417134                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63484.926551                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59723.377758                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks               75143                       # number of writebacks
+system.l2c.writebacks::total                    75143                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu1.inst         2310                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data        16826                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         4404                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data        17896                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           41436                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           12                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           12                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        18045                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        21583                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         39628                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2310                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        34871                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         4404                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        39479                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            81064                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2310                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        34871                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         4404                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        39479                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           81064                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    138909503                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    911100250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    279632500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    972656001                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   2302298254                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       279009                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       279009                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1010621760                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1486000274                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   2496622034                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    138909503                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1921722010                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    279632500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   2458656275                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   4798920288                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    138909503                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1921722010                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    279632500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   2458656275                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   4798920288                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    277729500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    292749000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    570478500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    344555500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    403769000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total    748324500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    622285000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    696518000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1318803000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018176                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.166117                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014826                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.069524                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.020294                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.444444                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.408110                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.241426                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.130926                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018176                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.239653                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014826                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.113837                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034577                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018176                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.239653                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014826                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.113837                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034577                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60133.983983                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54148.356710                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63495.118074                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54350.469435                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 55562.753499                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23250.750000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23250.750000                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56005.639235                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68850.496873                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63001.464470                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60133.983983                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55109.460870                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63495.118074                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62277.572254                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59199.154841                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60133.983983                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55109.460870                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63495.118074                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62277.572254                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59199.154841                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -648,14 +640,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.254944                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.262765                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1694864715000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.254944                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078434                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078434                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1694865594000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.262765                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078923                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078923                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -669,14 +661,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide      9303463                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total      9303463                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   5375933278                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   5375933278                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   5385236741                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5385236741                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   5385236741                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5385236741                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide      9418062                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total      9418062                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   5145673458                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   5145673458                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5155091520                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5155091520                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5155091520                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5155091520                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -693,56 +685,56 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 53777.242775                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 129378.448161                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 129378.448161                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 129064.990797                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129064.990797                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 129064.990797                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129064.990797                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        158120                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54439.664740                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 54439.664740                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 123836.962312                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 123836.962312                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 123549.227561                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 123549.227561                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 123549.227561                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 123549.227561                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        151978                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11558                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                11614                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.680568                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.085759                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide           69                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        16896                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        16896                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        16965                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        16965                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        16965                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        16965                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5714463                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      5714463                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   4496386278                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   4496386278                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   4502100741                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4502100741                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   4502100741                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4502100741                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.398844                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide     0.406623                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total     0.406623                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide     0.406591                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.406591                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide     0.406591                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.406591                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 266121.346946                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 266121.346946                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 265375.817330                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 265375.817330                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 265375.817330                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 265375.817330                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::tsunami.ide        17152                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        17152                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        17222                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        17222                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        17222                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        17222                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5777062                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      5777062                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   4252886458                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   4252886458                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   4258663520                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4258663520                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   4258663520                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4258663520                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::tsunami.ide     0.412784                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total     0.412784                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide     0.412750                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.412750                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide     0.412750                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.412750                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82529.457143                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 82529.457143                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247952.801889                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 247952.801889                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247280.427360                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 247280.427360                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247280.427360                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 247280.427360                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -760,22 +752,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4928404                       # DTB read hits
+system.cpu0.dtb.read_hits                     4916751                       # DTB read hits
 system.cpu0.dtb.read_misses                      6099                       # DTB read misses
 system.cpu0.dtb.read_acv                          126                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  428233                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3518338                       # DTB write hits
+system.cpu0.dtb.write_hits                    3511411                       # DTB write hits
 system.cpu0.dtb.write_misses                      670                       # DTB write misses
 system.cpu0.dtb.write_acv                          84                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 163777                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8446742                       # DTB hits
+system.cpu0.dtb.data_hits                     8428162                       # DTB hits
 system.cpu0.dtb.data_misses                      6769                       # DTB misses
 system.cpu0.dtb.data_acv                          210                       # DTB access violations
 system.cpu0.dtb.data_accesses                  592010                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2763962                       # ITB hits
+system.cpu0.itb.fetch_hits                    2761691                       # ITB hits
 system.cpu0.itb.fetch_misses                     3034                       # ITB misses
 system.cpu0.itb.fetch_acv                         104                       # ITB acv
-system.cpu0.itb.fetch_accesses                2766996                       # ITB accesses
+system.cpu0.itb.fetch_accesses                2764725                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -788,52 +780,87 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       928692350                       # number of cpu cycles simulated
+system.cpu0.numCycles                       928579533                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   34273964                       # Number of instructions committed
-system.cpu0.committedOps                     34273964                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             32130742                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                169948                       # Number of float alu accesses
-system.cpu0.num_func_calls                     813899                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4819398                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    32130742                       # number of integer instructions
-system.cpu0.num_fp_insts                       169948                       # number of float instructions
-system.cpu0.num_int_register_reads           45237353                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          23423813                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               87792                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              89256                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8476912                       # number of memory refs
-system.cpu0.num_load_insts                    4949798                       # Number of load instructions
-system.cpu0.num_store_insts                   3527114                       # Number of store instructions
-system.cpu0.num_idle_cycles              904863863.789935                       # Number of idle cycles
-system.cpu0.num_busy_cycles              23828486.210065                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.025658                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.974342                       # Percentage of idle cycles
-system.cpu0.Branches                          5897308                       # Number of branches fetched
+system.cpu0.committedInsts                   33817210                       # Number of instructions committed
+system.cpu0.committedOps                     33817210                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             31677975                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                169596                       # Number of float alu accesses
+system.cpu0.num_func_calls                     812570                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4683135                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    31677975                       # number of integer instructions
+system.cpu0.num_fp_insts                       169596                       # number of float instructions
+system.cpu0.num_int_register_reads           44495639                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          23114141                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               87595                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              89102                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8458293                       # number of memory refs
+system.cpu0.num_load_insts                    4938120                       # Number of load instructions
+system.cpu0.num_store_insts                   3520173                       # Number of store instructions
+system.cpu0.num_idle_cycles              904460149.841647                       # Number of idle cycles
+system.cpu0.num_busy_cycles              24119383.158353                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.025974                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.974026                       # Percentage of idle cycles
+system.cpu0.Branches                          5759211                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              1618304      4.78%      4.78% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 23033604     68.10%     72.88% # Class of executed instruction
+system.cpu0.op_class::IntMult                   32432      0.10%     72.98% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     72.98% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  12174      0.04%     73.01% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     73.01% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     73.01% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     73.01% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1606      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     73.02% # Class of executed instruction
+system.cpu0.op_class::MemRead                 5072252     15.00%     88.02% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3523323     10.42%     98.43% # Class of executed instruction
+system.cpu0.op_class::IprAccess                530494      1.57%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                  33824189                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6415                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211374                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   74800     40.97%     40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce                    6417                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211389                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   74803     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1879      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105691     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182573                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    73433     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::22                   1880      1.03%     42.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 105703     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182589                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    73436     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1879      1.26%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   73433     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               148948                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1819462416000     98.74%     98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               38889500      0.00%     98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              365010500      0.02%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22826642500      1.24%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1842692958500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_good::22                    1880      1.26%     50.70% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   73436     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               148955                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1820445327500     98.74%     98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               38826000      0.00%     98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              365496000      0.02%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22821970000      1.24%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1843671619500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.981725                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694790                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815827                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694739                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815794                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
@@ -869,33 +896,33 @@ system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # nu
 system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 4176      2.17%      2.17% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175314     91.20%     93.41% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6783      3.53%     96.94% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175328     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6784      3.53%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
-system.cpu0.kern.callpal::rti                    5176      2.69%     99.64% # number of callpals executed
+system.cpu0.kern.callpal::rti                    5177      2.69%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192229                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1737                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle               2096                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1907                      
-system.cpu0.kern.mode_good::user                 1737                      
-system.cpu0.kern.mode_good::idle                  170                      
-system.cpu0.kern.mode_switch_good::kernel     0.322020                       # fraction of useful protection mode switches
+system.cpu0.kern.callpal::total                192243                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             5923                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1739                       # number of protection mode switches
+system.cpu0.kern.mode_switch::idle               2094                       # number of protection mode switches
+system.cpu0.kern.mode_good::kernel               1908                      
+system.cpu0.kern.mode_good::user                 1739                      
+system.cpu0.kern.mode_good::idle                  169                      
+system.cpu0.kern.mode_switch_good::kernel     0.322134                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      0.081107                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.390979                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29759204500      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2578304000      0.14%      1.75% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1810355445500     98.25%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    4177                       # number of times the context was actually changed
+system.cpu0.kern.mode_switch_good::idle      0.080707                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     0.391144                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel       29786667000      1.62%      1.62% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2578002500      0.14%      1.76% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1811306945500     98.24%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -927,458 +954,460 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   110509038                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq             784786                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            784740                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              3779                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             3779                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           372271                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              13                       # Transaction distribution
+system.toL2Bus.throughput                   110441912                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq             785832                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            785787                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq              3765                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp             3765                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           372222                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq              16                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             14                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           150355                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          133459                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           31                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       846229                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1370023                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               2216252                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27078976                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     55338308                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total           82417284                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             203623496                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           10816                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         2138093500                       # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::UpgradeResp             17                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           150766                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          133614                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           30                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       848294                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1370287                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               2218581                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27145024                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     55347363                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total           82492387                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             203607824                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus           10880                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         2138460500                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           243000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           247500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1905810483                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1910550337                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2232783145                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        2233740752                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.iobus.throughput                       1469145                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq                 3004                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                3004                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               20675                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              20675                       # Transaction distribution
+system.iobus.throughput                       1468369                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq                 2983                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                2983                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               20917                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              20917                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         2330                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          136                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio           66                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio         8488                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         2374                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio         8382                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         2408                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf           34                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        13428                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        33930                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        33930                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                   47358                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        13356                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        34444                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        34444                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                   47800                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio         9320                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio          544                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio           61                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         4244                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         1548                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         4191                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         1568                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf           31                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        15748                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      1082792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      1082792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              1098540                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2707184                       # Total data (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        15715                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      1099184                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      1099184                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              1114899                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2707192                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy              2199000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy               57000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6326000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6246000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             1789000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             1819000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               20000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           154493741                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           156921520                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             9649000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             9591000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            17628000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            17887000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           951123                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.189701                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           44044625                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           951634                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            46.283156                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10406456250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   252.370031                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    94.623296                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   164.196374                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.492910                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.184811                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.320696                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998417                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           950608                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.189792                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           43374256                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           951119                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            45.603396                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10403794250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   251.164377                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    98.345392                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   161.680023                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.490555                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.192081                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.315781                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998418                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         45964526                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        45964526                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     33752258                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      8060384                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2231983                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       44044625                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     33752258                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      8060384                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2231983                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        44044625                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     33752258                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      8060384                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2231983                       # number of overall hits
-system.cpu0.icache.overall_hits::total       44044625                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       528685                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       127496                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       311915                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       968096                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       528685                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       127496                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       311915                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        968096                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       528685                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       127496                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       311915                       # number of overall misses
-system.cpu0.icache.overall_misses::total       968096                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1806037753                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4386195216                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6192232969                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1806037753                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4386195216                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6192232969                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1806037753                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4386195216                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6192232969                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     34280943                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      8187880                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      2543898                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     45012721                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     34280943                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      8187880                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      2543898                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     45012721                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     34280943                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      8187880                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      2543898                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     45012721                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015422                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015571                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122613                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.021507                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015422                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015571                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122613                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.021507                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015422                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015571                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122613                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.021507                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.446390                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14062.149034                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6396.300541                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14165.446390                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14062.149034                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6396.300541                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14165.446390                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14062.149034                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6396.300541                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         3438                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         45292775                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        45292775                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     33297051                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      7835821                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2241384                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       43374256                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     33297051                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      7835821                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2241384                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        43374256                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     33297051                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      7835821                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2241384                       # number of overall hits
+system.cpu0.icache.overall_hits::total       43374256                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       527138                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       127089                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       313001                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       967228                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       527138                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       127089                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       313001                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        967228                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       527138                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       127089                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       313001                       # number of overall misses
+system.cpu0.icache.overall_misses::total       967228                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1805503003                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4394679722                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6200182725                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1805503003                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4394679722                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6200182725                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1805503003                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4394679722                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6200182725                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     33824189                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      7962910                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      2554385                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     44341484                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     33824189                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      7962910                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      2554385                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     44341484                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     33824189                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      7962910                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      2554385                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     44341484                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015585                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015960                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122535                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.021813                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015585                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015960                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122535                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.021813                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015585                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015960                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122535                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.021813                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14206.603270                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14040.465436                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6410.259758                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14206.603270                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14040.465436                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6410.259758                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14206.603270                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14040.465436                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6410.259758                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         2211                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              178                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              139                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.314607                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.906475                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16291                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        16291                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        16291                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        16291                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        16291                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        16291                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       127496                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       295624                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       423120                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       127496                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       295624                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       423120                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       127496                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       295624                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       423120                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1550167247                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3614174758                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5164342005                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1550167247                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3614174758                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5164342005                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1550167247                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3614174758                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5164342005                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116209                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009400                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116209                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009400                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116209                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009400                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12158.555931                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12225.579648                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12205.383827                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12158.555931                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12225.579648                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12205.383827                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12158.555931                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12225.579648                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12205.383827                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        15937                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        15937                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        15937                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        15937                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        15937                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        15937                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       127089                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       297064                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       424153                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       127089                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       297064                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       424153                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       127089                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       297064                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       424153                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1550405997                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3623912160                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5174318157                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1550405997                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3623912160                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5174318157                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1550405997                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3623912160                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5174318157                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015960                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116296                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009566                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015960                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116296                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009566                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015960                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116296                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009566                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12199.372070                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12199.095683                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.178497                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12199.372070                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12199.095683                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.178497                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12199.372070                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12199.095683                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.178497                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1392490                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997811                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13295207                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1393002                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.544284                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1392627                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.997813                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           13291421                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1393139                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.540628                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   249.168016                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   132.479618                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   130.350177                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.486656                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.258749                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.254590                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   251.446594                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   129.524111                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   131.027107                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.491107                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.252977                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.255912                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          266                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63289936                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63289936                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4090319                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1090270                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2387407                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7567996                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3221527                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       836656                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1285562                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5343745                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117421                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19406                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        47293                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       184120                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       126604                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21447                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        51238                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199289                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7311846                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1926926                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      3672969                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12911741                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7311846                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1926926                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      3672969                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12911741                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       721875                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        99348                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       531757                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1352980                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       169301                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        44567                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       593518                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       807386                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9749                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2170                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         6797                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        18716                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses         63293161                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63293161                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4078776                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1086651                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2400445                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7565872                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3215108                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       831895                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1295006                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5342009                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117088                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19357                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        47741                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       184186                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       126296                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21393                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        51592                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       199281                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7293884                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1918546                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      3695451                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12907881                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7293884                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1918546                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      3695451                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12907881                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       722029                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        99123                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       533441                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1354593                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       169072                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        44217                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       597048                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       810337                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9771                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2167                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         6787                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        18725                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu2.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       891176                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       143915                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1125275                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2160366                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       891176                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       143915                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1125275                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2160366                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2256659500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9313664253                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  11570323753                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1642839260                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  18220741943                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  19863581203                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28601250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    101979747                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    130580997                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       891101                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       143340                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1130489                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2164930                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       891101                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       143340                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1130489                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2164930                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2252505500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9329560863                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11582066363                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1640569260                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  17995165012                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  19635734272                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28565250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    103170749                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    131735999                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        13000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   3899498760                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  27534406196                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  31433904956                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   3899498760                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  27534406196                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  31433904956                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4812194                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1189618                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      2919164                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8920976                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3390828                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       881223                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      1879080                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6151131                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       127170                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21576                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        54090                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       202836                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       126604                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21447                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        51239                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199290                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8203022                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      2070841                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      4798244                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15072107                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8203022                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      2070841                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      4798244                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15072107                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150010                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083513                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.182161                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.151663                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049929                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050574                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.315856                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.131258                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076661                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100575                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.125661                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092272                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000020                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.108640                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069496                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.234518                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.143335                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.108640                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069496                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.234518                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.143335                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22714.694810                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17514.887915                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  8551.733029                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36862.235735                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30699.560827                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 24602.335442                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13180.299539                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15003.640871                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6976.971415                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_latency::cpu1.data   3893074760                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  27324725875                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  31217800635                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   3893074760                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  27324725875                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  31217800635                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4800805                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1185774                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      2933886                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8920465                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3384180                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       876112                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      1892054                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6152346                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       126859                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21524                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        54528                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       202911                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       126297                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21393                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        51593                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199283                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8184985                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      2061886                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      4825940                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15072811                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8184985                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      2061886                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      4825940                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15072811                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150397                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083594                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.181821                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.151852                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049960                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050470                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.315555                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.131712                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077023                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100678                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.124468                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092282                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000019                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000010                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.108870                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069519                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.234253                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.143631                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.108870                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069519                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.234253                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.143631                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22724.347528                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17489.395946                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  8550.218673                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37102.681322                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30140.231626                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 24231.565721                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13181.933549                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15201.230146                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7035.300347                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27095.846576                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24469.046407                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14550.268314                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27095.846576                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24469.046407                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14550.268314                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       590264                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         1528                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            18149                       # number of cycles access was blocked
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total         6500                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27159.723455                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24170.713625                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14419.773681                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27159.723455                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24170.713625                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14419.773681                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       573016                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets          707                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            17657                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    32.523224                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   218.285714                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    32.452625                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          101                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       836107                       # number of writebacks
-system.cpu0.dcache.writebacks::total           836107                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       279755                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       279755                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       504860                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       504860                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1410                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1410                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       784615                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       784615                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       784615                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       784615                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        99348                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       252002                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       351350                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        44567                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        88658                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       133225                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2170                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5387                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7557                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       836240                       # number of writebacks
+system.cpu0.dcache.writebacks::total           836240                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       281234                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       281234                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       507881                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       507881                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1344                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1344                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       789115                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       789115                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       789115                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       789115                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        99123                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       252207                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       351330                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        44217                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        89167                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       133384                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2167                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5443                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7610                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       143915                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       340660                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       484575                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       143915                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       340660                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       484575                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2050446500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4236651993                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6287098493                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1545558740                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2630154746                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4175713486                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24259750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     65218003                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     89477753                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       143340                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       341374                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       484714                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       143340                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       341374                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       484714                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2046709500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4236520898                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6283230398                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1543938740                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2600534498                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4144473238                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24229750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     66769000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     90998750                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        11000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3596005240                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6866806739                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10462811979                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3596005240                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6866806739                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10462811979                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    298253500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    315317000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    613570500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    366377000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    431165001                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    797542001                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    664630500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    746482001                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1411112501                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083513                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086327                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3590648240                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6837055396                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10427703636                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3590648240                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6837055396                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10427703636                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    296463000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    311893000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    608356000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    365040500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    428466000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    793506500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    661503500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    740359000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1401862500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083594                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.085963                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.039385                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050574                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047182                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021659                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100575                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.099593                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.037257                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000020                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050470                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047127                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021680                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100678                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.099820                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.037504                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000019                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069496                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070997                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032150                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069496                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070997                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032150                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20639.031485                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16811.977655                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17894.118381                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34679.443086                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29666.299104                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31343.317591                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11179.608295                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12106.553369                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11840.380177                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069519                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070737                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032158                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069519                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070737                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032158                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20648.179535                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16797.792678                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17884.127168                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34917.310989                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29164.763848                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31071.742023                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11181.241347                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12266.948374                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.785808                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24987.007887                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20157.361413                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21591.728791                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24987.007887                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20157.361413                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21591.728791                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25049.869122                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20028.049576                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21513.105947                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25049.869122                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20028.049576                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21513.105947                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1393,22 +1422,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1209129                       # DTB read hits
+system.cpu1.dtb.read_hits                     1205243                       # DTB read hits
 system.cpu1.dtb.read_misses                      1367                       # DTB read misses
 system.cpu1.dtb.read_acv                           34                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  142945                       # DTB read accesses
-system.cpu1.dtb.write_hits                     903134                       # DTB write hits
+system.cpu1.dtb.write_hits                     897974                       # DTB write hits
 system.cpu1.dtb.write_misses                      185                       # DTB write misses
 system.cpu1.dtb.write_acv                          23                       # DTB write access violations
 system.cpu1.dtb.write_accesses                  58533                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2112263                       # DTB hits
+system.cpu1.dtb.data_hits                     2103217                       # DTB hits
 system.cpu1.dtb.data_misses                      1552                       # DTB misses
 system.cpu1.dtb.data_acv                           57                       # DTB access violations
 system.cpu1.dtb.data_accesses                  201478                       # DTB accesses
-system.cpu1.itb.fetch_hits                     860790                       # ITB hits
+system.cpu1.itb.fetch_hits                     859888                       # ITB hits
 system.cpu1.itb.fetch_misses                      693                       # ITB misses
 system.cpu1.itb.fetch_acv                          30                       # ITB acv
-system.cpu1.itb.fetch_accesses                 861483                       # ITB accesses
+system.cpu1.itb.fetch_accesses                 860581                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1421,29 +1450,64 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                       953612854                       # number of cpu cycles simulated
+system.cpu1.numCycles                       953622390                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    8186270                       # Number of instructions committed
-system.cpu1.committedOps                      8186270                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              7639715                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 45422                       # Number of float alu accesses
-system.cpu1.num_func_calls                     213980                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1089106                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     7639715                       # number of integer instructions
-system.cpu1.num_fp_insts                        45422                       # number of float instructions
-system.cpu1.num_int_register_reads           10757840                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           5542682                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               24502                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              24833                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      2119540                       # number of memory refs
-system.cpu1.num_load_insts                    1214044                       # Number of load instructions
-system.cpu1.num_store_insts                    905496                       # Number of store instructions
-system.cpu1.num_idle_cycles              923510145.865154                       # Number of idle cycles
-system.cpu1.num_busy_cycles              30102708.134846                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031567                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968433                       # Percentage of idle cycles
-system.cpu1.Branches                          1370105                       # Number of branches fetched
+system.cpu1.committedInsts                    7961300                       # Number of instructions committed
+system.cpu1.committedOps                      7961300                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              7416956                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 45099                       # Number of float alu accesses
+system.cpu1.num_func_calls                     213358                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1019863                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     7416956                       # number of integer instructions
+system.cpu1.num_fp_insts                        45099                       # number of float instructions
+system.cpu1.num_int_register_reads           10395465                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5394572                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               24307                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              24707                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      2110464                       # number of memory refs
+system.cpu1.num_load_insts                    1210140                       # Number of load instructions
+system.cpu1.num_store_insts                    900324                       # Number of store instructions
+system.cpu1.num_idle_cycles              923192460.103175                       # Number of idle cycles
+system.cpu1.num_busy_cycles              30429929.896825                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.031910                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.968090                       # Percentage of idle cycles
+system.cpu1.Branches                          1300058                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               413905      5.20%      5.20% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  5261386     66.07%     71.27% # Class of executed instruction
+system.cpu1.op_class::IntMult                    8416      0.11%     71.38% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     71.38% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   5003      0.06%     71.44% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     71.44% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     71.44% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     71.44% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                    810      0.01%     71.45% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1239389     15.56%     87.01% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 901545     11.32%     98.34% # Class of executed instruction
+system.cpu1.op_class::IprAccess                132455      1.66%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                   7962909                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
@@ -1461,35 +1525,35 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu2.branchPred.lookups                9158053                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          8481927                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           123683                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             7604727                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                6560922                       # Number of BTB hits
+system.cpu2.branchPred.lookups                9178120                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          8499449                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           123200                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             7695654                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                6571533                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            86.274261                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 280761                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             13305                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            85.392781                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 282084                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             12342                       # Number of incorrect RAS predictions.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3175061                       # DTB read hits
-system.cpu2.dtb.read_misses                     11717                       # DTB read misses
+system.cpu2.dtb.read_hits                     3191151                       # DTB read hits
+system.cpu2.dtb.read_misses                     11650                       # DTB read misses
 system.cpu2.dtb.read_acv                          122                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  217137                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2001578                       # DTB write hits
-system.cpu2.dtb.write_misses                     2618                       # DTB write misses
-system.cpu2.dtb.write_acv                         106                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  82142                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5176639                       # DTB hits
-system.cpu2.dtb.data_misses                     14335                       # DTB misses
-system.cpu2.dtb.data_acv                          228                       # DTB access violations
-system.cpu2.dtb.data_accesses                  299279                       # DTB accesses
-system.cpu2.itb.fetch_hits                     368924                       # ITB hits
-system.cpu2.itb.fetch_misses                     5740                       # ITB misses
-system.cpu2.itb.fetch_acv                         243                       # ITB acv
-system.cpu2.itb.fetch_accesses                 374664                       # ITB accesses
+system.cpu2.dtb.read_accesses                  216295                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2013879                       # DTB write hits
+system.cpu2.dtb.write_misses                     2626                       # DTB write misses
+system.cpu2.dtb.write_acv                         104                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  81955                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5205030                       # DTB hits
+system.cpu2.dtb.data_misses                     14276                       # DTB misses
+system.cpu2.dtb.data_acv                          226                       # DTB access violations
+system.cpu2.dtb.data_accesses                  298250                       # DTB accesses
+system.cpu2.itb.fetch_hits                     370022                       # ITB hits
+system.cpu2.itb.fetch_misses                     5569                       # ITB misses
+system.cpu2.itb.fetch_acv                         246                       # ITB acv
+system.cpu2.itb.fetch_accesses                 375591                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1502,270 +1566,305 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numCycles                        31279022                       # number of cpu cycles simulated
+system.cpu2.numCycles                        31335688                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           8287542                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      37055340                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                    9158053                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           6841683                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                      8878582                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 603474                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles               9658598                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles                9919                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1948                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        63764                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles        87901                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          585                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  2543899                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                85179                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples          27382085                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.353269                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.291783                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           8331242                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      37157937                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    9178120                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           6853617                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                      8899845                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 601293                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles               9656250                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles               10264                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1927                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        62491                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        87858                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          258                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2554389                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                85437                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples          27441825                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.354062                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.292990                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                18503503     67.58%     67.58% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  267960      0.98%     68.55% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  427466      1.56%     70.11% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 5038940     18.40%     88.52% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  758703      2.77%     91.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  165190      0.60%     91.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  190909      0.70%     92.59% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  425900      1.56%     94.14% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 1603514      5.86%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                18541980     67.57%     67.57% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  269924      0.98%     68.55% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  430608      1.57%     70.12% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 5041958     18.37%     88.49% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  762355      2.78%     91.27% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  165901      0.60%     91.88% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  191104      0.70%     92.57% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  428586      1.56%     94.14% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 1609409      5.86%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            27382085                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.292786                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.184671                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 8439244                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles              9737555                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  8269995                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               308345                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                381075                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              165536                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                12831                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              36664015                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                39751                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                381075                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 8796739                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                2804819                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       5741072                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  8142606                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              1269911                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              35531036                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                 2469                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                231647                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents               446543                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands           23808302                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             44475961                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        44419812                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            52401                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             22020270                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 1788032                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            498319                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         58753                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3705896                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3335757                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2091143                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           366529                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          285241                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  33051386                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             616780                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 32598005                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            35098                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        2143170                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1082478                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        435207                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     27382085                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.190487                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.575531                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            27441825                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.292897                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.185802                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 8480872                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles              9736053                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  8290323                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               308881                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                379812                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              165178                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                12521                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              36770346                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                39237                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                379812                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 8839767                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                2783657                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       5759458                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  8162466                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              1270789                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              35635356                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 2433                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                230404                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents               445807                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands           23881418                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             44614948                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        44558512                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            52675                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             22098169                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 1783249                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            500707                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         58904                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3714662                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3352351                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2102718                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           368829                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          261079                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  33144056                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             620028                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 32694445                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            35243                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        2135274                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1079120                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        437376                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     27441825                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.191409                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.576872                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           15085778     55.09%     55.09% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            3054879     11.16%     66.25% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1548873      5.66%     71.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            5868849     21.43%     93.34% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4             901287      3.29%     96.63% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             476925      1.74%     98.37% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             288026      1.05%     99.42% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             138840      0.51%     99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              18628      0.07%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           15111094     55.07%     55.07% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            3067205     11.18%     66.24% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1556680      5.67%     71.92% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            5872597     21.40%     93.32% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4             904620      3.30%     96.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             481374      1.75%     98.37% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             286422      1.04%     99.41% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             142457      0.52%     99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              19376      0.07%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       27382085                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       27441825                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  33655     13.83%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     13.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                111431     45.78%     59.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                98340     40.40%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  33866     13.68%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     13.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                112679     45.53%     59.21% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               100956     40.79%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass             2440      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             26953534     82.68%     82.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               19910      0.06%     82.75% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     82.75% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd               8410      0.03%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3301438     10.13%     92.91% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2024047      6.21%     99.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            287006      0.88%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             27019317     82.64%     82.65% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               20282      0.06%     82.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     82.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd               8426      0.03%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     82.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3318398     10.15%     92.89% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2035966      6.23%     99.12% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            288396      0.88%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              32598005                       # Type of FU issued
-system.cpu2.iq.rate                          1.042168                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     243426                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.007468                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          92623863                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         35700994                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     32205742                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             232756                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            114085                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       110215                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              32717888                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 121103                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          185687                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              32694445                       # Type of FU issued
+system.cpu2.iq.rate                          1.043361                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     247501                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.007570                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          92879210                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         35788610                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     32300559                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             234249                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            114557                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       110717                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              32817438                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 122068                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          187489                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       410803                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1083                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         3827                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       157383                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       409544                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses          984                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         3929                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       155635                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         4176                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        27619                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         4136                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        26287                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                381075                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                2023183                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               204607                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           34934170                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts           220301                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3335757                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2091143                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            547666                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                141469                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents                 2123                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          3827                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         63090                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.iewSquashCycles                379812                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                2011431                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               204809                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           35034427                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts           220433                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3352351                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2102718                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            550753                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                142349                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                 2108                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          3929                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         63003                       # Number of branches that were predicted taken incorrectly
 system.cpu2.iew.predictedNotTakenIncorrect       127121                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              190211                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             32442083                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3195032                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           155922                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.branchMispredicts              190124                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             32537756                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3211080                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           156689                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1266004                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     5203645                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 7597485                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2008613                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.037183                       # Inst execution rate
-system.cpu2.iew.wb_sent                      32348485                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     32315957                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 18839799                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 22025525                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                      1270343                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5232018                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 7610407                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2020938                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.038361                       # Inst execution rate
+system.cpu2.iew.wb_sent                      32444193                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     32411276                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 18891849                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 22089477                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.033151                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.855362                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.034325                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.855242                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        2315429                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         181573                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           175784                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     27001010                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.206363                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.845727                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        2305077                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         182652                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           175963                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     27062013                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.207707                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.849174                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     16087817     59.58%     59.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2320535      8.59%     68.18% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1221811      4.53%     72.70% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      5612171     20.79%     93.49% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       500601      1.85%     95.34% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       184383      0.68%     96.02% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       174610      0.65%     96.67% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       192284      0.71%     97.38% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       706798      2.62%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     16121128     59.57%     59.57% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2330838      8.61%     68.18% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1224813      4.53%     72.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      5615394     20.75%     93.46% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       503174      1.86%     95.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       185895      0.69%     96.01% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       176248      0.65%     96.66% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       179513      0.66%     97.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       725010      2.68%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     27001010                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            32573021                       # Number of instructions committed
-system.cpu2.commit.committedOps              32573021                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     27062013                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            32682976                       # Number of instructions committed
+system.cpu2.commit.committedOps              32682976                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       4858714                       # Number of memory references committed
-system.cpu2.commit.loads                      2924954                       # Number of loads committed
-system.cpu2.commit.membars                      63567                       # Number of memory barriers committed
-system.cpu2.commit.branches                   7451291                       # Number of branches committed
-system.cpu2.commit.fp_insts                    109021                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 31134232                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              227850                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events               706798                       # number cycles where commit BW limit reached
+system.cpu2.commit.refs                       4889890                       # Number of memory references committed
+system.cpu2.commit.loads                      2942807                       # Number of loads committed
+system.cpu2.commit.membars                      63964                       # Number of memory barriers committed
+system.cpu2.commit.branches                   7465437                       # Number of branches committed
+system.cpu2.commit.fp_insts                    109562                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 31237309                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              229028                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass      1167807      3.57%      3.57% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        26241804     80.29%     83.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          19886      0.06%     83.93% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     83.93% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd          8426      0.03%     83.95% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     83.95% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     83.95% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     83.95% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv          1220      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     83.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        3006771      9.20%     93.16% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       1948666      5.96%     99.12% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess       288396      0.88%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::total         32682976                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events               725010                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                    61108801                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   70157468                       # The number of ROB writes
-system.cpu2.timesIdled                         244589                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        3896937                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1746488839                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   31413101                       # Number of Instructions Simulated
-system.cpu2.committedOps                     31413101                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total             31413101                       # Number of Instructions Simulated
-system.cpu2.cpi                              0.995732                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.995732                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.004287                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.004287                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                42678646                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               22701958                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    67399                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   67744                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                5400058                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                256035                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                    61251181                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   70355425                       # The number of ROB writes
+system.cpu2.timesIdled                         245354                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        3893863                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1748379581                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   31517609                       # Number of Instructions Simulated
+system.cpu2.committedOps                     31517609                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total             31517609                       # Number of Instructions Simulated
+system.cpu2.cpi                              0.994228                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.994228                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.005806                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.005806                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                42812311                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               22772429                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    67678                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   67966                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                5406368                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                257490                       # number of misc regfile writes
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 5f9799ffe..2c9e78fdf 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,137 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.526170                       # Number of seconds simulated
-sim_ticks                                2526169857500                       # Number of ticks simulated
-final_tick                               2526169857500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.526192                       # Number of seconds simulated
+sim_ticks                                2526192217500                       # Number of ticks simulated
+final_tick                               2526192217500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46796                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60213                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1960134913                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 468616                       # Number of bytes of host memory used
-host_seconds                                  1288.77                       # Real time elapsed on the host
-sim_insts                                    60309637                       # Number of instructions simulated
-sim_ops                                      77601213                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  45758                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58877                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1916680323                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 469072                       # Number of bytes of host memory used
+host_seconds                                  1318.00                       # Real time elapsed on the host
+sim_insts                                    60309034                       # Number of instructions simulated
+sim_ops                                      77600502                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         2880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            797632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9095320                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129433624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       797632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          797632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3785024                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            796992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9095192                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129433368                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       796992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          796992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3784320                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6801096                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6800392                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           45                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           53                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12463                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142150                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15096868                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59141                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12453                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142148                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15096864                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59130                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813159                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47319725                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1140                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               813148                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47319307                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1343                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               315748                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3600439                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51237103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          315748                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315748                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1498325                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1193931                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2692256                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1498325                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47319725                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1140                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               315491                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3600356                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51236548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          315491                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315491                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1498033                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1193920                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2691954                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1498033                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47319307                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1343                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              315748                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4794370                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53929359                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15096868                       # Number of read requests accepted
-system.physmem.writeReqs                       813159                       # Number of write requests accepted
-system.physmem.readBursts                    15096868                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813159                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                960809152                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   5390400                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6824768                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 129433624                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6801096                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    84225                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706499                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4674                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              943297                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              937033                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              936962                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              936535                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              942693                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              936569                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              936319                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              936043                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              943596                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              936992                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             936414                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             935912                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             943556                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             937007                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             937039                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             936676                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6606                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6375                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6521                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6552                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6461                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6711                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6720                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6668                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7045                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6826                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6497                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6136                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7072                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6672                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6956                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6819                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              315491                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4794277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53928501                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15096864                       # Number of read requests accepted
+system.physmem.writeReqs                       813148                       # Number of write requests accepted
+system.physmem.readBursts                    15096864                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     813148                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                961540928                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   4658368                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6820736                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 129433368                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6800392                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    72787                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706544                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4695                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              943480                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              937980                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              937559                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              937528                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              943087                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              937982                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              937070                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              936990                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              943982                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              938303                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             937119                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             936407                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             943924                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             938214                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             937241                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             937211                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6601                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6388                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6528                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6554                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6464                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6726                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6713                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6652                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7031                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6803                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6461                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6104                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7064                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6684                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6965                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6836                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2526168741500                       # Total gap between requests
+system.physmem.totGap                    2526191083500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
 system.physmem.readPktSize::3                14942208                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154622                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154618                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59141                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1044851                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    985737                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    938636                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    947948                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    933228                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    933834                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2717841                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2709185                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3589675                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     37568                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    33871                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    34960                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    32201                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    30053                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    21726                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    21191                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  59130                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1056388                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    996212                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    954030                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1063517                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    957350                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1019929                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2630220                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2535649                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3302007                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    132277                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   114408                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   104766                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                   100921                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19448                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18562                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18244                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      130                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -159,47 +159,47 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1817                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5776                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6376                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6039                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6697                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      587                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      595                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      576                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      540                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      538                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2638                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6394                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6781                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6438                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6465                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
@@ -208,67 +208,50 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       949853                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     1012.832967                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     998.129194                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev      95.600820                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           4614      0.49%      0.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         3555      0.37%      0.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1868      0.20%      1.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1270      0.13%      1.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          998      0.11%      1.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          697      0.07%      1.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          628      0.07%      1.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          802      0.08%      1.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       935421     98.48%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         949853                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5541                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2709.372676                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    121858.968991                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         5537     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.04%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       995555                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      972.685250                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     907.127186                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     202.423056                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22972      2.31%      2.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        19885      2.00%      4.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8241      0.83%      5.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2302      0.23%      5.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2369      0.24%      5.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1811      0.18%      5.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8514      0.86%      6.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          964      0.10%      6.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       928497     93.26%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         995555                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6226                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2413.115644                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    115125.420570                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         6222     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5541                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5541                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.245082                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.302826                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.619957                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3691     66.61%     66.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 16      0.29%     66.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                178      3.21%     70.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1008     18.19%     88.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 44      0.79%     89.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 25      0.45%     89.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 20      0.36%     89.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 16      0.29%     90.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  5      0.09%     90.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  2      0.04%     90.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.02%     90.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  1      0.02%     90.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.02%     90.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  2      0.04%     90.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  1      0.02%     90.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                143      2.58%     93.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                305      5.50%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                 21      0.38%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                 14      0.25%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                 20      0.36%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                 15      0.27%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  5      0.09%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  3      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  3      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5541                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   571195583500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              674382869750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  75063215000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 28124071250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       38047.64                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1873.36                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            6226                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6226                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.117571                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.060113                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.446555                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3515     56.46%     56.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 41      0.66%     57.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1615     25.94%     83.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                842     13.52%     96.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 76      1.22%     97.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 41      0.66%     98.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 38      0.61%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 41      0.66%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 16      0.26%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6226                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   389908010000                       # Total ticks spent queuing
+system.physmem.totMemAccLat              671609453750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  75120385000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25952.21                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44921.00                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         380.34                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44702.21                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         380.63                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.70                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       51.24                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.69                       # Average system write bandwidth in MiByte/s
@@ -276,15 +259,19 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           2.99                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         7.11                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.53                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14041195                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     91389                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.68                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158778.41                       # Average gap between requests
-system.physmem.pageHitRate                      93.47                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.34                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         6.80                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        27.01                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14044000                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     91096                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.45                       # Row buffer hit rate for writes
+system.physmem.avgGap                       158779.96                       # Average gap between requests
+system.physmem.pageHitRate                      93.42                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2186359463750                       # Time in different power states
+system.physmem.memoryStateTime::REF       84354920000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      255472398750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
@@ -297,50 +284,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst           25
 system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54878638                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16149508                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16149508                       # Transaction distribution
+system.membus.throughput                     54877773                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16149486                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16149486                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763349                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763349                       # Transaction distribution
-system.membus.trans_dist::Writeback             59141                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4671                       # Transaction distribution
+system.membus.trans_dist::Writeback             59130                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4692                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4674                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131433                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131433                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4695                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131451                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131451                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383044                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3760                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885845                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272653                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885868                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272676                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29884416                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     29884416                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34157069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34157092                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390454                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16697056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19095098                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16696096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19094138                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119537664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           138632762                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              138632762                       # Total data (bytes)
+system.membus.tot_pkt_size::total           138631802                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              138631802                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1487078000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1486816000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3653000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3620500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17362845500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17362899000                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4737809043                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4734189076                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37210156152                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        36898450149                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -348,7 +335,7 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48266001                       # Throughput (bytes/s)
+system.iobus.throughput                      48265574                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq             16125556                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            16125556                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8174                       # Transaction distribution
@@ -458,18 +445,18 @@ system.iobus.reqLayer25.occupancy         14942208000                       # La
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374870000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         37245686848                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         37675624851                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14755327                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11837490                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            706705                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9530563                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7665782                       # Number of BTB hits
+system.cpu.branchPred.lookups                14753661                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11836576                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            705670                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9513727                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7668660                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.433674                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1400618                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              72971                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.606265                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1399145                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              72578                       # Number of incorrect RAS predictions.
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -493,9 +480,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             14987589                       # DTB read hits
-system.cpu.checker.dtb.read_misses               7306                       # DTB read misses
-system.cpu.checker.dtb.write_hits            11227681                       # DTB write hits
+system.cpu.checker.dtb.read_hits             14987453                       # DTB read hits
+system.cpu.checker.dtb.read_misses               7308                       # DTB read misses
+system.cpu.checker.dtb.write_hits            11227597                       # DTB write hits
 system.cpu.checker.dtb.write_misses              2191                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
@@ -506,12 +493,12 @@ system.cpu.checker.dtb.align_faults                 0                       # Nu
 system.cpu.checker.dtb.prefetch_faults            180                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         14994895                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        11229872                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         14994761                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        11229788                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  26215270                       # DTB hits
-system.cpu.checker.dtb.misses                    9497                       # DTB misses
-system.cpu.checker.dtb.accesses              26224767                       # DTB accesses
+system.cpu.checker.dtb.hits                  26215050                       # DTB hits
+system.cpu.checker.dtb.misses                    9499                       # DTB misses
+system.cpu.checker.dtb.accesses              26224549                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -533,7 +520,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.inst_hits             61483612                       # ITB inst hits
+system.cpu.checker.itb.inst_hits             61483008                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4473                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -550,11 +537,11 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses         61488085                       # ITB inst accesses
-system.cpu.checker.itb.hits                  61483612                       # DTB hits
+system.cpu.checker.itb.inst_accesses         61487481                       # ITB inst accesses
+system.cpu.checker.itb.hits                  61483008                       # DTB hits
 system.cpu.checker.itb.misses                    4473                       # DTB misses
-system.cpu.checker.itb.accesses              61488085                       # DTB accesses
-system.cpu.checker.numCycles                 77887007                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses              61487481                       # DTB accesses
+system.cpu.checker.numCycles                 77886295                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -580,25 +567,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51187284                       # DTB read hits
-system.cpu.dtb.read_misses                      65383                       # DTB read misses
-system.cpu.dtb.write_hits                    11703682                       # DTB write hits
-system.cpu.dtb.write_misses                     15916                       # DTB write misses
+system.cpu.dtb.read_hits                     51183231                       # DTB read hits
+system.cpu.dtb.read_misses                      65223                       # DTB read misses
+system.cpu.dtb.write_hits                    11700953                       # DTB write hits
+system.cpu.dtb.write_misses                     15725                       # DTB write misses
 system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3484                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2464                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.flush_entries                     3479                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      2504                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                    408                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1363                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51252667                       # DTB read accesses
-system.cpu.dtb.write_accesses                11719598                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1339                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51248454                       # DTB read accesses
+system.cpu.dtb.write_accesses                11716678                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          62890966                       # DTB hits
-system.cpu.dtb.misses                           81299                       # DTB misses
-system.cpu.dtb.accesses                      62972265                       # DTB accesses
+system.cpu.dtb.hits                          62884184                       # DTB hits
+system.cpu.dtb.misses                           80948                       # DTB misses
+system.cpu.dtb.accesses                      62965132                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -620,8 +607,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     11527099                       # ITB inst hits
-system.cpu.itb.inst_misses                      11249                       # ITB inst misses
+system.cpu.itb.inst_hits                     11525561                       # ITB inst hits
+system.cpu.itb.inst_misses                      11159                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -630,113 +617,113 @@ system.cpu.itb.flush_tlb                            4                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2504                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2509                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                      2978                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 11538348                       # ITB inst accesses
-system.cpu.itb.hits                          11527099                       # DTB hits
-system.cpu.itb.misses                           11249                       # DTB misses
-system.cpu.itb.accesses                      11538348                       # DTB accesses
-system.cpu.numCycles                        477119451                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 11536720                       # ITB inst accesses
+system.cpu.itb.hits                          11525561                       # DTB hits
+system.cpu.itb.misses                           11159                       # DTB misses
+system.cpu.itb.accesses                      11536720                       # DTB accesses
+system.cpu.numCycles                        477128882                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29745347                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       90343663                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14755327                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9066400                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      20160515                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4659374                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     121718                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               98274067                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2638                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         88444                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      2690508                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          430                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11523637                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                709778                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5230                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          154294046                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.730147                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.081756                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29759197                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       90327124                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14753661                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9067805                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      20158177                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4657193                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     122600                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               98301886                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2694                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         86268                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      2686675                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          550                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  11522069                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                710692                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5197                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          154327188                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.729776                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.081128                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                134149007     86.94%     86.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1305162      0.85%     87.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1712027      1.11%     88.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2298089      1.49%     90.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2109453      1.37%     91.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1103374      0.72%     92.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2555030      1.66%     94.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   746204      0.48%     94.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  8315700      5.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                134184573     86.95%     86.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1304702      0.85%     87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1713961      1.11%     88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2295969      1.49%     90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2111581      1.37%     91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1105061      0.72%     92.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2556088      1.66%     94.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   746376      0.48%     94.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  8308877      5.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            154294046                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.030926                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.189352                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 31777956                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             100129696                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18080387                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1265250                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3040757                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              1958128                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                172070                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              107328179                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                570705                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3040757                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 33516419                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                38693091                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       55142047                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  17591419                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6310313                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102323009                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   472                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1000039                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4066050                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              733                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           106393961                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             474042454                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        432890289                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10421                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              78727775                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27666185                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1171025                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1077190                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12642564                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19725934                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13308899                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1965192                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2472766                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   95138203                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1987496                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 122932074                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            165549                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18954995                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     47273204                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         505173                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     154294046                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.796739                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.515436                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            154327188                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.030922                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.189314                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 31784305                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             100158613                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18079626                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1265080                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3039564                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              1958546                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                172069                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              107310478                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                569843                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3039564                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 33522780                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                38730372                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       55131073                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  17590016                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6313383                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102310347                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   498                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 999968                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4068660                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              821                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           106387059                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             473967662                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        432826370                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10390                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              78726997                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 27660061                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1170574                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1076856                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12635163                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             19719056                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13304976                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1944651                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2472247                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   95130107                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1987847                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 122918672                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            165693                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18947879                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     47268855                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         505540                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     154327188                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.796481                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.515149                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           109928517     71.25%     71.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14405522      9.34%     80.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6874407      4.46%     85.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5677816      3.68%     88.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12311103      7.98%     96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2805861      1.82%     98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1693952      1.10%     99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              468083      0.30%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              128785      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           109964387     71.25%     71.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14401004      9.33%     80.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             6880878      4.46%     85.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5675452      3.68%     88.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12310168      7.98%     96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2806019      1.82%     98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1694480      1.10%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              466491      0.30%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              128309      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       154294046                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       154327188                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   61713      0.70%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   61903      0.70%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      4      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.70% # attempts to use FU when none available
@@ -765,13 +752,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.70% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8365366     94.65%     95.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                411034      4.65%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8364845     94.62%     95.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                413343      4.68%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             28518      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              57971139     47.16%     47.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                93360      0.08%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              57967032     47.16%     47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                93290      0.08%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.26% # Type of FU issued
@@ -784,11 +771,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.26% # Ty
 system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  25      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  21      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc              18      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc              13      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.26% # Type of FU issued
@@ -797,404 +784,440 @@ system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.26% # Ty
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc           19      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc           14      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             52513425     42.72%     89.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12323457     10.02%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             52507324     42.72%     89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12320347     10.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              122932074                       # Type of FU issued
-system.cpu.iq.rate                           0.257655                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8838117                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.071894                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          409219406                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         116097301                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85490758                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               23382                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12446                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10288                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              131729199                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12474                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           624027                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              122918672                       # Type of FU issued
+system.cpu.iq.rate                           0.257622                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8840095                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.071918                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          409227562                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         116082546                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     85482417                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               23345                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12482                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10295                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              131717793                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12456                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           625155                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4071144                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6793                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        30196                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1576838                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4064409                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6818                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        30381                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1573005                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34107946                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        680806                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107982                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        680619                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3040757                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                30225758                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                434257                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            97346977                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            205962                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19725934                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13308899                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1415361                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 113324                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  3429                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          30196                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         351437                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       270055                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               621492                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             120854906                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              51874598                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2077168                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3039564                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                30259815                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                434333                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            97340803                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            205354                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              19719056                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13304976                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1415400                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 113322                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3328                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          30381                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         350453                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       269952                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               620405                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             120843569                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              51870507                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2075103                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        221278                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64090111                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11821235                       # Number of branches executed
-system.cpu.iew.exec_stores                   12215513                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.253301                       # Inst execution rate
-system.cpu.iew.wb_sent                      119911072                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85501046                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  47029089                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  87607932                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        222849                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64083354                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11822089                       # Number of branches executed
+system.cpu.iew.exec_stores                   12212847                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.253272                       # Inst execution rate
+system.cpu.iew.wb_sent                      119902421                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      85492712                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47017508                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  87566112                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.179203                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.536813                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.179182                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.536937                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        18687715                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1482323                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            537083                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    151253289                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.514049                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.489960                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        18682974                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1482307                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            536093                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    151287624                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.513928                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.489816                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    122784132     81.18%     81.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14644365      9.68%     90.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3917692      2.59%     93.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2132798      1.41%     94.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1620432      1.07%     95.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       975760      0.65%     96.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1598249      1.06%     97.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       715459      0.47%     98.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2864402      1.89%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    122817908     81.18%     81.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14643914      9.68%     90.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3918754      2.59%     93.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2134639      1.41%     94.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1621396      1.07%     95.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       973729      0.64%     96.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1595383      1.05%     97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       716191      0.47%     98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2865710      1.89%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    151253289                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             60460018                       # Number of instructions committed
-system.cpu.commit.committedOps               77751594                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    151287624                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60459415                       # Number of instructions committed
+system.cpu.commit.committedOps               77750883                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27386851                       # Number of memory references committed
-system.cpu.commit.loads                      15654790                       # Number of loads committed
-system.cpu.commit.membars                      403577                       # Number of memory barriers committed
-system.cpu.commit.branches                   10306380                       # Number of branches committed
+system.cpu.commit.refs                       27386618                       # Number of memory references committed
+system.cpu.commit.loads                      15654647                       # Number of loads committed
+system.cpu.commit.membars                      403571                       # Number of memory barriers committed
+system.cpu.commit.branches                   10306311                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  69191623                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               991253                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2864402                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  69190973                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               991245                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         50274217     64.66%     64.66% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           87935      0.11%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         2113      0.00%     64.78% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     64.78% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.78% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.78% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        15654647     20.13%     84.91% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       11731971     15.09%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total          77750883                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2865710                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    242979782                       # The number of ROB reads
-system.cpu.rob.rob_writes                   196005989                       # The number of ROB writes
-system.cpu.timesIdled                         1777234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       322825405                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4575137230                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    60309637                       # Number of Instructions Simulated
-system.cpu.committedOps                      77601213                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              60309637                       # Number of Instructions Simulated
-system.cpu.cpi                               7.911164                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.911164                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.126404                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.126404                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                548698002                       # number of integer regfile reads
-system.cpu.int_regfile_writes                87552826                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8408                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2932                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               268236665                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1173235                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                58867266                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2659080                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2659079                       # Transaction distribution
+system.cpu.rob.rob_reads                    243007370                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195993770                       # The number of ROB writes
+system.cpu.timesIdled                         1776375                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       322801694                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4575172520                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60309034                       # Number of Instructions Simulated
+system.cpu.committedOps                      77600502                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              60309034                       # Number of Instructions Simulated
+system.cpu.cpi                               7.911400                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.911400                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.126400                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.126400                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                548643018                       # number of integer regfile reads
+system.cpu.int_regfile_writes                87545925                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8332                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2902                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               268108891                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1173224                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                58876928                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2658786                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2658785                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq        763349                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp       763349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       607635                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2959                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2975                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       246069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       246069                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1961962                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5796085                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30498                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       129069                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7917614                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62744960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85505466                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214572                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148505990                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148505990                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       202724                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3129185667                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback       607456                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2966                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           12                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2978                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       246178                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       246178                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1963155                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5795994                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30467                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128822                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7918438                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62783488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85496634                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        41888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       215832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      148537842                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         148537842                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       196596                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3128822166                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1474638965                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1475557763                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2549207556                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2549946762                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      20255489                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19999491                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      75530794                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74967796                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            980897                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.570903                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            10462766                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            981409                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             10.660964                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        6958078250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.570903                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999162                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            981488                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.574363                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            10460581                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            982000                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             10.652323                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        6957426250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.574363                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999169                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999169                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          222                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          155                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          12504958                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         12504958                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     10462766                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        10462766                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      10462766                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         10462766                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     10462766                       # number of overall hits
-system.cpu.icache.overall_hits::total        10462766                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1060743                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1060743                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1060743                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1060743                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1060743                       # number of overall misses
-system.cpu.icache.overall_misses::total       1060743                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14268635888                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14268635888                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14268635888                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14268635888                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14268635888                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14268635888                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11523509                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11523509                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11523509                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11523509                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11523509                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11523509                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092050                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.092050                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.092050                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.092050                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.092050                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.092050                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13451.548479                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13451.548479                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         7798                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          12503981                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         12503981                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     10460581                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        10460581                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      10460581                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         10460581                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     10460581                       # number of overall hits
+system.cpu.icache.overall_hits::total        10460581                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1061360                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1061360                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1061360                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1061360                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1061360                       # number of overall misses
+system.cpu.icache.overall_misses::total       1061360                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14265779687                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14265779687                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14265779687                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14265779687                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14265779687                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14265779687                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     11521941                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     11521941                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     11521941                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     11521941                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     11521941                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     11521941                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092116                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.092116                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.092116                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.092116                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.092116                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.092116                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13441.037619                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13441.037619                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         7028                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               344                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               352                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    22.668605                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    19.965909                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79293                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        79293                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        79293                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        79293                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        79293                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        79293                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981450                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       981450                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       981450                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       981450                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       981450                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       981450                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11587546773                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11587546773                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11587546773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11587546773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11587546773                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11587546773                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      9345000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      9345000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      9345000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      9345000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085169                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.085169                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.085169                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79319                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        79319                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        79319                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        79319                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        79319                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        79319                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       982041                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       982041                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       982041                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       982041                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       982041                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       982041                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11583712225                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11583712225                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11583712225                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11583712225                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11583712225                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11583712225                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      8965500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      8965500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      8965500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      8965500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085232                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085232                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085232                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.085232                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085232                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.085232                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            64391                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        51374.630920                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1887139                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           129786                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            14.540390                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2490832751500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    31.305745                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000374                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8179.061871                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6245.594773                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563334                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000478                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            64387                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        51384.068329                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1888247                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           129781                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            14.549487                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2490875317000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    37.347999                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000373                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8175.789418                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6233.237161                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.563624                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000570                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124803                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.095300                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.783915                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65372                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3052                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6933                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54996                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000351                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997498                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18788998                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18788998                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53598                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10246                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       967912                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       386978                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1418734                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       607635                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       607635                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           46                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           46                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           13                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total           13                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       112878                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       112878                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        53598                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        10246                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       967912                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       499856                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1531612                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        53598                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        10246                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       967912                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       499856                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1531612                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           45                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124753                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.095112                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.784059                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           27                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65367                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           26                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          353                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3046                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6928                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54999                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000412                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997421                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18797143                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18797143                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53905                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10470                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       968525                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       386928                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1419828                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       607456                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       607456                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           45                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           45                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            9                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total            9                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       112956                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       112956                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        53905                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        10470                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       968525                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       499884                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1532784                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        53905                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        10470                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       968525                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       499884                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1532784                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           53                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12357                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        10744                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        23148                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2913                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2913                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        12346                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        10726                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        23127                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2921                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2921                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133191                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133191                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           45                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133222                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133222                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           53                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12357                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143935                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        156339                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           45                       # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst        12346                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       143948                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        156349                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           53                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12357                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143935                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       156339                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3974500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       412000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    905251250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    810262998                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1719900748                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       510978                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       510978                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9827066492                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9827066492                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3974500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       412000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    905251250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10637329490                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11546967240                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3974500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       412000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    905251250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10637329490                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11546967240                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53643                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10248                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       980269                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       397722                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1441882                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       607635                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       607635                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2959                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2959                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           16                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total           16                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       246069                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       246069                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        53643                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        10248                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       980269                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       643791                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1687951                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        53643                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        10248                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       980269                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       643791                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1687951                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000195                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012606                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.027014                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016054                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.984454                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.984454                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.187500                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.187500                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541275                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.541275                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000195                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012606                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.223574                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.092621                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000195                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012606                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.223574                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.092621                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       206000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73258.173505                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75415.394453                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74300.187835                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   175.412976                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   175.412976                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73781.760720                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73781.760720                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       206000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73258.173505                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73903.702991                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73858.520523                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       206000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73258.173505                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73903.702991                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73858.520523                       # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.inst        12346                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       143948                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       156349                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4489500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       430000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    894766750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    805694000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1705380250                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       465480                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       465480                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9848665479                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9848665479                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4489500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       430000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    894766750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10654359479                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11554045729                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4489500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       430000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    894766750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10654359479                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11554045729                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53958                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10472                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       980871                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       397654                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1442955                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       607456                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       607456                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2966                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2966                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           12                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total           12                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       246178                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       246178                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        53958                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        10472                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       980871                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       643832                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1689133                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        53958                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        10472                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       980871                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       643832                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1689133                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000982                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000191                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012587                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026973                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.016028                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.984828                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.984828                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541161                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.541161                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000982                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000191                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012587                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.223580                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.092562                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000982                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000191                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012587                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.223580                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.092562                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84707.547170                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       215000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72474.222420                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.979862                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73739.795477                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   159.356385                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   159.356385                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73926.719904                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73926.719904                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84707.547170                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       215000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72474.222420                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74015.335253                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73899.070215                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84707.547170                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       215000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72474.222420                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74015.335253                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73899.070215                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1203,109 +1226,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        59141                       # number of writebacks
-system.cpu.l2cache.writebacks::total            59141                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           65                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           65                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           65                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           80                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           45                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        59130                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59130                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           67                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           81                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           67                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           81                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           14                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           67                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           81                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           53                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12342                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10679                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        23068                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2913                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2913                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12332                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10659                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        23046                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2921                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2921                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133191                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133191                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           45                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133222                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133222                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           53                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12342                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143870                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       156259                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           45                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        12332                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143881                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       156268                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           53                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12342                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143870                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       156259                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       387500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    749197750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    673040498                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1426043248                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29132913                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29132913                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12332                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143881                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       156268                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3834000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       405500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    738779500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    668273250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1411292250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29213921                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29213921                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8170239508                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8170239508                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       387500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    749197750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8843280006                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9596282756                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       387500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    749197750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8843280006                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9596282756                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6814499                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942562250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166949376749                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17458567530                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17458567530                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6814499                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184401129780                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184407944279                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026850                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015999                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.984454                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984454                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.187500                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.187500                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541275                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541275                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223473                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.092573                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223473                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.092573                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63024.674408                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61819.110803                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8190370021                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8190370021                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3834000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       405500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    738779500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8858643271                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9601662271                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3834000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       405500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    738779500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8858643271                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9601662271                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6434999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17456853479                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17456853479                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6434999                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000982                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000191                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012572                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026805                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015971                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.984828                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984828                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541161                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541161                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000982                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000191                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012572                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223476                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.092514                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000982                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000191                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012572                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223476                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.092514                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       202750                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       202750                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       202750                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1315,168 +1338,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            643279                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993228                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            21514190                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            643791                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             33.417973                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          43094250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993228                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            643320                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.993245                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21508532                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            643832                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             33.407056                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          42989250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.993245                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         101537487                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        101537487                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13760648                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13760648                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7259865                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7259865                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       242998                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       242998                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247594                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247594                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21020513                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21020513                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21020513                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21020513                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       736359                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        736359                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2962417                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2962417                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13527                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13527                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           16                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           16                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3698776                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3698776                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3698776                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3698776                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9982812336                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9982812336                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 139744433579                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    185287000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    185287000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       245503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       245503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 149727245915                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 149727245915                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 149727245915                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 149727245915                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14497007                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14497007                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222282                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222282                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256525                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       256525                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247610                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247610                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24719289                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24719289                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24719289                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24719289                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050794                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.050794                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289800                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.289800                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052732                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052732                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000065                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000065                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.149631                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.149631                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.149631                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.149631                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40480.214513                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40480.214513                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        31777                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        23524                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2637                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             274                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.050436                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    85.854015                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses         101516564                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        101516564                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13756930                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13756930                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7258142                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7258142                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       242767                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       242767                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247595                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247595                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21015072                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21015072                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21015072                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21015072                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       735153                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        735153                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2964059                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2964059                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13525                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13525                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           12                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3699212                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3699212                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3699212                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3699212                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9975087313                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9975087313                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 139822431498                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    185099999                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    185099999                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       193503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       193503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 149797518811                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 149797518811                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 149797518811                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 149797518811                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14492083                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14492083                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10222201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256292                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       256292                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247607                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247607                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24714284                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24714284                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24714284                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24714284                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050728                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.050728                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289963                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.289963                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052772                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052772                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000048                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.149679                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.149679                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.149679                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.149679                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40494.440116                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40494.440116                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32269                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        24322                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2609                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             289                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.368340                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    84.159170                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607635                       # number of writebacks
-system.cpu.dcache.writebacks::total            607635                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       350728                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       350728                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2713476                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2713476                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1349                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1349                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3064204                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3064204                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3064204                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3064204                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385631                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       385631                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248941                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       248941                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12178                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12178                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           16                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           16                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       634572                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       634572                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       634572                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       634572                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4967633608                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4967633608                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11307381788                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11307381788                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145644250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145644250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       213497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       213497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16275015396                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16275015396                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16275015396                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  16275015396                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26867769000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26867769000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026601                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026601                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047473                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047473                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000065                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025671                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025671                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       607456                       # number of writebacks
+system.cpu.dcache.writebacks::total            607456                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       349595                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       349595                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2715007                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2715007                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1337                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1337                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3064602                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3064602                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3064602                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3064602                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385558                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       385558                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249052                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       249052                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12188                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12188                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           12                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       634610                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       634610                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       634610                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       634610                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4962813125                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4962813125                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11330760273                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11330760273                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145614251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145614251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       169497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       169497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16293573398                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  16293573398                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16293573398                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  16293573398                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26860394736                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26860394736                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026605                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026605                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024364                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024364                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047555                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047555                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000048                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025678                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025678                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025678                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025678                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1500,16 +1523,16 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1715151162848                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1712402234851                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    83035                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    83034                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 7d13ac1ec..97a804211 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,156 +1,156 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.605649                       # Number of seconds simulated
-sim_ticks                                2605649343000                       # Number of ticks simulated
-final_tick                               2605649343000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.605644                       # Number of seconds simulated
+sim_ticks                                2605643988500                       # Number of ticks simulated
+final_tick                               2605643988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  57764                       # Simulator instruction rate (inst/s)
-host_op_rate                                    74374                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2397402056                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 474764                       # Number of bytes of host memory used
-host_seconds                                  1086.86                       # Real time elapsed on the host
-sim_insts                                    62781325                       # Number of instructions simulated
-sim_ops                                      80834116                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  56388                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72604                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2339801960                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 475216                       # Number of bytes of host memory used
+host_seconds                                  1113.62                       # Real time elapsed on the host
+sim_insts                                    62794806                       # Number of instructions simulated
+sim_ops                                      80853196                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker         1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          768                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           383680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5448188                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           438080                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4125688                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131508276                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       383680                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       438080                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          821760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4229952                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst           394240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4377212                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           429184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5246712                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131559796                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       394240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       429184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          823424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4275584                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7259088                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7304720                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker           16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           12                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              5995                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             85202                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6845                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             64492                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15301383                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66093                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              6160                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             68468                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              6706                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             82008                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15302188                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66806                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               823377                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46479979                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           393                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               824090                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        46480075                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           295                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              147249                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             2090914                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           368                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              168127                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1583363                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50470443                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         147249                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         168127                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315376                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1623377                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              151302                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1679896                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           393                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              164713                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             2013595                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50490319                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         151302                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         164713                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             316016                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1640893                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6524                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            1156002                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2785904                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1623377                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46479979                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          393                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            1156004                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2803422                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1640893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       46480075                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          295                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             147249                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            2097438                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          368                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             168127                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2739365                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53256346                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15301383                       # Number of read requests accepted
-system.physmem.writeReqs                       823377                       # Number of write requests accepted
-system.physmem.readBursts                    15301383                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     823377                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                973889408                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   5399104                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7284800                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131508276                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7259088                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    84361                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  709522                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          14082                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              956098                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              950020                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              950090                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              949980                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              956223                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              949119                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              948884                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              948711                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              956337                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              950158                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             948908                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             948900                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             955944                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             949314                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             949393                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             948943                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7119                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7037                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7071                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7168                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7696                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7220                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7070                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6913                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7415                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7415                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6887                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6788                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7071                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6872                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7197                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6886                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst             151302                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1686421                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          393                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             164713                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            3169600                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53293741                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15302188                       # Number of read requests accepted
+system.physmem.writeReqs                       824090                       # Number of write requests accepted
+system.physmem.readBursts                    15302188                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     824090                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                974626176                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   4713856                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7328128                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131559796                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7304720                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    73654                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  709569                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          14159                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              956238                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              951013                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              950196                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              950464                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              956634                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              950822                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              949869                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              949811                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              956681                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              951277                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             949961                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             949024                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             956331                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             950586                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             950041                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             949586                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7062                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6963                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7126                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7116                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7811                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7409                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7013                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7004                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7458                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7561                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6914                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6583                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7179                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7101                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7219                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6983                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2605648115500                       # Total gap between requests
+system.physmem.totGap                    2605642823000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
 system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  162458                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  163263                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 757284                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66093                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1062706                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    998935                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    950903                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    959607                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    945820                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    946342                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2754714                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2746120                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3637640                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     38272                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    34182                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    34523                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    32360                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    30630                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    22253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    21644                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      254                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      101                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        8                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66806                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1074226                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1009957                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    967065                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1078396                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    970167                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1034458                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2664402                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2566961                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3342237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    136100                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   116220                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   107345                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                   103465                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19833                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18840                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18525                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      210                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -176,47 +176,47 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1944                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2401                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4700                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6079                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6509                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      601                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      590                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      556                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      578                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      541                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      540                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      541                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2784                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3035                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4735                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6909                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6865                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6844                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6850                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6821                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6824                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6992                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6732                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
@@ -225,85 +225,74 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       965097                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     1010.691593                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     992.992769                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     104.599429                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           5712      0.59%      0.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4413      0.46%      1.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         2116      0.22%      1.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1499      0.16%      1.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1121      0.12%      1.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          815      0.08%      1.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          661      0.07%      1.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          851      0.09%      1.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       947909     98.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         965097                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5955                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2555.332662                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    92927.024688                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-262143         5949     99.90%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::262144-524287            1      0.02%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-786431            1      0.02%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-1.04858e+06            1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06            2      0.03%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5955                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5955                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.114190                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.218740                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.431880                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3971     66.68%     66.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 19      0.32%     67.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                175      2.94%     69.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1141     19.16%     89.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 44      0.74%     89.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 19      0.32%     90.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 21      0.35%     90.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 10      0.17%     90.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  6      0.10%     90.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  3      0.05%     90.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  4      0.07%     90.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.02%     90.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  1      0.02%     90.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.02%     90.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  1      0.02%     90.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  1      0.02%     90.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                146      2.45%     93.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                311      5.22%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                 13      0.22%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                 13      0.22%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                 16      0.27%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                 22      0.37%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  9      0.15%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  4      0.07%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  3      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5955                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   579051796250                       # Total ticks spent queuing
-system.physmem.totMemAccLat              683715373750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  76085110000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 28578467500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       38052.90                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1878.06                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples      1012463                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      969.866853                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     900.909804                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     207.662919                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24967      2.47%      2.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        21104      2.08%      4.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8681      0.86%      5.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2506      0.25%      5.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2720      0.27%      5.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2029      0.20%      6.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8638      0.85%      6.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1014      0.10%      7.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       940804     92.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1012463                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6706                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2270.880853                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    84552.226363                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-262143         6700     99.91%     99.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::262144-524287            1      0.01%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-786431            1      0.01%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-1.04858e+06            1      0.01%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06            1      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.88358e+06-3.14573e+06            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5.24288e+06-5.50502e+06            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6706                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6706                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.074560                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.020748                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.396636                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3829     57.10%     57.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 48      0.72%     57.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1779     26.53%     84.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                878     13.09%     97.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 53      0.79%     98.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 31      0.46%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 34      0.51%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 40      0.60%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 12      0.18%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6706                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   395588666000                       # Total ticks spent queuing
+system.physmem.totMemAccLat              681123678500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76142670000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25976.81                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44930.96                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         373.76                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.80                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       50.47                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44726.81                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         374.04                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       50.49                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.80                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.94                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.92                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.53                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.75                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14231578                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96073                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.52                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  84.38                       # Row buffer hit rate for writes
-system.physmem.avgGap                       161592.99                       # Average gap between requests
-system.physmem.pageHitRate                      93.46                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.22                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         6.23                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.05                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14234195                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     96378                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.47                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  84.16                       # Row buffer hit rate for writes
+system.physmem.avgGap                       161577.45                       # Average gap between requests
+system.physmem.pageHitRate                      93.40                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2260536385250                       # Time in different power states
+system.physmem.memoryStateTime::REF       87007960000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      258093332250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
@@ -322,300 +311,299 @@ system.realview.nvmem.bw_inst_read::total          172                       # I
 system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst          147                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             172                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54186995                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16352581                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16352581                       # Transaction distribution
-system.membus.trans_dist::WriteReq             769189                       # Transaction distribution
-system.membus.trans_dist::WriteResp            769189                       # Transaction distribution
-system.membus.trans_dist::Writeback             66093                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35785                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          18271                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14082                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137406                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137045                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384396                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                     54224369                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16352672                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16352672                       # Transaction distribution
+system.membus.trans_dist::WriteReq             769183                       # Transaction distribution
+system.membus.trans_dist::WriteResp            769183                       # Transaction distribution
+system.membus.trans_dist::Writeback             66806                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35949                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          18292                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           14159                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138125                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137746                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384364                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13840                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13834                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2042                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1974294                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4374590                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1976897                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4377155                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34652222                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392725                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               34654787                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392677                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        27680                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        27668                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4084                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17656836                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     20081781                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17753988                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     20178873                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           141192309                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              141192309                       # Total data (bytes)
+system.membus.tot_pkt_size::total           141289401                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              141289401                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1488242000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1487962500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                7000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11807000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11808000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy             1798000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy             1796000                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17652470999                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17659548997                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4843604815                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4847870095                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37703679634                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        37379122644                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    72164                       # number of replacements
-system.l2c.tags.tagsinuse                53016.131060                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1876966                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   137304                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.670148                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    72974                       # number of replacements
+system.l2c.tags.tagsinuse                53023.948009                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1873330                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   138152                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    13.559920                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37702.356015                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     7.377107                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000365                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4186.473555                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2957.675740                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    10.683393                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4035.806716                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     4115.758170                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.575292                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000113                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   37706.296895                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.412172                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000364                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4169.126027                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2962.597547                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.621110                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4061.748879                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     4107.145016                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.575352                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000083                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.063881                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.045131                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000163                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.061582                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.062801                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.808962                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.063616                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.045206                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000177                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.061977                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.062670                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.809081                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65136                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3097                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8263                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53454                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65174                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          289                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3154                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         9081                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52631                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.993896                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 18860644                       # Number of tag accesses
-system.l2c.tags.data_accesses                18860644                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        23595                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         5577                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             409210                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             169724                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        33221                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5824                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             593571                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             196649                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1437371                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          582434                       # number of Writeback hits
-system.l2c.Writeback_hits::total               582434                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             737                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1202                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1939                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           203                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           149                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               352                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            52746                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            54725                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               107471                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         23595                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          5577                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              409210                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              222470                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         33221                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5824                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              593571                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              251374                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1544842                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        23595                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         5577                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             409210                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             222470                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        33221                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5824                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             593571                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             251374                       # number of overall hits
-system.l2c.overall_hits::total                1544842                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker           16                       # number of ReadReq misses
+system.l2c.tags.occ_task_id_percent::1024     0.994476                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 18850449                       # Number of tag accesses
+system.l2c.tags.data_accesses                18850449                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        22712                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         4441                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             393676                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             165723                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        33196                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         5802                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             607870                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             201576                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1434996                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          583128                       # number of Writeback hits
+system.l2c.Writeback_hits::total               583128                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1123                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             727                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1850                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           207                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           158                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               365                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            47567                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            59393                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               106960                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         22712                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          4441                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              393676                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              213290                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         33196                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          5802                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              607870                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              260969                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1541956                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        22712                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         4441                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             393676                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             213290                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        33196                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         5802                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             607870                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             260969                       # number of overall hits
+system.l2c.overall_hits::total                1541956                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker           12                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             5877                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6190                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker           15                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             6810                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             6416                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                25326                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          5271                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4770                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             10041                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          769                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          576                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1345                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          80429                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          59312                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             139741                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker           16                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu0.inst             6041                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6321                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker           16                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             6670                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             6363                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                25425                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          5691                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4436                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             10127                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          767                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          589                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1356                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          63545                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          76877                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             140422                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker           12                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              5877                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             86619                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           15                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              6810                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             65728                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                165067                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker           16                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst              6041                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             69866                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           16                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              6670                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             83240                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                165847                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker           12                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             5877                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            86619                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           15                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             6810                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            65728                       # number of overall misses
-system.l2c.overall_misses::total               165067                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1263000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker       158000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    424519750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    461015999                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1424250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    503203750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    495567749                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1887152498                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      8440130                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     13402927                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     21843057                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       510978                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2957372                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      3468350                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   5751042289                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4687313508                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  10438355797                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker      1263000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       158000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    424519750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   6212058288                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker      1424250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    503203750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   5182881257                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     12325508295                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker      1263000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       158000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    424519750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   6212058288                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker      1424250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    503203750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   5182881257                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    12325508295                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        23611                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         5579                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         415087                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         175914                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        33236                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         5824                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         600381                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         203065                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1462697                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       582434                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           582434                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         6008                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5972                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           11980                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          972                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          725                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1697                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       133175                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       114037                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247212                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        23611                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         5579                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          415087                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          309089                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        33236                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5824                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          600381                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          317102                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1709909                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        23611                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         5579                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         415087                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         309089                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        33236                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5824                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         600381                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         317102                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1709909                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000678                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000358                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014158                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.035188                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000451                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.011343                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.031596                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.017315                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.877330                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.798727                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.838147                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.791152                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.794483                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.792575                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.603935                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.520112                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.565268                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000678                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000358                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014158                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.280240                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000451                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.011343                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.207277                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.096536                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000678                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000358                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014158                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.280240                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000451                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.011343                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.207277                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.096536                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78937.500000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        79000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72234.090522                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 74477.544265                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        94950                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73891.886931                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77239.362375                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 74514.431730                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1601.238854                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2809.837945                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2175.386615                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   664.470741                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5134.326389                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  2578.698885                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71504.585274                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79028.080456                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 74697.875334                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78937.500000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 72234.090522                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 71717.040003                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        94950                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 73891.886931                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 78853.475794                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 74669.729837                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78937.500000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 72234.090522                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 71717.040003                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        94950                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 73891.886931                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 78853.475794                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 74669.729837                       # average overall miss latency
+system.l2c.overall_misses::cpu0.inst             6041                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            69866                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           16                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             6670                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            83240                       # number of overall misses
+system.l2c.overall_misses::total               165847                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1149750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker       368000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    435967250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    468270999                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1231000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    485141500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    483349999                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1875478498                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      9144593                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     12320478                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     21465071                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       441981                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      3192363                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      3634344                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   4462150559                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   6003353008                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  10465503567                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      1149750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       368000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    435967250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   4930421558                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker      1231000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    485141500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   6486703007                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     12340982065                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      1149750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       368000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    435967250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   4930421558                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      1231000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    485141500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   6486703007                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    12340982065                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        22724                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         4443                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         399717                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         172044                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        33212                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         5802                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         614540                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         207939                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1460421                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       583128                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           583128                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         6814                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5163                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           11977                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          974                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          747                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1721                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       111112                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       136270                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247382                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        22724                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         4443                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          399717                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          283156                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        33212                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         5802                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          614540                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          344209                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1707803                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        22724                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         4443                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         399717                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         283156                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        33212                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         5802                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         614540                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         344209                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1707803                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000528                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000450                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.015113                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.036741                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000482                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.010854                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.030600                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.017409                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.835192                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.859190                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.845537                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.787474                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.788487                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.787914                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.571900                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.564152                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.567632                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000528                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000450                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.015113                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.246740                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000482                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.010854                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.241830                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.097111                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000528                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000450                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.015113                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.246740                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000482                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.010854                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.241830                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.097111                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95812.500000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       184000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72168.059924                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 74081.790698                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76937.500000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72734.857571                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 75962.596102                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 73765.132665                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1606.851696                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2777.384581                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2119.588328                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   576.246415                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5419.971138                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  2680.194690                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70220.325108                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78090.365233                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 74528.945372                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95812.500000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker       184000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 72168.059924                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 70569.684224                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76937.500000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 72734.857571                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 77927.715125                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 74411.849868                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95812.500000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker       184000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 72168.059924                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 70569.684224                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76937.500000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 72734.857571                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 77927.715125                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 74411.849868                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -624,168 +612,168 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               66093                       # number of writebacks
-system.l2c.writebacks::total                    66093                       # number of writebacks
+system.l2c.writebacks::writebacks               66806                       # number of writebacks
+system.l2c.writebacks::total                    66806                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            40                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data            37                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.data            26                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                79                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                75                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             40                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             37                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.data             26                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 79                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 75                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            40                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            37                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.data            26                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                79                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           16                       # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::total                75                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           12                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         5872                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         6150                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           15                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         6802                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         6390                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           25247                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         5271                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4770                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        10041                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          769                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          576                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1345                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        80429                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        59312                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        139741                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker           16                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         6036                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         6284                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           16                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         6663                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         6337                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           25350                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         5691                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4436                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        10127                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          767                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          589                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1356                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        63545                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        76877                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        140422                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           12                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         5872                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        86579                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         6802                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        65702                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           164988                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           16                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         6036                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        69829                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         6663                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        83214                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           165772                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker           12                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         5872                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        86579                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           15                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         6802                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        65702                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          164988                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1063000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       133500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    350406250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    380974999                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1239250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    417280250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    414218499                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1565315748                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     52852722                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     48053192                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    100905914                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7702266                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      5777069                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     13479335                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4750287699                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3948467988                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8698755687                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1063000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    350406250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   5131262698                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1239250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    417280250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   4362686487                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  10264071435                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1063000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       133500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    350406250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   5131262698                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1239250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    417280250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   4362686487                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  10264071435                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6908499                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 110354445727                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2586249                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  56865414992                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167229355467                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1097294498                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  16505203944                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  17602498442                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6908499                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 111451740225                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2586249                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  73370618936                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184831853909                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000678                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000358                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014146                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.034960                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000451                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.031468                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.017261                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.877330                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.798727                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.838147                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.791152                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.794483                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.792575                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.603935                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.520112                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.565268                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000678                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000358                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014146                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.280110                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000451                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.207195                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.096489                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000678                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000358                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014146                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.280110                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000451                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.207195                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.096489                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59674.088896                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61947.154309                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61346.699500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64822.926291                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 62000.069236                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.076836                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10074.044444                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.388905                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.950585                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.633681                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10021.810409                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.876923                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66571.148975                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 62249.130084                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59674.088896                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59266.827961                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61346.699500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66401.121534                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 62211.017983                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59674.088896                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59266.827961                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61346.699500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66401.121534                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 62211.017983                       # average overall mshr miss latency
+system.l2c.overall_mshr_misses::cpu0.inst         6036                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        69829                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           16                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         6663                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        83214                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          165772                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1001750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       343500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    359682000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    387178249                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1034000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    400959000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    402487249                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1552685748                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     57050142                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     44722851                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    101772993                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7680764                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      5892086                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     13572850                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3668395937                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5048276480                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8716672417                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1001750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       343500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    359682000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4055574186                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1034000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    400959000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   5450763729                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  10269358165                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1001750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       343500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    359682000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4055574186                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1034000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    400959000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   5450763729                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  10269358165                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6890749                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12335372988                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2843750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154881314980                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167226422467                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1073382998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  16528122341                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  17601505339                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6890749                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13408755986                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2843750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171409437321                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184827927806                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000528                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000450                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015101                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036526                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000482                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010842                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030475                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.017358                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.835192                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.859190                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.845537                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.787474                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.788487                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.787914                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.571900                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.564152                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.567632                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000528                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000450                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015101                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.246610                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000482                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010842                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.241754                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.097067                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000528                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000450                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015101                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.246610                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000482                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010842                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.241754                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.097067                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       171750                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59589.463221                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61613.343253                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        64625                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60176.947321                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63513.847089                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 61249.930888                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10024.625198                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.796889                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.668510                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10014.033898                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.541596                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10009.476401                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57729.104367                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65666.928730                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 62074.834549                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       171750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59589.463221                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58078.651935                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        64625                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60176.947321                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65502.964994                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61948.689556                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       171750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59589.463221                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58078.651935                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        64625                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60176.947321                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65502.964994                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61948.689556                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -806,62 +794,62 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    58721934                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2742702                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2742701                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            769189                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           769189                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           582434                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           35028                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         18623                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          53651                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           259025                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          259025                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       831060                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2542800                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        15169                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        56113                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1201524                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      3348368                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        16175                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        77084                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8088293                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     26573504                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     39205457                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        22316                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        94444                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     38427456                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     43600612                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        23296                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       132944                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          148080029                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             148080029                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         4928740                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4918843977                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    58718575                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2740966                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2740965                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            769183                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           769183                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           583128                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           35123                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         18657                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          53780                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           259272                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          259272                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       800244                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1073141                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        13760                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        56807                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1229764                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4820581                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        15635                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        75586                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8085518                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     25589824                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     34686241                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        17772                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        90896                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     39333696                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     48239320                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        23208                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       132848                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          148113805                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             148113805                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4885896                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4921313376                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1872939397                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1803473389                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2324821689                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1514355955                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           9616940                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           9338456                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          32646700                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          34226949                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy        2706859206                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy        2770248418                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy        2444231662                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy        3257977460                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy          10370957                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer8.occupancy           9851958                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy          44131664                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer9.occupancy          42643941                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      47398263                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16322928                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16322928                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8086                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8086                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8852                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                      47398342                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16322915                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16322915                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                8083                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               8083                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8836                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
@@ -883,12 +871,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2384396                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2384364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                32662028                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40729                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17704                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                32661996                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40713                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17672                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
@@ -910,14 +898,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2392725                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2392677                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            123503253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               123503253                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             21724000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total            123503205                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               123503205                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy             21713000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4432000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              4424000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -963,19 +951,19 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2376310000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2376281000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         37739478366                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                6715650                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted          5214611                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           297509                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             4164563                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                3259277                       # Number of BTB hits
+system.iobus.respLayer1.occupancy         38174483356                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
+system.cpu0.branchPred.lookups                6117114                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted          4670626                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           296157                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             3842728                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                2949969                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            78.262161                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 722080                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             28659                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            76.767572                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 683314                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             28361                       # Number of incorrect RAS predictions.
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -999,25 +987,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    30314049                       # DTB read hits
-system.cpu0.dtb.read_misses                     28675                       # DTB read misses
-system.cpu0.dtb.write_hits                    5612279                       # DTB write hits
-system.cpu0.dtb.write_misses                     4120                       # DTB write misses
+system.cpu0.dtb.read_hits                     8969403                       # DTB read hits
+system.cpu0.dtb.read_misses                     29343                       # DTB read misses
+system.cpu0.dtb.write_hits                    5210557                       # DTB write hits
+system.cpu0.dtb.write_misses                     5731                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1934                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1024                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   293                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    1733                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1050                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   278                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      686                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                30342724                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5616399                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      596                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 8998746                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5216288                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         35926328                       # DTB hits
-system.cpu0.dtb.misses                          32795                       # DTB misses
-system.cpu0.dtb.accesses                     35959123                       # DTB accesses
+system.cpu0.dtb.hits                         14179960                       # DTB hits
+system.cpu0.dtb.misses                          35074                       # DTB misses
+system.cpu0.dtb.accesses                     14215034                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1039,8 +1027,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                     4601822                       # ITB inst hits
-system.cpu0.itb.inst_misses                      5333                       # ITB inst misses
+system.cpu0.itb.inst_hits                     4277605                       # ITB inst hits
+system.cpu0.itb.inst_misses                      5145                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -1049,544 +1037,584 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1359                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1215                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1531                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1426                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                 4607155                       # ITB inst accesses
-system.cpu0.itb.hits                          4601822                       # DTB hits
-system.cpu0.itb.misses                           5333                       # DTB misses
-system.cpu0.itb.accesses                      4607155                       # DTB accesses
-system.cpu0.numCycles                       298758505                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                 4282750                       # ITB inst accesses
+system.cpu0.itb.hits                          4277605                       # DTB hits
+system.cpu0.itb.misses                           5145                       # DTB misses
+system.cpu0.itb.accesses                      4282750                       # DTB accesses
+system.cpu0.numCycles                        70248238                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          12556555                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      35349888                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                    6715650                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           3981357                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                      8343175                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1485021                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                     73668                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles              62934939                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                5979                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles        43768                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles      1358657                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          326                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  4600051                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               159705                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   2319                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples          86381436                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.526874                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.794731                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          11931842                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      32451975                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    6117114                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           3633283                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                      7612739                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1460869                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                     60951                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles              20309232                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles                6063                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles        46682                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles      1377400                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          299                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  4276074                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               156796                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   2089                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples          42393450                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.988978                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.370199                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                78045507     90.35%     90.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  675063      0.78%     91.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                  847046      0.98%     92.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  783211      0.91%     93.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1013921      1.17%     94.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  572462      0.66%     94.86% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  659407      0.76%     95.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  359642      0.42%     96.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 3425177      3.97%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                34788183     82.06%     82.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  572054      1.35%     83.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                  825907      1.95%     85.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  686377      1.62%     86.98% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                  779180      1.84%     88.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  565083      1.33%     90.15% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  677221      1.60%     91.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  357838      0.84%     92.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 3141607      7.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            86381436                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.022479                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.118323                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                13622847                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             63604727                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  7412124                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               742617                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                999121                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              974392                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                66422                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              44125799                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               218867                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                999121                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                14363042                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               26099881                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      33731509                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  7356267                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              3831616                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              43013829                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                  321                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                629927                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              2476084                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents              94                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands           43352703                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            198103413                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       178854732                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             5396                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             34867311                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 8485392                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts            643580                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        598183                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  7434614                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             8769305                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6206849                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1218439                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1296110                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  40716219                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1133567                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 61584494                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            78672                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6465857                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     13399979                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        300001                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     86381436                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.712937                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.420531                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            42393450                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.087079                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.461961                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                12487890                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             21493629                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  6874468                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               552722                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                984741                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              950951                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                64626                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              40558878                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               212020                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                984741                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                13064503                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                5883311                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      13498743                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  6804692                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              2157460                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              39446559                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                  311                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                442642                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1180293                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents             145                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands           39856275                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            180582545                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       163877057                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             4135                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             31488132                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 8368142                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            460013                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        416638                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  5509006                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             7758217                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5771757                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1123661                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1193308                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  37348678                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded             906063                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 37718806                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            82800                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6312476                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     13233696                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        257258                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     42393450                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.889732                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.506737                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           63313818     73.30%     73.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            8088215      9.36%     82.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3310781      3.83%     86.49% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2721682      3.15%     89.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            7122842      8.25%     97.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1038791      1.20%     99.09% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             532976      0.62%     99.71% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             192156      0.22%     99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              60175      0.07%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           27027469     63.75%     63.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            5904750     13.93%     77.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3167008      7.47%     85.15% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2470651      5.83%     90.98% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2117188      4.99%     95.97% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5             941206      2.22%     98.20% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             520081      1.23%     99.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             187957      0.44%     99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              57140      0.13%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       86381436                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       42393450                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  26298      0.46%      0.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                   452      0.01%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5416194     95.59%     96.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               223026      3.94%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  26875      2.51%      2.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                   458      0.04%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                836202     77.98%     80.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               208765     19.47%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass            15923      0.03%      0.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             24790294     40.25%     40.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               50109      0.08%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                 12      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              9      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc           806      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     40.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            30788025     49.99%     90.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5939307      9.64%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass            14551      0.04%      0.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             22694630     60.17%     60.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               47979      0.13%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                 14      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc             10      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc           680      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc           12      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9430195     25.00%     85.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5530734     14.66%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              61584494                       # Type of FU issued
-system.cpu0.iq.rate                          0.206135                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    5665970                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.092003                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         215315704                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         48322789                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     38367249                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              11842                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              6226                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         5089                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              67228191                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   6350                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          325894                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              37718806                       # Type of FU issued
+system.cpu0.iq.rate                          0.536936                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1072300                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.028429                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         119012569                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         44575137                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     34852276                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads               8350                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              4654                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         3869                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              38772197                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   4358                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          316382                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1367932                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2587                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        13911                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       563678                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1375838                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2694                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        13105                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       538991                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads     22510150                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked         5899                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2149907                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked         5937                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                999121                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               20412775                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               272757                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           41952562                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts            83343                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              8769305                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6206849                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            796686                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 50755                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 3694                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         13911                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        151015                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       116203                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              267218                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             61206576                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             30649831                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           377918                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                984741                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                4273547                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                99764                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           38372810                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts            83727                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              7758217                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             5771757                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            578717                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 40350                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 3282                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         13105                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        151036                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       117828                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              268864                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             37337135                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9286340                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           381671                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       102776                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    36543183                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 5550332                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5893352                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.204870                       # Inst execution rate
-system.cpu0.iew.wb_sent                      61019070                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     38372338                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 20674113                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 38142518                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       118069                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    14769450                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 4962843                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5483110                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.531503                       # Inst execution rate
+system.cpu0.iew.wb_sent                      37142523                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     34856145                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 18592748                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 35683758                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.128439                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.542023                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.496185                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.521042                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        6195680                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         833566                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           232261                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     85382315                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.412432                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.299663                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        6125993                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         648805                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           232656                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     41408709                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.767702                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.726975                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     71262923     83.46%     83.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7740236      9.07%     92.53% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      2004904      2.35%     94.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1114217      1.30%     96.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4       806577      0.94%     97.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       503262      0.59%     97.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       497454      0.58%     98.30% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       227564      0.27%     98.57% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1225178      1.43%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     29445863     71.11%     71.11% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      5939620     14.34%     85.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      1940870      4.69%     90.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1013361      2.45%     92.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4       759448      1.83%     94.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       515426      1.24%     95.67% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       408347      0.99%     96.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       223076      0.54%     97.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1162698      2.81%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     85382315                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            26835114                       # Number of instructions committed
-system.cpu0.commit.committedOps              35214409                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     41408709                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            24071577                       # Number of instructions committed
+system.cpu0.commit.committedOps              31789563                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      13044544                       # Number of memory references committed
-system.cpu0.commit.loads                      7401373                       # Number of loads committed
-system.cpu0.commit.membars                     236456                       # Number of memory barriers committed
-system.cpu0.commit.branches                   4918099                       # Number of branches committed
-system.cpu0.commit.fp_insts                      5062                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 31243705                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              531450                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1225178                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      11615145                       # Number of memory references committed
+system.cpu0.commit.loads                      6382379                       # Number of loads committed
+system.cpu0.commit.membars                     231812                       # Number of memory barriers committed
+system.cpu0.commit.branches                   4351457                       # Number of branches committed
+system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 28135168                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              498959                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        20133954     63.34%     63.34% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          39784      0.13%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc          680      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        6382379     20.08%     83.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5232766     16.46%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::total         31789563                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1162698                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   124649951                       # The number of ROB reads
-system.cpu0.rob.rob_writes                   83821170                       # The number of ROB writes
-system.cpu0.timesIdled                        1018994                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                      212377069                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  4911896145                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   26765511                       # Number of Instructions Simulated
-system.cpu0.committedOps                     35144806                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             26765511                       # Number of Instructions Simulated
-system.cpu0.cpi                             11.162070                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                       11.162070                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.089589                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.089589                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               273626518                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               37917674                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     4695                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                     986                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads              148789996                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                678362                       # number of misc regfile writes
-system.cpu0.icache.tags.replacements           415188                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.568306                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            4152259                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           415700                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             9.988595                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       7103550250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.568306                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999157                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999157                       # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads                    77292791                       # The number of ROB reads
+system.cpu0.rob.rob_writes                   76817595                       # The number of ROB writes
+system.cpu0.timesIdled                         365665                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       27854788                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5140997105                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   23990835                       # Number of Instructions Simulated
+system.cpu0.committedOps                     31708821                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             23990835                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.928128                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.928128                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.341515                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.341515                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               174285855                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               34604955                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     3294                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                     912                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads               79299010                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                500883                       # number of misc regfile writes
+system.cpu0.icache.tags.replacements           399739                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.543627                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            3844274                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           400251                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             9.604658                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       7097393250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.543627                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999109                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999109                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          5015647                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         5015647                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      4152259                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        4152259                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      4152259                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         4152259                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      4152259                       # number of overall hits
-system.cpu0.icache.overall_hits::total        4152259                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       447663                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       447663                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       447663                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        447663                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       447663                       # number of overall misses
-system.cpu0.icache.overall_misses::total       447663                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6158685000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6158685000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   6158685000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6158685000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   6158685000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6158685000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      4599922                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      4599922                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      4599922                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      4599922                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      4599922                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      4599922                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.097320                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.097320                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.097320                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.097320                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.097320                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.097320                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13757.413501                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13757.413501                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13757.413501                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13757.413501                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13757.413501                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13757.413501                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4464                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses          4676219                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         4676219                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      3844274                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        3844274                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      3844274                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         3844274                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      3844274                       # number of overall hits
+system.cpu0.icache.overall_hits::total        3844274                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       431668                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       431668                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       431668                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        431668                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       431668                       # number of overall misses
+system.cpu0.icache.overall_misses::total       431668                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5966691765                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   5966691765                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   5966691765                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   5966691765                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   5966691765                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   5966691765                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      4275942                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      4275942                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      4275942                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      4275942                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      4275942                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      4275942                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100953                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.100953                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100953                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.100953                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100953                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.100953                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13822.409271                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13822.409271                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13822.409271                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13822.409271                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13822.409271                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13822.409271                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4149                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              167                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              172                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    26.730539                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.122093                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        31938                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        31938                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        31938                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        31938                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        31938                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        31938                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       415725                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       415725                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       415725                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       415725                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       415725                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       415725                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5022987594                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5022987594                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5022987594                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5022987594                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5022987594                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5022987594                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9487250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9487250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9487250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total      9487250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.090377                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.090377                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.090377                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.090377                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.090377                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.090377                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12082.476623                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12082.476623                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12082.476623                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12082.476623                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12082.476623                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12082.476623                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        31390                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        31390                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        31390                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        31390                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        31390                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        31390                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       400278                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       400278                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       400278                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       400278                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       400278                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       400278                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4859637603                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   4859637603                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4859637603                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   4859637603                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4859637603                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   4859637603                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9490000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9490000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9490000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total      9490000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093612                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093612                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093612                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.093612                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093612                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.093612                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12140.656251                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12140.656251                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12140.656251                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12140.656251                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12140.656251                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12140.656251                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           298882                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          483.456705                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10027143                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           299266                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            33.505787                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         44230250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   483.456705                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.944251                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.944251                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          384                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          384                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         48541082                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        48541082                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6144970                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6144970                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3563655                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3563655                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       144672                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       144672                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       142233                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       142233                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9708625                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9708625                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9708625                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9708625                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       393929                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       393929                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1644577                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1644577                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9244                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9244                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7866                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7866                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2038506                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2038506                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2038506                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2038506                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5542234631                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5542234631                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  82471404032                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  82471404032                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     94602484                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     94602484                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     50293768                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     50293768                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  88013638663                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  88013638663                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  88013638663                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  88013638663                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6538899                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6538899                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5208232                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5208232                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       153916                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       153916                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       150099                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       150099                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     11747131                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     11747131                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11747131                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     11747131                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.060244                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.060244                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.315765                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.315765                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060059                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.060059                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052405                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052405                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.173532                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.173532                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.173532                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.173532                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.120656                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.120656                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50147.487185                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 50147.487185                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10233.933795                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10233.933795                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6393.817442                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6393.817442                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43175.560270                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 43175.560270                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43175.560270                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 43175.560270                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs        10878                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         5936                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs              678                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            116                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.044248                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    51.172414                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.replacements           275002                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          479.873805                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs            9429051                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           275514                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            34.223491                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         43985250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.873805                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.937254                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.937254                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          181                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         45805638                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        45805638                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5875796                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5875796                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3229179                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3229179                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139566                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       139566                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137212                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       137212                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9104975                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9104975                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9104975                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9104975                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       392540                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       392540                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1582550                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1582550                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8878                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         8878                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7747                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7747                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1975090                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1975090                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1975090                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1975090                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5503316358                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5503316358                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  80403947306                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  80403947306                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     91149731                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     91149731                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     49845761                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     49845761                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  85907263664                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  85907263664                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  85907263664                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  85907263664                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6268336                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6268336                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4811729                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4811729                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       148444                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       148444                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144959                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       144959                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11080065                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     11080065                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11080065                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     11080065                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.062623                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.062623                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.328894                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.328894                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059807                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059807                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053443                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053443                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.178256                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.178256                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.178256                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.178256                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14019.759408                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14019.759408                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50806.576289                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 50806.576289                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10266.921717                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10266.921717                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6434.201756                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6434.201756                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43495.366623                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 43495.366623                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43495.366623                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 43495.366623                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         9513                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         7748                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs              587                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            136                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.206133                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    56.970588                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       278268                       # number of writebacks
-system.cpu0.dcache.writebacks::total           278268                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       201648                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       201648                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1493557                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1493557                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          632                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total          632                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1695205                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1695205                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1695205                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1695205                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       192281                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       192281                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       151020                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       151020                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8612                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8612                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7866                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7866                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       343301                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       343301                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       343301                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       343301                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2438332267                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2438332267                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6681240000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6681240000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     70543016                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     70543016                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     34562232                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     34562232                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.writebacks::writebacks       255347                       # number of writebacks
+system.cpu0.dcache.writebacks::total           255347                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       203411                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       203411                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1451593                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1451593                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          468                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          468                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1655004                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1655004                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1655004                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1655004                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189129                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       189129                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130957                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       130957                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8410                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8410                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7747                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7747                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       320086                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       320086                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       320086                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       320086                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2397985131                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2397985131                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5338215866                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5338215866                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     69513767                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     69513767                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     34349239                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     34349239                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9119572267                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9119572267                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9119572267                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   9119572267                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 120538982283                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 120538982283                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1232045382                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1232045382                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 121771027665                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 121771027665                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.029406                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029406                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.028996                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.028996                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.055953                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.055953                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052405                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052405                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029224                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029224                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029224                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.029224                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12681.087923                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12681.087923                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44240.762813                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44240.762813                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8191.246633                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8191.246633                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4393.876430                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4393.876430                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7736200997                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7736200997                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7736200997                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   7736200997                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13434640527                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13434640527                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1206086382                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1206086382                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14640726909                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14640726909                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030172                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030172                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027216                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027216                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056654                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056654                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053443                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053443                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028888                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028888                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028888                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028888                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12679.098028                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12679.098028                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40763.119696                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40763.119696                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8265.608442                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8265.608442                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4433.876210                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4433.876210                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26564.362664                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26564.362664                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26564.362664                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26564.362664                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24169.132661                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24169.132661                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24169.132661                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24169.132661                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1594,15 +1622,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                8689698                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          7082612                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           415349                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             5570453                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                4730059                       # Number of BTB hits
+system.cpu1.branchPred.lookups                9293378                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          7631598                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           415998                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             5889507                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                5046361                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            84.913363                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 759549                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             43595                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            85.683929                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 797302                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             43622                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1626,25 +1654,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    21626734                       # DTB read hits
-system.cpu1.dtb.read_misses                     38691                       # DTB read misses
-system.cpu1.dtb.write_hits                    6575784                       # DTB write hits
-system.cpu1.dtb.write_misses                    12298                       # DTB write misses
+system.cpu1.dtb.read_hits                    42971422                       # DTB read hits
+system.cpu1.dtb.read_misses                     37905                       # DTB read misses
+system.cpu1.dtb.write_hits                    6976449                       # DTB write hits
+system.cpu1.dtb.write_misses                    10883                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1712                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     3023                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   279                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1918                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     2893                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   296                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      600                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                21665425                       # DTB read accesses
-system.cpu1.dtb.write_accesses                6588082                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      686                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                43009327                       # DTB read accesses
+system.cpu1.dtb.write_accesses                6987332                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         28202518                       # DTB hits
-system.cpu1.dtb.misses                          50989                       # DTB misses
-system.cpu1.dtb.accesses                     28253507                       # DTB accesses
+system.cpu1.dtb.hits                         49947871                       # DTB hits
+system.cpu1.dtb.misses                          48788                       # DTB misses
+system.cpu1.dtb.accesses                     49996659                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1666,8 +1694,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     7394895                       # ITB inst hits
-system.cpu1.itb.inst_misses                      5860                       # ITB inst misses
+system.cpu1.itb.inst_hits                     7719787                       # ITB inst hits
+system.cpu1.itb.inst_misses                      5634                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1676,546 +1704,575 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1207                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1369                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1503                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1538                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 7400755                       # ITB inst accesses
-system.cpu1.itb.hits                          7394895                       # DTB hits
-system.cpu1.itb.misses                           5860                       # DTB misses
-system.cpu1.itb.accesses                      7400755                       # DTB accesses
-system.cpu1.numCycles                       185247782                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 7725421                       # ITB inst accesses
+system.cpu1.itb.hits                          7719787                       # DTB hits
+system.cpu1.itb.misses                           5634                       # DTB misses
+system.cpu1.itb.accesses                      7725421                       # DTB accesses
+system.cpu1.numCycles                       413693823                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          18767441                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      58413381                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    8689698                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           5489608                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     12630025                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3326163                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     70879                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles              38401480                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                5864                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        46813                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles      1518730                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          309                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  7393189                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               549179                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3073                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          73717325                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.969397                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.351920                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          19372544                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      61318271                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    9293378                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           5843663                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     13362487                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3346253                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     69736                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles              80999073                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles                5941                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        42062                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles      1494344                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          284                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  7717920                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               551887                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2996                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         117635394                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.638004                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.959630                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                61095045     82.88%     82.88% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  712004      0.97%     83.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  939814      1.27%     85.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 1614257      2.19%     87.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1180828      1.60%     88.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  579149      0.79%     89.70% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 1971485      2.67%     92.37% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  418985      0.57%     92.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 5205758      7.06%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               104280280     88.65%     88.65% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  814710      0.69%     89.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  961160      0.82%     90.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 1713171      1.46%     91.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1415249      1.20%     92.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  586962      0.50%     93.32% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 1954597      1.66%     94.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  422243      0.36%     95.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 5487022      4.66%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            73717325                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.046909                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.315326                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                19856835                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             39689565                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 11370888                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               621997                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               2178040                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1113164                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                99384                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              67504859                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               329486                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               2178040                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                20884497                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               13732674                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      23091492                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 10921071                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              2909551                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              63553177                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  150                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                495727                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents              1775459                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents             454                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands           67243012                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            295535307                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       271726361                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             4962                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             47019288                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                20223723                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            581683                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        523637                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  6484055                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            11835207                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            7683859                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           982260                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         1485488                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  58475771                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             951228                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 65019700                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            99369                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       13400197                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     36106127                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        236520                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     73717325                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.882014                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.585621                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           117635394                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.022464                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.148221                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                20963679                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             81759193                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 11913295                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               809519                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               2189708                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1137363                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               100954                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              71089276                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               336011                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               2189708                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                22156707                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               33902507                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      43325786                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 11473545                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              4587141                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              67137864                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  137                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                682095                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents              3075433                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents            1010                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands           70763032                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            313108743                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       286757803                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             6623                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             50416422                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                20346610                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            765987                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        705836                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  8420477                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            12843204                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            8115826                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          1055497                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         1512633                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  61850161                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1179252                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 88896986                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            93979                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       13548762                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     36246660                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        279849                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    117635394                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.755699                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.498688                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           50542925     68.56%     68.56% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            7121407      9.66%     78.22% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            4031042      5.47%     83.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3362905      4.56%     88.25% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            5367239      7.28%     95.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1894348      2.57%     98.10% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1048738      1.42%     99.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             275398      0.37%     99.90% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              73323      0.10%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           86772303     73.76%     73.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            9298113      7.90%     81.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            4175598      3.55%     85.22% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            3594840      3.06%     88.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           10374006      8.82%     97.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1994938      1.70%     98.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1065613      0.91%     99.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             281099      0.24%     99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              78884      0.07%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       73717325                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      117635394                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  33869      1.02%      1.02% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   996      0.03%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               2994112     90.44%     91.49% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               281623      8.51%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  32152      0.41%      0.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   986      0.01%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               7573471     95.70%     96.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               306947      3.88%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass            12895      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             35505233     54.61%     54.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               59031      0.09%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                 14      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc             10      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          1556      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     54.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            22501549     34.61%     89.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            6939400     10.67%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass            14268      0.02%      0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             37614404     42.31%     42.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               61197      0.07%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                 13      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc             10      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          1706      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            43858329     49.34%     91.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            7347048      8.26%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              65019700                       # Type of FU issued
-system.cpu1.iq.rate                          0.350988                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    3310600                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.050917                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         207206368                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         72837982                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     50730101                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              11167                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              5978                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         5058                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              68311542                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   5863                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          343642                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              88896986                       # Type of FU issued
+system.cpu1.iq.rate                          0.214886                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    7913556                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.089019                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         303469985                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         76586992                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     54255274                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              15534                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              8108                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         6874                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              96788024                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   8250                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          355713                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2877094                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         3994                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        17361                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1094953                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2862172                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         4122                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        17485                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1111950                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads     11606945                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       675630                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads     31965671                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       675853                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               2178040                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               10295917                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               191116                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           59545170                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           114100                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             11835207                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             7683859                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            664311                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 56460                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 4454                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         17361                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        204103                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       160517                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              364620                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             63283569                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             21990431                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          1736131                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               2189708                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               26386476                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               363440                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           63133555                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           115239                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             12843204                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             8115826                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            883054                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 66097                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 4286                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         17485                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        204520                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       158639                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              363159                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             87164207                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             43354058                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          1732779                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       118171                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    28863200                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 6787528                       # Number of branches executed
-system.cpu1.iew.exec_stores                   6872769                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.341616                       # Inst execution rate
-system.cpu1.iew.wb_sent                      62514610                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     50735159                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 28199774                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 51433237                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       104142                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    50636612                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 7376811                       # Number of branches executed
+system.cpu1.iew.exec_stores                   7282554                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.210697                       # Inst execution rate
+system.cpu1.iew.wb_sent                      86400335                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     54262148                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 30287291                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 53873069                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.273877                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.548279                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.131165                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.562197                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       13377367                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         714708                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           317605                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     71539285                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.639790                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.672504                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       13443206                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         899403                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           316783                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    115445686                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.426296                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.378874                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     55665383     77.81%     77.81% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      7811223     10.92%     88.73% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      2101815      2.94%     91.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      1189986      1.66%     93.33% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       946066      1.32%     94.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       613597      0.86%     95.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       912617      1.28%     96.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       531458      0.74%     97.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1767140      2.47%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     97421932     84.39%     84.39% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      9594899      8.31%     92.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      2172227      1.88%     94.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      1301741      1.13%     95.71% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       988993      0.86%     96.56% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       587152      0.51%     97.07% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1008803      0.87%     97.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       534624      0.46%     98.41% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1835315      1.59%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     71539285                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            36096592                       # Number of instructions committed
-system.cpu1.commit.committedOps              45770088                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    115445686                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            38873610                       # Number of instructions committed
+system.cpu1.commit.committedOps              49214014                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      15547019                       # Number of memory references committed
-system.cpu1.commit.loads                      8958113                       # Number of loads committed
-system.cpu1.commit.membars                     191016                       # Number of memory barriers committed
-system.cpu1.commit.branches                   5856523                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5022                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 40800338                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              520894                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events              1767140                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                      16984908                       # Number of memory references committed
+system.cpu1.commit.loads                      9981032                       # Number of loads committed
+system.cpu1.commit.membars                     195536                       # Number of memory barriers committed
+system.cpu1.commit.branches                   6424997                       # Number of branches committed
+system.cpu1.commit.fp_insts                      6822                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 43926362                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              553376                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        32169137     65.37%     65.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          58263      0.12%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         1706      0.00%     65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        9981032     20.28%     85.77% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       7003876     14.23%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::total         49214014                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1835315                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   127901171                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  120555711                       # The number of ROB writes
-system.cpu1.timesIdled                         777241                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                      111530457                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5026003021                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   36015814                       # Number of Instructions Simulated
-system.cpu1.committedOps                     45689310                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             36015814                       # Number of Instructions Simulated
-system.cpu1.cpi                              5.143512                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        5.143512                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.194420                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.194420                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               292255401                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               53047565                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     3797                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                    1766                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads              133121160                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                545345                       # number of misc regfile writes
-system.cpu1.icache.tags.replacements           600500                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.750005                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            6745926                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           601012                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            11.224278                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      74974413000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.750005                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974121                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.974121                       # Average percentage of cache occupancy
+system.cpu1.rob.rob_reads                   175201017                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  127586843                       # The number of ROB writes
+system.cpu1.timesIdled                        1428644                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                      296058429                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  4796946974                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   38803971                       # Number of Instructions Simulated
+system.cpu1.committedOps                     49144375                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             38803971                       # Number of Instructions Simulated
+system.cpu1.cpi                             10.661121                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                       10.661121                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.093799                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.093799                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               391634066                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               56368159                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     5144                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                    2332                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads              202762353                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                723009                       # number of misc regfile writes
+system.cpu1.icache.tags.replacements           614589                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.738252                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            7056364                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           615101                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            11.471879                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      74953244500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.738252                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974098                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.974098                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          151                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          7994182                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         7994182                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      6745926                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        6745926                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      6745926                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         6745926                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      6745926                       # number of overall hits
-system.cpu1.icache.overall_hits::total        6745926                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       647211                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       647211                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       647211                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        647211                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       647211                       # number of overall misses
-system.cpu1.icache.overall_misses::total       647211                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8801556837                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   8801556837                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   8801556837                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   8801556837                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   8801556837                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   8801556837                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      7393137                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      7393137                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      7393137                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      7393137                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      7393137                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      7393137                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.087542                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.087542                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.087542                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.087542                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.087542                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.087542                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13599.207734                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13599.207734                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13599.207734                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13599.207734                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13599.207734                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13599.207734                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs         3107                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          341                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs              199                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    15.613065                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          341                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses          8332995                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         8332995                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      7056364                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        7056364                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      7056364                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         7056364                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      7056364                       # number of overall hits
+system.cpu1.icache.overall_hits::total        7056364                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       661505                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       661505                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       661505                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        661505                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       661505                       # number of overall misses
+system.cpu1.icache.overall_misses::total       661505                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8964922762                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   8964922762                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   8964922762                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   8964922762                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   8964922762                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   8964922762                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      7717869                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      7717869                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      7717869                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      7717869                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      7717869                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      7717869                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.085711                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.085711                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.085711                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.085711                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.085711                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.085711                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13552.312926                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13552.312926                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13552.312926                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13552.312926                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13552.312926                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13552.312926                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs         3582                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs              212                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    16.896226                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        46165                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        46165                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        46165                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        46165                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        46165                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        46165                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       601046                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       601046                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       601046                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       601046                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       601046                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       601046                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7178040035                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   7178040035                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7178040035                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   7178040035                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7178040035                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   7178040035                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3605250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3605250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3605250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      3605250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.081298                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.081298                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.081298                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.081298                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.081298                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.081298                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11942.580160                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11942.580160                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11942.580160                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11942.580160                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11942.580160                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11942.580160                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        46379                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        46379                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        46379                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        46379                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        46379                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        46379                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       615126                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       615126                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       615126                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       615126                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       615126                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       615126                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7320744820                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   7320744820                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7320744820                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   7320744820                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7320744820                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   7320744820                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3847250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3847250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3847250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      3847250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.079702                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.079702                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.079702                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.079702                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.079702                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.079702                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11901.211817                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11901.211817                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11901.211817                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11901.211817                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11901.211817                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11901.211817                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           339082                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          482.965075                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           12423447                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           339594                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            36.583235                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      71024759250                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   482.965075                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.943291                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.943291                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         57544569                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        57544569                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      8247311                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        8247311                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      3935666                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3935666                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        94453                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        94453                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        92037                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        92037                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     12182977                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        12182977                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     12182977                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       12182977                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       400036                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       400036                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1501327                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1501327                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13642                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        13642                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10758                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10758                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      1901363                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       1901363                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      1901363                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      1901363                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6052529769                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   6052529769                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  75305143416                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  75305143416                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    124772740                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    124772740                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     57202570                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     57202570                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  81357673185                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  81357673185                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  81357673185                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  81357673185                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      8647347                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      8647347                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      5436993                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      5436993                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       108095                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       108095                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102795                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       102795                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     14084340                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     14084340                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     14084340                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     14084340                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.046261                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.046261                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.276132                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.276132                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.126204                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.126204                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.104655                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.104655                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134998                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.134998                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134998                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.134998                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15129.962726                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15129.962726                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50159.054900                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 50159.054900                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9146.220496                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9146.220496                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5317.212307                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5317.212307                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42789.132420                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 42789.132420                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42789.132420                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 42789.132420                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs        27478                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets        17677                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             3226                       # number of cycles access was blocked
+system.cpu1.dcache.tags.replacements           363297                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          486.117445                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           13019165                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           363645                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            35.801853                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      71011321250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.117445                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.949448                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.949448                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          348                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.679688                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         60291027                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        60291027                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      8513196                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        8513196                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4271027                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4271027                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        99804                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        99804                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        97081                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        97081                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     12784223                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        12784223                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     12784223                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       12784223                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       403038                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       403038                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1566274                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1566274                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14187                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        14187                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10911                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10911                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      1969312                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       1969312                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      1969312                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      1969312                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6108097691                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   6108097691                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  77891341203                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  77891341203                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    131130743                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    131130743                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     58206088                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     58206088                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  83999438894                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  83999438894                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  83999438894                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  83999438894                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      8916234                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      8916234                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      5837301                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      5837301                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       113991                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       113991                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       107992                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       107992                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     14753535                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     14753535                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     14753535                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     14753535                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045203                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.045203                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.268322                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.268322                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.124457                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.124457                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.101035                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.101035                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.133481                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.133481                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.133481                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.133481                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15155.140932                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15155.140932                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 49730.341692                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 49730.341692                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9243.021287                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9243.021287                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5334.624507                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5334.624507                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42654.205577                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 42654.205577                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42654.205577                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 42654.205577                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs        29593                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets        18156                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             3287                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets            175                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     8.517669                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets   101.011429                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.003042                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets   103.748571                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       304166                       # number of writebacks
-system.cpu1.dcache.writebacks::total           304166                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       172051                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       172051                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1358464                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      1358464                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1244                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1244                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1530515                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1530515                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1530515                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1530515                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       227985                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       227985                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       142863                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       142863                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12398                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12398                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10758                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10758                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       370848                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       370848                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       370848                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       370848                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2835218608                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2835218608                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5632564954                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5632564954                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     86730259                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     86730259                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     35684430                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     35684430                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8467783562                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   8467783562                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8467783562                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   8467783562                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  62130810008                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total  62130810008                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25850406364                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25850406364                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data  87981216372                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total  87981216372                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026365                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.026365                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.026276                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.026276                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.114695                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.114695                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.104655                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.104655                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026331                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026331                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026331                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026331                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12435.987490                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12435.987490                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39426.338198                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39426.338198                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6995.504033                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6995.504033                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3317.013385                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3317.013385                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22833.569446                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22833.569446                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22833.569446                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22833.569446                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       327781                       # number of writebacks
+system.cpu1.dcache.writebacks::total           327781                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       171674                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       171674                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1403027                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      1403027                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1467                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1467                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1574701                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1574701                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1574701                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1574701                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231364                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       231364                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       163247                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       163247                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12720                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12720                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10911                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10911                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       394611                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       394611                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       394611                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       394611                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2878773157                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2878773157                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   7001686259                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   7001686259                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89753005                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89753005                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     36382912                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     36382912                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9880459416                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   9880459416                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9880459416                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   9880459416                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231749012                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231749012                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25869959988                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25869959988                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195101709000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195101709000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025949                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025949                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027966                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027966                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.111588                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.111588                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.101035                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.101035                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026747                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026747                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026747                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026747                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12442.614914                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12442.614914                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42890.137393                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42890.137393                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7056.053852                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7056.053852                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3334.516726                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3334.516726                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25038.479454                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25038.479454                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25038.479454                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25038.479454                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2239,18 +2296,18 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737834287366                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1737834287366                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737834287366                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1737834287366                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735350782356                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1735350782356                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735350782356                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1735350782356                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   45161                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   42636                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   47884                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   50408                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 0d3018ad7..d345e80f2 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,137 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.526170                       # Number of seconds simulated
-sim_ticks                                2526169857500                       # Number of ticks simulated
-final_tick                               2526169857500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.526192                       # Number of seconds simulated
+sim_ticks                                2526192217500                       # Number of ticks simulated
+final_tick                               2526192217500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  58326                       # Simulator instruction rate (inst/s)
-host_op_rate                                    75048                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2443063970                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 467448                       # Number of bytes of host memory used
-host_seconds                                  1034.02                       # Real time elapsed on the host
-sim_insts                                    60309637                       # Number of instructions simulated
-sim_ops                                      77601213                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  56578                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72800                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2369913329                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 467016                       # Number of bytes of host memory used
+host_seconds                                  1065.94                       # Real time elapsed on the host
+sim_insts                                    60309034                       # Number of instructions simulated
+sim_ops                                      77600502                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         2880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            797632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9095320                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129433624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       797632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          797632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3785024                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            796992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9095192                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129433368                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       796992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          796992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3784320                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6801096                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6800392                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           45                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           53                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12463                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142150                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15096868                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59141                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12453                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142148                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15096864                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59130                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813159                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47319725                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1140                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               813148                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47319307                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1343                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               315748                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3600439                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51237103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          315748                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315748                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1498325                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1193931                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2692256                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1498325                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47319725                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1140                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               315491                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3600356                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51236548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          315491                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315491                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1498033                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1193920                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2691954                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1498033                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47319307                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1343                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              315748                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4794370                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53929359                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15096868                       # Number of read requests accepted
-system.physmem.writeReqs                       813159                       # Number of write requests accepted
-system.physmem.readBursts                    15096868                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813159                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                960809152                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   5390400                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6824768                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 129433624                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6801096                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    84225                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706499                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4674                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              943297                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              937033                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              936962                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              936535                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              942693                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              936569                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              936319                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              936043                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              943596                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              936992                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             936414                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             935912                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             943556                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             937007                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             937039                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             936676                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6606                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6375                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6521                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6552                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6461                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6711                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6720                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6668                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7045                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6826                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6497                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6136                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7072                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6672                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6956                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6819                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              315491                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4794277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53928501                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15096864                       # Number of read requests accepted
+system.physmem.writeReqs                       813148                       # Number of write requests accepted
+system.physmem.readBursts                    15096864                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     813148                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                961540928                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   4658368                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6820736                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 129433368                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6800392                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    72787                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706544                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4695                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              943480                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              937980                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              937559                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              937528                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              943087                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              937982                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              937070                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              936990                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              943982                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              938303                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             937119                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             936407                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             943924                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             938214                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             937241                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             937211                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6601                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6388                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6528                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6554                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6464                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6726                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6713                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6652                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7031                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6803                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6461                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6104                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7064                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6684                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6965                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6836                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2526168741500                       # Total gap between requests
+system.physmem.totGap                    2526191083500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
 system.physmem.readPktSize::3                14942208                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154622                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154618                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59141                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1044851                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    985737                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    938636                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    947948                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    933228                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    933834                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2717841                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2709185                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3589675                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     37568                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    33871                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    34960                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    32201                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    30053                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    21726                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    21191                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  59130                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1056388                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    996212                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    954030                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1063517                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    957350                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1019929                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2630220                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2535649                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3302007                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    132277                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   114408                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   104766                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                   100921                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19448                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18562                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18244                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      130                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -159,47 +159,47 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1817                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5776                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6376                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6039                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6697                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      587                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      595                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      576                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      540                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      538                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2638                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6394                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6781                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6438                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6465                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
@@ -208,67 +208,50 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       949853                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     1012.832967                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     998.129194                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev      95.600820                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           4614      0.49%      0.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         3555      0.37%      0.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1868      0.20%      1.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1270      0.13%      1.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          998      0.11%      1.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          697      0.07%      1.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          628      0.07%      1.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          802      0.08%      1.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       935421     98.48%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         949853                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5541                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2709.372676                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    121858.968991                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         5537     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.04%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       995555                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      972.685250                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     907.127186                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     202.423056                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22972      2.31%      2.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        19885      2.00%      4.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8241      0.83%      5.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2302      0.23%      5.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2369      0.24%      5.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1811      0.18%      5.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8514      0.86%      6.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          964      0.10%      6.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       928497     93.26%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         995555                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6226                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2413.115644                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    115125.420570                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         6222     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5541                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5541                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.245082                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.302826                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.619957                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3691     66.61%     66.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 16      0.29%     66.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                178      3.21%     70.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1008     18.19%     88.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 44      0.79%     89.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 25      0.45%     89.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 20      0.36%     89.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 16      0.29%     90.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  5      0.09%     90.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  2      0.04%     90.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.02%     90.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  1      0.02%     90.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.02%     90.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  2      0.04%     90.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  1      0.02%     90.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                143      2.58%     93.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                305      5.50%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                 21      0.38%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                 14      0.25%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                 20      0.36%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                 15      0.27%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  5      0.09%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  3      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  3      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5541                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   571195583500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              674382869750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  75063215000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 28124071250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       38047.64                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1873.36                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            6226                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6226                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.117571                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.060113                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.446555                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3515     56.46%     56.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 41      0.66%     57.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1615     25.94%     83.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                842     13.52%     96.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 76      1.22%     97.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 41      0.66%     98.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 38      0.61%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 41      0.66%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 16      0.26%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6226                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   389908010000                       # Total ticks spent queuing
+system.physmem.totMemAccLat              671609453750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  75120385000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25952.21                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44921.00                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         380.34                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44702.21                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         380.63                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.70                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       51.24                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.69                       # Average system write bandwidth in MiByte/s
@@ -276,15 +259,19 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           2.99                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         7.11                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.53                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14041195                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     91389                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.68                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158778.41                       # Average gap between requests
-system.physmem.pageHitRate                      93.47                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.34                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         6.80                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        27.01                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14044000                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     91096                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.45                       # Row buffer hit rate for writes
+system.physmem.avgGap                       158779.96                       # Average gap between requests
+system.physmem.pageHitRate                      93.42                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2186359463750                       # Time in different power states
+system.physmem.memoryStateTime::REF       84354920000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      255472398750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
@@ -297,50 +284,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst           25
 system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54878638                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16149508                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16149508                       # Transaction distribution
+system.membus.throughput                     54877773                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16149486                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16149486                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763349                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763349                       # Transaction distribution
-system.membus.trans_dist::Writeback             59141                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4671                       # Transaction distribution
+system.membus.trans_dist::Writeback             59130                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4692                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4674                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131433                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131433                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4695                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131451                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131451                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383044                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3760                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885845                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272653                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885868                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272676                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29884416                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     29884416                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34157069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34157092                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390454                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16697056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19095098                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16696096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19094138                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119537664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           138632762                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              138632762                       # Total data (bytes)
+system.membus.tot_pkt_size::total           138631802                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              138631802                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1487078000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1486816000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3653000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3620500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17362845500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17362899000                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4737809043                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4734189076                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37210156152                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        36898450149                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -348,7 +335,7 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48266001                       # Throughput (bytes/s)
+system.iobus.throughput                      48265574                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq             16125556                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            16125556                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8174                       # Transaction distribution
@@ -458,18 +445,18 @@ system.iobus.reqLayer25.occupancy         14942208000                       # La
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374870000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         37245686848                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         37675624851                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14755327                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11837490                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            706705                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9530563                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7665782                       # Number of BTB hits
+system.cpu.branchPred.lookups                14753661                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11836576                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            705670                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9513727                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7668660                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.433674                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1400618                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              72971                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.606265                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1399145                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              72578                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -493,25 +480,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51187284                       # DTB read hits
-system.cpu.dtb.read_misses                      65383                       # DTB read misses
-system.cpu.dtb.write_hits                    11703682                       # DTB write hits
-system.cpu.dtb.write_misses                     15916                       # DTB write misses
+system.cpu.dtb.read_hits                     51183231                       # DTB read hits
+system.cpu.dtb.read_misses                      65223                       # DTB read misses
+system.cpu.dtb.write_hits                    11700953                       # DTB write hits
+system.cpu.dtb.write_misses                     15725                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3484                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2464                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.flush_entries                     3479                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      2504                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                    408                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1363                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51252667                       # DTB read accesses
-system.cpu.dtb.write_accesses                11719598                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1339                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51248454                       # DTB read accesses
+system.cpu.dtb.write_accesses                11716678                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          62890966                       # DTB hits
-system.cpu.dtb.misses                           81299                       # DTB misses
-system.cpu.dtb.accesses                      62972265                       # DTB accesses
+system.cpu.dtb.hits                          62884184                       # DTB hits
+system.cpu.dtb.misses                           80948                       # DTB misses
+system.cpu.dtb.accesses                      62965132                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -533,8 +520,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     11527099                       # ITB inst hits
-system.cpu.itb.inst_misses                      11249                       # ITB inst misses
+system.cpu.itb.inst_hits                     11525561                       # ITB inst hits
+system.cpu.itb.inst_misses                      11159                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -543,113 +530,113 @@ system.cpu.itb.flush_tlb                            2                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2504                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2509                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                      2978                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 11538348                       # ITB inst accesses
-system.cpu.itb.hits                          11527099                       # DTB hits
-system.cpu.itb.misses                           11249                       # DTB misses
-system.cpu.itb.accesses                      11538348                       # DTB accesses
-system.cpu.numCycles                        477119451                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 11536720                       # ITB inst accesses
+system.cpu.itb.hits                          11525561                       # DTB hits
+system.cpu.itb.misses                           11159                       # DTB misses
+system.cpu.itb.accesses                      11536720                       # DTB accesses
+system.cpu.numCycles                        477128882                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29745347                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       90343663                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14755327                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9066400                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      20160515                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4659374                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     121718                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               98274067                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2638                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         88444                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      2690508                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          430                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11523637                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                709778                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5230                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          154294046                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.730147                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.081756                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29759197                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       90327124                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14753661                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9067805                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      20158177                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4657193                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     122600                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               98301886                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2694                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         86268                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      2686675                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          550                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  11522069                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                710692                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5197                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          154327188                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.729776                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.081128                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                134149007     86.94%     86.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1305162      0.85%     87.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1712027      1.11%     88.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2298089      1.49%     90.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2109453      1.37%     91.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1103374      0.72%     92.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2555030      1.66%     94.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   746204      0.48%     94.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  8315700      5.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                134184573     86.95%     86.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1304702      0.85%     87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1713961      1.11%     88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2295969      1.49%     90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2111581      1.37%     91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1105061      0.72%     92.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2556088      1.66%     94.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   746376      0.48%     94.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  8308877      5.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            154294046                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.030926                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.189352                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 31777956                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             100129696                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18080387                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1265250                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3040757                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              1958128                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                172070                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              107328179                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                570705                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3040757                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 33516419                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                38693091                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       55142047                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  17591419                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6310313                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102323009                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   472                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1000039                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4066050                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              733                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           106393961                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             474042454                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        432890289                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10421                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              78727775                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27666185                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1171025                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1077190                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12642564                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19725934                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13308899                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1965192                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2472766                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   95138203                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1987496                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 122932074                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            165549                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18954995                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     47273204                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         505173                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     154294046                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.796739                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.515436                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            154327188                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.030922                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.189314                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 31784305                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             100158613                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18079626                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1265080                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3039564                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              1958546                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                172069                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              107310478                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                569843                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3039564                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 33522780                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                38730372                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       55131073                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  17590016                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6313383                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102310347                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   498                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 999968                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4068660                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              821                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           106387059                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             473967662                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        432826370                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10390                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              78726997                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 27660061                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1170574                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1076856                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12635163                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             19719056                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13304976                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1944651                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2472247                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   95130107                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1987847                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 122918672                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            165693                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18947879                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     47268855                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         505540                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     154327188                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.796481                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.515149                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           109928517     71.25%     71.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14405522      9.34%     80.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6874407      4.46%     85.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5677816      3.68%     88.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12311103      7.98%     96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2805861      1.82%     98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1693952      1.10%     99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              468083      0.30%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              128785      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           109964387     71.25%     71.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14401004      9.33%     80.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             6880878      4.46%     85.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5675452      3.68%     88.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12310168      7.98%     96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2806019      1.82%     98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1694480      1.10%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              466491      0.30%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              128309      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       154294046                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       154327188                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   61713      0.70%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   61903      0.70%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      4      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.70% # attempts to use FU when none available
@@ -678,13 +665,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.70% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8365366     94.65%     95.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                411034      4.65%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8364845     94.62%     95.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                413343      4.68%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             28518      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              57971139     47.16%     47.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                93360      0.08%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              57967032     47.16%     47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                93290      0.08%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.26% # Type of FU issued
@@ -697,11 +684,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.26% # Ty
 system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  25      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  21      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc              18      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc              13      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.26% # Type of FU issued
@@ -710,404 +697,440 @@ system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.26% # Ty
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc           19      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc           14      0.00%     47.26% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             52513425     42.72%     89.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12323457     10.02%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             52507324     42.72%     89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12320347     10.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              122932074                       # Type of FU issued
-system.cpu.iq.rate                           0.257655                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8838117                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.071894                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          409219406                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         116097301                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85490758                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               23382                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12446                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10288                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              131729199                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12474                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           624027                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              122918672                       # Type of FU issued
+system.cpu.iq.rate                           0.257622                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8840095                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.071918                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          409227562                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         116082546                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     85482417                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               23345                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12482                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10295                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              131717793                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12456                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           625155                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4071144                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6793                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        30196                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1576838                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4064409                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6818                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        30381                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1573005                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34107946                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        680806                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107982                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        680619                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3040757                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                30225758                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                434257                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            97346977                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            205962                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19725934                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13308899                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1415361                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 113324                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  3429                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          30196                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         351437                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       270055                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               621492                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             120854906                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              51874598                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2077168                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3039564                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                30259815                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                434333                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            97340803                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            205354                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              19719056                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13304976                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1415400                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 113322                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3328                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          30381                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         350453                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       269952                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               620405                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             120843569                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              51870507                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2075103                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        221278                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64090111                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11821235                       # Number of branches executed
-system.cpu.iew.exec_stores                   12215513                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.253301                       # Inst execution rate
-system.cpu.iew.wb_sent                      119911072                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85501046                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  47029089                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  87607932                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        222849                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64083354                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11822089                       # Number of branches executed
+system.cpu.iew.exec_stores                   12212847                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.253272                       # Inst execution rate
+system.cpu.iew.wb_sent                      119902421                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      85492712                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47017508                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  87566112                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.179203                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.536813                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.179182                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.536937                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        18687715                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1482323                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            537083                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    151253289                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.514049                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.489960                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        18682974                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1482307                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            536093                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    151287624                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.513928                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.489816                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    122784132     81.18%     81.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14644365      9.68%     90.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3917692      2.59%     93.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2132798      1.41%     94.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1620432      1.07%     95.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       975760      0.65%     96.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1598249      1.06%     97.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       715459      0.47%     98.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2864402      1.89%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    122817908     81.18%     81.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14643914      9.68%     90.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3918754      2.59%     93.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2134639      1.41%     94.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1621396      1.07%     95.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       973729      0.64%     96.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1595383      1.05%     97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       716191      0.47%     98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2865710      1.89%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    151253289                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             60460018                       # Number of instructions committed
-system.cpu.commit.committedOps               77751594                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    151287624                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60459415                       # Number of instructions committed
+system.cpu.commit.committedOps               77750883                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27386851                       # Number of memory references committed
-system.cpu.commit.loads                      15654790                       # Number of loads committed
-system.cpu.commit.membars                      403577                       # Number of memory barriers committed
-system.cpu.commit.branches                   10306380                       # Number of branches committed
+system.cpu.commit.refs                       27386618                       # Number of memory references committed
+system.cpu.commit.loads                      15654647                       # Number of loads committed
+system.cpu.commit.membars                      403571                       # Number of memory barriers committed
+system.cpu.commit.branches                   10306311                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  69191623                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               991253                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2864402                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  69190973                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               991245                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         50274217     64.66%     64.66% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           87935      0.11%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     64.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         2113      0.00%     64.78% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     64.78% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.78% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.78% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        15654647     20.13%     84.91% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       11731971     15.09%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total          77750883                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2865710                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    242979782                       # The number of ROB reads
-system.cpu.rob.rob_writes                   196005989                       # The number of ROB writes
-system.cpu.timesIdled                         1777234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       322825405                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4575137230                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    60309637                       # Number of Instructions Simulated
-system.cpu.committedOps                      77601213                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              60309637                       # Number of Instructions Simulated
-system.cpu.cpi                               7.911164                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.911164                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.126404                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.126404                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                548697999                       # number of integer regfile reads
-system.cpu.int_regfile_writes                87552825                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8408                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2932                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               268236665                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1173235                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                58867266                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2659080                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2659079                       # Transaction distribution
+system.cpu.rob.rob_reads                    243007370                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195993770                       # The number of ROB writes
+system.cpu.timesIdled                         1776375                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       322801694                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4575172520                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60309034                       # Number of Instructions Simulated
+system.cpu.committedOps                      77600502                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              60309034                       # Number of Instructions Simulated
+system.cpu.cpi                               7.911400                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.911400                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.126400                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.126400                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                548643015                       # number of integer regfile reads
+system.cpu.int_regfile_writes                87545924                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8332                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2902                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               268108891                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1173224                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                58876928                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2658786                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2658785                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq        763349                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp       763349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       607635                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2959                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2975                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       246069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       246069                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1961962                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5796085                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30498                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       129069                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7917614                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62744960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85505466                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214572                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148505990                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148505990                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       202724                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3129185667                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback       607456                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2966                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           12                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2978                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       246178                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       246178                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1963155                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5795994                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30467                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128822                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7918438                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62783488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85496634                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        41888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       215832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      148537842                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         148537842                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       196596                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3128822166                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1474638965                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1475557763                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2549207556                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2549946762                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      20255489                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19999491                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      75530794                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74967796                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            980897                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.570903                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            10462766                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            981409                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             10.660964                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        6958078250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.570903                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999162                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            981488                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.574363                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            10460581                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            982000                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             10.652323                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        6957426250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.574363                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999169                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999169                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          222                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          155                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          12504958                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         12504958                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     10462766                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        10462766                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      10462766                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         10462766                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     10462766                       # number of overall hits
-system.cpu.icache.overall_hits::total        10462766                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1060743                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1060743                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1060743                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1060743                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1060743                       # number of overall misses
-system.cpu.icache.overall_misses::total       1060743                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14268635888                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14268635888                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14268635888                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14268635888                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14268635888                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14268635888                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11523509                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11523509                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11523509                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11523509                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11523509                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11523509                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092050                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.092050                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.092050                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.092050                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.092050                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.092050                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13451.548479                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13451.548479                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         7798                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          12503981                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         12503981                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     10460581                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        10460581                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      10460581                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         10460581                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     10460581                       # number of overall hits
+system.cpu.icache.overall_hits::total        10460581                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1061360                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1061360                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1061360                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1061360                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1061360                       # number of overall misses
+system.cpu.icache.overall_misses::total       1061360                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14265779687                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14265779687                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14265779687                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14265779687                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14265779687                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14265779687                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     11521941                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     11521941                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     11521941                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     11521941                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     11521941                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     11521941                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092116                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.092116                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.092116                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.092116                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.092116                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.092116                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13441.037619                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13441.037619                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         7028                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               344                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               352                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    22.668605                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    19.965909                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79293                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        79293                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        79293                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        79293                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        79293                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        79293                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981450                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       981450                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       981450                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       981450                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       981450                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       981450                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11587546773                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11587546773                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11587546773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11587546773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11587546773                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11587546773                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      9345000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      9345000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      9345000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      9345000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085169                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.085169                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.085169                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79319                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        79319                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        79319                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        79319                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        79319                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        79319                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       982041                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       982041                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       982041                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       982041                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       982041                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       982041                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11583712225                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11583712225                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11583712225                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11583712225                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11583712225                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11583712225                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      8965500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      8965500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      8965500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      8965500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085232                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085232                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085232                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.085232                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085232                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.085232                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            64391                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        51374.630920                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1887139                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           129786                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            14.540390                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2490832751500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    31.305745                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000374                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8179.061871                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6245.594773                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563334                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000478                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            64387                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        51384.068329                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1888247                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           129781                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            14.549487                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2490875317000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    37.347999                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000373                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8175.789418                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6233.237161                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.563624                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000570                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124803                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.095300                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.783915                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65372                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3052                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6933                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54996                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000351                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997498                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18788998                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18788998                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53598                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10246                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       967912                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       386978                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1418734                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       607635                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       607635                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           46                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           46                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           13                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total           13                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       112878                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       112878                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        53598                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        10246                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       967912                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       499856                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1531612                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        53598                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        10246                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       967912                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       499856                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1531612                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           45                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124753                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.095112                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.784059                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           27                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65367                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           26                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          353                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3046                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6928                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54999                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000412                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997421                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18797143                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18797143                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53905                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10470                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       968525                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       386928                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1419828                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       607456                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       607456                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           45                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           45                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            9                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total            9                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       112956                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       112956                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        53905                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        10470                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       968525                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       499884                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1532784                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        53905                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        10470                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       968525                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       499884                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1532784                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           53                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12357                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        10744                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        23148                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2913                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2913                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        12346                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        10726                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        23127                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2921                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2921                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133191                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133191                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           45                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133222                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133222                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           53                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12357                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143935                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        156339                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           45                       # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst        12346                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       143948                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        156349                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           53                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12357                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143935                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       156339                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3974500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       412000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    905251250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    810262998                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1719900748                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       510978                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       510978                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9827066492                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9827066492                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3974500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       412000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    905251250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10637329490                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11546967240                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3974500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       412000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    905251250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10637329490                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11546967240                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53643                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10248                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       980269                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       397722                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1441882                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       607635                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       607635                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2959                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2959                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           16                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total           16                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       246069                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       246069                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        53643                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        10248                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       980269                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       643791                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1687951                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        53643                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        10248                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       980269                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       643791                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1687951                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000195                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012606                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.027014                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016054                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.984454                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.984454                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.187500                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.187500                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541275                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.541275                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000195                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012606                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.223574                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.092621                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000195                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012606                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.223574                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.092621                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       206000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73258.173505                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75415.394453                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74300.187835                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   175.412976                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   175.412976                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73781.760720                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73781.760720                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       206000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73258.173505                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73903.702991                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73858.520523                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       206000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73258.173505                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73903.702991                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73858.520523                       # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.inst        12346                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       143948                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       156349                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4489500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       430000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    894766750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    805694000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1705380250                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       465480                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       465480                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9848665479                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9848665479                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4489500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       430000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    894766750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10654359479                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11554045729                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4489500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       430000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    894766750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10654359479                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11554045729                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53958                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10472                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       980871                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       397654                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1442955                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       607456                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       607456                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2966                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2966                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           12                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total           12                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       246178                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       246178                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        53958                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        10472                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       980871                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       643832                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1689133                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        53958                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        10472                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       980871                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       643832                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1689133                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000982                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000191                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012587                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026973                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.016028                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.984828                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.984828                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541161                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.541161                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000982                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000191                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012587                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.223580                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.092562                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000982                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000191                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012587                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.223580                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.092562                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84707.547170                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       215000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72474.222420                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.979862                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73739.795477                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   159.356385                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   159.356385                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73926.719904                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73926.719904                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84707.547170                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       215000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72474.222420                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74015.335253                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73899.070215                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84707.547170                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       215000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72474.222420                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74015.335253                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73899.070215                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1116,109 +1139,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        59141                       # number of writebacks
-system.cpu.l2cache.writebacks::total            59141                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           65                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           65                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           65                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           80                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           45                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        59130                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59130                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           67                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           81                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           67                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           81                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           14                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           67                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           81                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           53                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12342                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10679                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        23068                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2913                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2913                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12332                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10659                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        23046                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2921                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2921                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133191                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133191                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           45                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133222                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133222                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           53                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12342                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143870                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       156259                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           45                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        12332                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143881                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       156268                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           53                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12342                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143870                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       156259                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       387500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    749197750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    673040498                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1426043248                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29132913                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29132913                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12332                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143881                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       156268                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3834000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       405500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    738779500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    668273250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1411292250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29213921                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29213921                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8170239508                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8170239508                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       387500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    749197750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8843280006                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9596282756                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       387500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    749197750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8843280006                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9596282756                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6814499                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942562250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166949376749                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17458567530                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17458567530                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6814499                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184401129780                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184407944279                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026850                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015999                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.984454                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984454                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.187500                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.187500                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541275                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541275                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223473                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.092573                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223473                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.092573                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63024.674408                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61819.110803                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8190370021                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8190370021                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3834000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       405500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    738779500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8858643271                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9601662271                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3834000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       405500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    738779500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8858643271                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9601662271                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6434999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17456853479                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17456853479                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6434999                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000982                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000191                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012572                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026805                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015971                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.984828                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984828                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541161                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541161                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000982                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000191                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012572                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223476                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.092514                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000982                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000191                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012572                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223476                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.092514                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       202750                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       202750                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       202750                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1228,168 +1251,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            643279                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993228                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            21514190                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            643791                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             33.417973                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          43094250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993228                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            643320                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.993245                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21508532                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            643832                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             33.407056                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          42989250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.993245                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         101537487                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        101537487                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13760648                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13760648                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7259865                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7259865                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       242998                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       242998                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247594                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247594                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21020513                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21020513                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21020513                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21020513                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       736359                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        736359                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2962417                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2962417                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13527                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13527                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           16                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           16                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3698776                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3698776                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3698776                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3698776                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9982812336                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9982812336                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 139744433579                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    185287000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    185287000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       245503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       245503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 149727245915                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 149727245915                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 149727245915                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 149727245915                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14497007                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14497007                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222282                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222282                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256525                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       256525                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247610                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247610                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24719289                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24719289                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24719289                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24719289                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050794                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.050794                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289800                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.289800                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052732                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052732                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000065                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000065                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.149631                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.149631                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.149631                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.149631                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40480.214513                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40480.214513                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        31777                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        23524                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2637                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             274                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.050436                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    85.854015                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses         101516564                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        101516564                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13756930                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13756930                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7258142                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7258142                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       242767                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       242767                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247595                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247595                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21015072                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21015072                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21015072                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21015072                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       735153                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        735153                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2964059                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2964059                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13525                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13525                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           12                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3699212                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3699212                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3699212                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3699212                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9975087313                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9975087313                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 139822431498                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    185099999                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    185099999                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       193503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       193503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 149797518811                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 149797518811                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 149797518811                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 149797518811                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14492083                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14492083                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10222201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256292                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       256292                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247607                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247607                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24714284                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24714284                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24714284                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24714284                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050728                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.050728                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289963                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.289963                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052772                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052772                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000048                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.149679                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.149679                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.149679                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.149679                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40494.440116                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40494.440116                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32269                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        24322                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2609                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             289                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.368340                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    84.159170                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607635                       # number of writebacks
-system.cpu.dcache.writebacks::total            607635                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       350728                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       350728                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2713476                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2713476                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1349                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1349                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3064204                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3064204                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3064204                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3064204                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385631                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       385631                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248941                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       248941                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12178                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12178                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           16                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           16                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       634572                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       634572                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       634572                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       634572                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4967633608                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4967633608                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11307381788                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11307381788                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145644250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145644250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       213497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       213497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16275015396                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16275015396                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16275015396                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  16275015396                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26867769000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26867769000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026601                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026601                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047473                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047473                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000065                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025671                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025671                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       607456                       # number of writebacks
+system.cpu.dcache.writebacks::total            607456                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       349595                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       349595                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2715007                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2715007                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1337                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1337                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3064602                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3064602                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3064602                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3064602                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385558                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       385558                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249052                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       249052                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12188                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12188                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           12                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       634610                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       634610                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       634610                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       634610                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4962813125                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4962813125                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11330760273                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11330760273                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145614251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145614251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       169497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       169497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16293573398                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  16293573398                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16293573398                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  16293573398                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26860394736                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26860394736                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026605                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026605                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024364                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024364                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047555                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047555                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000048                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025678                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025678                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025678                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025678                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1413,16 +1436,16 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1715151162848                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1712402234851                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    83035                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    83034                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 8e01cba8d..8f1b31c18 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,172 +1,168 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.403854                       # Number of seconds simulated
-sim_ticks                                2403853586500                       # Number of ticks simulated
-final_tick                               2403853586500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.403852                       # Number of seconds simulated
+sim_ticks                                2403852457500                       # Number of ticks simulated
+final_tick                               2403852457500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 171159                       # Simulator instruction rate (inst/s)
-host_op_rate                                   219830                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6819657603                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 469520                       # Number of bytes of host memory used
-host_seconds                                   352.49                       # Real time elapsed on the host
-sim_insts                                    60331708                       # Number of instructions simulated
-sim_ops                                      77487722                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 165592                       # Simulator instruction rate (inst/s)
+host_op_rate                                   212680                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6597855857                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 469068                       # Number of bytes of host memory used
+host_seconds                                   364.34                       # Real time elapsed on the host
+sim_insts                                    60331653                       # Number of instructions simulated
+sim_ops                                      77487544                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           512776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          7053720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           512456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          7048216                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            63616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           681152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker          640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           186368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          1342304                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            124659968                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       512776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        63616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       186368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          762760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3743360                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1298364                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data        159256                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data       1558196                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6759176                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst            63936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           680960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker          576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           186944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          1348288                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            124660704                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       512456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        63936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       186944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          763336                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3743808                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1298564                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data        159248                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data       1558004                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6759624                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      14352384                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             14224                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            110250                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             14219                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            110164                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               994                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10643                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           10                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              2912                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             20981                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14512403                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           58490                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           324591                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data            39814                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data           389549                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               812444                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47764586                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst               999                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             10640                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker            9                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              2921                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             21067                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14512407                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           58497                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           324641                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data            39812                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data           389501                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               812451                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47764609                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              213314                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             2934338                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              213181                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             2932050                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               26464                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              283358                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           266                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker            27                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               77529                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              558397                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51858386                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         213314                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          26464                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          77529                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             317307                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1557233                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             540118                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data              66250                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data             648208                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2811809                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1557233                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47764586                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               26597                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              283279                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           240                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               77769                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              560886                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51858717                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         213181                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          26597                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          77769                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             317547                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1557420                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             540201                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data              66247                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data             648128                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2811996                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1557420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47764609                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             213314                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3474456                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             213181                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3472251                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              26464                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             349609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          266                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              77529                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1206604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54670195                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      13446822                       # Number of read requests accepted
-system.physmem.writeReqs                       446449                       # Number of write requests accepted
-system.physmem.readBursts                    13446822                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     446449                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                860596480                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       128                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2823168                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 109564448                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2810956                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        2                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  402307                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           2362                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              835680                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              835344                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              835508                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              835965                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              837088                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              837779                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              837907                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              839147                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              840641                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              843268                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             843373                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             843869                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             845852                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             846016                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             844806                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             844577                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2668                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2526                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2530                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3005                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                3419                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                3167                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                2515                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2303                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                2186                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2396                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               2346                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2792                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               3710                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst              26597                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             349526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          240                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              77769                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1209014                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54670713                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      13446501                       # Number of read requests accepted
+system.physmem.writeReqs                       446412                       # Number of write requests accepted
+system.physmem.readBursts                    13446501                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     446412                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                860576000                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                        64                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   2816640                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 109567680                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                2811588                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        1                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  402376                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           2365                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              835689                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              835334                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              835514                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              835992                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              837083                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              837766                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              837910                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              839140                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              840643                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              843328                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             843395                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             843892                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             845429                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             846004                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             844795                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             844586                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2674                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2534                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2538                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                3024                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                3410                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                3131                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                2493                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2267                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                2164                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2378                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               2328                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2803                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               3718                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               3446                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               2600                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2503                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               2595                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2507                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2402817511500                       # Total gap between requests
+system.physmem.totGap                    2402816386500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       8                       # Read request sizes (log2)
-system.physmem.readPktSize::3                13411280                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                13410864                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   35534                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   35637                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                 429363                       # Write request sizes (log2)
+system.physmem.writePktSize::2                 429313                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  17086                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    867414                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    844196                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    838512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    839224                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    838671                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    838847                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2475363                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2475187                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3292199                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     20391                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    19694                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    19741                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    19565                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19474                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    19175                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    19145                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       22                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  17099                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    877452                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    853858                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    853065                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    937219                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    861122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    912169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2402802                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2330624                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3052022                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     86874                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    80661                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    76244                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    73288                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    16615                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    16291                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    16173                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -184,8 +180,8 @@ system.physmem.rdQLenPdf::30                        0                       # Wh
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                        99                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        96                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        95                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                        95                       # What write queue length does an incoming req see
@@ -196,48 +192,48 @@ system.physmem.wrQLenPdf::10                       93                       # Wh
 system.physmem.wrQLenPdf::11                       93                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                       92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     1625                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     1655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     1647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     1678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     1696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     1634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     1798                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     1677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     1653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     1860                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     1651                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     1605                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     1601                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     1586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      710                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      654                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      638                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      638                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      635                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      635                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      638                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2421                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     2461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     2402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     2681                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     2411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     2396                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     2417                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     2368                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     2356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     2413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     2343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     2346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     2344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     2313                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
@@ -246,79 +242,63 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       844644                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     1019.942660                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1014.395909                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev      58.300980                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           1516      0.18%      0.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         1237      0.15%      0.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          570      0.07%      0.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          375      0.04%      0.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          256      0.03%      0.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          198      0.02%      0.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          155      0.02%      0.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          158      0.02%      0.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       840179     99.47%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         844644                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          1621                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      8295.373226                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    315033.644502                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         1620     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07            1      0.06%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            1621                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          1621                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.212832                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       24.563019                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.121341                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1                   1      0.06%      0.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2                   2      0.12%      0.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3                   1      0.06%      0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4                   1      0.06%      0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5                   1      0.06%      0.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7                   1      0.06%      0.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9                   1      0.06%      0.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12                  2      0.12%      0.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15                  6      0.37%      0.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                488     30.10%     31.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 27      1.67%     32.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 60      3.70%     36.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                333     20.54%     57.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 10      0.62%     57.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  3      0.19%     57.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  2      0.12%     57.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  3      0.19%     58.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  2      0.12%     58.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  3      0.19%     58.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  5      0.31%     58.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  4      0.25%     58.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  5      0.31%     59.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  7      0.43%     59.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  3      0.19%     59.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  2      0.12%     60.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  8      0.49%     60.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  2      0.12%     60.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.06%     60.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                 50      3.08%     63.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  4      0.25%     64.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                167     10.30%     74.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                328     20.23%     94.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                 16      0.99%     95.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                 15      0.93%     96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                 23      1.42%     97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                 17      1.05%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                 13      0.80%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  2      0.12%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  2      0.12%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            1621                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   510864117000                       # Total ticks spent queuing
-system.physmem.totMemAccLat              601782495750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  67234100000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 23684278750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       37991.44                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1761.33                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples       866032                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      996.952353                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     964.296727                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     145.584191                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           8288      0.96%      0.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8846      1.02%      1.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6189      0.71%      2.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          800      0.09%      2.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          916      0.11%      2.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          687      0.08%      2.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7828      0.90%      3.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          243      0.03%      3.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       832235     96.10%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         866032                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2414                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      5570.207125                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    258157.496677                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         2413     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07            1      0.04%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            2414                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2414                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.231152                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.108696                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.979905                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   1      0.04%      0.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   2      0.08%      0.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   1      0.04%      0.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   1      0.04%      0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7                   2      0.08%      0.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9                   1      0.04%      0.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12                  1      0.04%      0.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14                  1      0.04%      0.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                  7      0.29%      0.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                485     20.09%     20.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 15      0.62%     21.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                872     36.12%     57.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                845     35.00%     92.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 52      2.15%     94.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 24      0.99%     95.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 26      1.08%     96.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 34      1.41%     98.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 13      0.54%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  5      0.21%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  6      0.25%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.04%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  6      0.25%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  7      0.29%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  2      0.08%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  4      0.17%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2414                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   345783645500                       # Total ticks spent queuing
+system.physmem.totMemAccLat              597905520500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  67232500000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25715.51                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44752.77                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         358.01                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44465.51                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         358.00                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.17                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       45.58                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.17                       # Average system write bandwidth in MiByte/s
@@ -326,15 +306,19 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           2.81                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.80                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         8.42                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         5.41                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   12595156                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     38053                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  86.21                       # Row buffer hit rate for writes
-system.physmem.avgGap                       172948.29                       # Average gap between requests
-system.physmem.pageHitRate                      93.64                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               2.74                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         7.51                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         4.43                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   12586631                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     37847                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.61                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.95                       # Row buffer hit rate for writes
+system.physmem.avgGap                       172952.67                       # Average gap between requests
+system.physmem.pageHitRate                      93.58                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2167477603250                       # Time in different power states
+system.physmem.memoryStateTime::REF       80269800000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      156101819250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -347,341 +331,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst            8
 system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     55667457                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            13781916                       # Transaction distribution
-system.membus.trans_dist::ReadResp           13781916                       # Transaction distribution
-system.membus.trans_dist::WriteReq             432200                       # Transaction distribution
-system.membus.trans_dist::WriteResp            432200                       # Transaction distribution
-system.membus.trans_dist::Writeback             17086                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2361                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            2362                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             27973                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            27973                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       731598                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          210                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       951620                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1683428                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     26822560                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     26822560                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               28505988                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       735468                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          420                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      5085164                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total      5821052                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    107290240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total    107290240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           113111292                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              133816415                       # Total data (bytes)
+system.membus.throughput                     55667977                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            13781620                       # Transaction distribution
+system.membus.trans_dist::ReadResp           13781620                       # Transaction distribution
+system.membus.trans_dist::WriteReq             432153                       # Transaction distribution
+system.membus.trans_dist::WriteResp            432153                       # Transaction distribution
+system.membus.trans_dist::Writeback             17099                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2365                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            2365                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             28041                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            28041                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       731786                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          214                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       951729                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1683729                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     26821728                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total     26821728                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               28505457                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       735662                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          428                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      5092356                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total      5828446                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    107286912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total    107286912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           113115358                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              133817603                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           416850000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           416874000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              198000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              199500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         14576843000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         14576510500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1595419615                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1596663785                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        33523642000                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        33229062000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    63235                       # number of replacements
-system.l2c.tags.tagsinuse                50381.174231                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1749008                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   128627                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.597518                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             2375559570500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36838.397677                       # Average occupied blocks per requestor
+system.l2c.tags.replacements                    63248                       # number of replacements
+system.l2c.tags.tagsinuse                50398.234461                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1749256                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   128641                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    13.597966                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle             2375562300000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   36845.662788                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000018                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000124                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5238.516596                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3833.196793                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.993316                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      493.229672                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      688.317801                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker     8.879272                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker     0.004789                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1684.639749                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     1594.998425                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.562109                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst     5231.089770                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3832.891832                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.993317                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      496.025776                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      690.296020                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker     8.797358                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1694.464698                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     1598.012760                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.562220                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.079933                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.058490                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.079820                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.058485                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.007526                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.010503                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000135                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.025706                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.024338                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.768756                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65386                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu1.inst       0.007569                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.010533                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000134                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.025855                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.024384                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.769016                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65389                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2640                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6490                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55882                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.997711                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 17681539                       # Number of tag accesses
-system.l2c.tags.data_accesses                17681539                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         8692                       # number of ReadReq hits
+system.l2c.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2635                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6488                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55889                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997757                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 17683113                       # Number of tag accesses
+system.l2c.tags.data_accesses                17683113                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         8690                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         3137                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             468000                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             177035                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         2622                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1183                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             129681                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              64527                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        18896                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker         4217                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             281169                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             131701                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1290860                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          597704                       # number of Writeback hits
-system.l2c.Writeback_hits::total               597704                       # number of Writeback hits
+system.l2c.ReadReq_hits::cpu0.inst             468117                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             177120                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         2623                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1184                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             129717                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              64377                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        18993                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker         4195                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             281260                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             131724                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1291137                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          597632                       # number of Writeback hits
+system.l2c.Writeback_hits::total               597632                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              15                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  33                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data             3                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            61997                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            18431                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            33199                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               113627                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          8692                       # number of demand (read+write) hits
+system.l2c.UpgradeReq_hits::cpu2.data              12                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  30                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu2.data             4                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 4                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            62001                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            18409                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            33201                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               113611                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          8690                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.itb.walker          3137                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              468000                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              239032                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          2622                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1183                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              129681                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               82958                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         18896                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker          4217                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              281169                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              164900                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1404487                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         8692                       # number of overall hits
+system.l2c.demand_hits::cpu0.inst              468117                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              239121                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          2623                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          1184                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              129717                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               82786                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker         18993                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker          4195                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              281260                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              164925                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1404748                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         8690                       # number of overall hits
 system.l2c.overall_hits::cpu0.itb.walker         3137                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             468000                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             239032                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         2622                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1183                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             129681                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              82958                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        18896                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker         4217                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             281169                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             164900                       # number of overall hits
-system.l2c.overall_hits::total                1404487                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             468117                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             239121                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         2623                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         1184                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             129717                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              82786                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker        18993                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker         4195                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             281260                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             164925                       # number of overall hits
+system.l2c.overall_hits::total                1404748                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             7598                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6467                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             7593                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6464                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              994                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             1116                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           10                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             2913                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data             2538                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                21641                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1418                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           468                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data          1020                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2906                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu2.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         104538                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           9799                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          19047                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133384                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu1.inst              999                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             1119                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker            9                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst             2922                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data             2560                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                21670                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1416                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           469                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data          1019                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2904                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         104452                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           9794                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          19124                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133370                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7598                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            111005                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              7593                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            110916                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               994                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             10915                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker           10                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              2913                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             21585                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                155025                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst               999                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             10913                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker            9                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              2922                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             21684                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                155040                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7598                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           111005                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             7593                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           110916                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              994                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            10915                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker           10                       # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             2913                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            21585                       # number of overall misses
-system.l2c.overall_misses::total               155025                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst              999                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            10913                       # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker            9                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             2922                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            21684                       # number of overall misses
+system.l2c.overall_misses::total               155040                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        74500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     70385750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     86555000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker       790250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker        75000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst    219321000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data    195686250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      572887750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst     70879750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     85596750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker       673000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    220789250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data    196778249                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total      574791499                       # number of ReadReq miss cycles
 system.l2c.UpgradeReq_miss_latency::cpu1.data        93996                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data       139994                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       233990                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    724629978                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   1410364149                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   2134994127                       # number of ReadExReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data       139494                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       233490                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    710505727                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   1408534646                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2119040373                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu1.dtb.walker        74500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     70385750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    811184978                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker       790250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker        75000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    219321000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   1606050399                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      2707881877                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     70879750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    796102477                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker       673000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    220789250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   1605312895                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      2693831872                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker        74500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     70385750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    811184978                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker       790250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker        75000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    219321000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   1606050399                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     2707881877                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         8693                       # number of ReadReq accesses(hits+misses)
+system.l2c.overall_miss_latency::cpu1.inst     70879750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    796102477                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker       673000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    220789250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   1605312895                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     2693831872                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         8691                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.itb.walker         3139                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         475598                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         183502                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         2623                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1183                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         130675                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          65643                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker        18906                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker         4218                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst         284082                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data         134239                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1312501                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       597704                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           597704                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1432                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          472                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data         1035                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2939                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         475710                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         183584                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         2624                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1184                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         130716                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          65496                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker        19002                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker         4195                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst         284182                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data         134284                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1312807                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       597632                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           597632                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1430                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          473                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data         1031                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2934                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu2.data            4                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       166535                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        28230                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        52246                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247011                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         8693                       # number of demand (read+write) accesses
+system.l2c.ReadExReq_accesses::cpu0.data       166453                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        28203                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        52325                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           246981                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         8691                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.itb.walker         3139                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          475598                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          475710                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.data          350037                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         2623                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1183                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          130675                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           93873                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker        18906                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker         4218                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          284082                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          186485                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1559512                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         8693                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         2624                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1184                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          130716                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           93699                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        19002                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker         4195                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          284182                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          186609                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1559788                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         8691                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.itb.walker         3139                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         475598                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         475710                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.data         350037                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         2623                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1183                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         130675                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          93873                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker        18906                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker         4218                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         284082                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         186485                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1559512                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         2624                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1184                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         130716                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          93699                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker        19002                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker         4195                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         284182                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         186609                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1559788                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000115                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000637                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.015976                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.035242                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.015961                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.035210                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.007607                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.017001                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000529                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000237                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.010254                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.018907                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016488                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990223                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991525                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.985507                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.988772                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.250000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.627724                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.347113                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.364564                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.539992                       # miss rate for ReadExReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.007643                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.017085                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000474                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.010282                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.019064                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016507                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990210                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991543                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.988361                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.989775                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.627516                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.347268                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.365485                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.540001                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000115                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.000637                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015976                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.317124                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.015961                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.316869                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.007607                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.116274                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000529                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.000237                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.010254                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.115747                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.099406                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.007643                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.116469                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000474                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.010282                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.116200                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.099398                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000115                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.000637                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015976                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.317124                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.015961                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.316869                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.007607                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.116274                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000529                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.000237                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.010254                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.115747                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.099406                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.007643                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.116469                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000474                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.010282                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.116200                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.099398                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70810.613682                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77558.243728                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker        79025                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        75000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75290.422245                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 77102.541371                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 26472.332609                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   200.846154                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   137.249020                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total    80.519615                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73949.380345                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74046.524335                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 16006.373531                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70950.700701                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76493.967828                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 74777.777778                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75561.002738                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 76866.503516                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 26524.757683                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   200.417910                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   136.893032                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total    80.402893                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72544.999694                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73652.721502                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 15888.433478                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 70810.613682                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 74318.367201                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker        79025                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker        75000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 75290.422245                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 74405.855872                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 17467.388337                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 70950.700701                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 72949.920004                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 74777.777778                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 75561.002738                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 74032.138674                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 17375.076574                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 70810.613682                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 74318.367201                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker        79025                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker        75000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 75290.422245                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 74405.855872                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 17467.388337                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 70950.700701                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 72949.920004                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 74777.777778                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 75561.002738                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 74032.138674                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 17375.076574                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -690,154 +655,134 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               58490                       # number of writebacks
-system.l2c.writebacks::total                    58490                       # number of writebacks
+system.l2c.writebacks::writebacks               58497                       # number of writebacks
+system.l2c.writebacks::total                    58497                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu2.inst             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.data            11                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                12                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.data            13                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                14                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data             11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 12                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data             13                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 14                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data            11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                12                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data            13                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                14                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst          994                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         1116                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           10                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         2912                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data         2527                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            7561                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          468                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data         1020                       # number of UpgradeReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst          999                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         1119                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker            9                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         2921                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data         2547                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            7596                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          469                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data         1019                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::total         1488                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         9799                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        19047                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         28846                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         9794                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        19124                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         28918                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          994                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        10915                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           10                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         2912                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        21574                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            36407                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst          999                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        10913                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker            9                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         2921                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        21671                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            36514                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          994                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        10915                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           10                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         2912                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        21574                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           36407                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst          999                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        10913                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker            9                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         2921                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        21671                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           36514                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     57779750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     72669000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker       666250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker        62500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    182779750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data    163556500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    477576250                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4680468                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     10201020                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     58206250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     71681250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker       562500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    184124500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    164011999                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    478648999                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4690469                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     10191019                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::total     14881488                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    600655022                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1172932351                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1773587373                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    586577273                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1169906854                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1756484127                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     57779750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    673324022                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker       666250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    182779750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   1336488851                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   2251163623                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     58206250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    658258523                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker       562500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    184124500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   1333918853                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   2235133126                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     57779750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    673324022                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       666250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        62500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    182779750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   1336488851                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   2251163623                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25059808500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  26177769250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  51237577750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    932383523                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   8518108000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   9450491523                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  25992192023                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  34695877250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  60688069273                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     58206250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    658258523                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       562500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    184124500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   1333918853                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   2235133126                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25072597000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  26177785500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  51250382500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    933416100                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   8516272500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   9449688600                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  26006013100                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  34694058000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  60700071100                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.007607                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017001                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000529                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000237                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.010251                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.018825                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.005761                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991525                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.985507                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.506295                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.347113                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.364564                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.116780                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.007643                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017085                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000474                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.010279                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.018967                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.005786                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991543                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.988361                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.507157                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.347268                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.365485                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.117086                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007607                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.116274                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000529                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000237                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010251                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.115688                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.023345                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007643                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.116469                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000474                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010279                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.116131                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.023410                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007607                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.116274                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000529                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000237                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010251                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.115688                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.023345                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007643                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.116469                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000474                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010279                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.116131                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.023410                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58128.521127                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65115.591398                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker        66625                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62767.771291                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64723.585279                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 63163.106732                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58264.514515                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64058.310992                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63034.748374                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64394.188850                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 63013.296340                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61297.583631                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61580.949808                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 61484.690182                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59891.492036                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61174.798891                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60740.166229                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58128.521127                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61687.954375                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker        66625                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62767.771291                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61949.052146                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 61833.263466                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58264.514515                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60318.750389                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63034.748374                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61553.174888                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61213.045024                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58128.521127                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61687.954375                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker        66625                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62767.771291                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61949.052146                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 61833.263466                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58264.514515                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60318.750389                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63034.748374                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61553.174888                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61213.045024                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -854,52 +799,52 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    58805312                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            1019677                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           1019676                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            432200                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           432200                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           265274                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1507                       # Transaction distribution
+system.toL2Bus.throughput                    58808825                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            1019736                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           1019735                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            432153                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           432153                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           265208                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1504                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1511                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            80476                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           80476                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       830192                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2419562                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        15560                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        52654                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               3317968                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     26544384                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     37373820                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        21604                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        86116                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total           64025924                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             141258487                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          100872                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         2176910263                       # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::UpgradeResp           1508                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            80528                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           80528                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       830481                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2419466                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        15414                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        52803                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               3318164                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     26553408                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     37366366                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        21516                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        86504                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total           64027794                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             141267007                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          100732                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         2176624753                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1870334166                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1870991697                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1845880168                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1845922726                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          10179455                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          10050964                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          31260469                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          31304739                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      48758934                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             13774305                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            13774305                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                2774                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               2774                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        11404                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3022                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                      48758959                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             13773981                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            13773981                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                2776                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               2776                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        11410                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3028                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           18                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          252                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          254                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       716614                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       716788                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -915,18 +860,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       731598                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     26822560                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     26822560                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                27554158                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        15368                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6044                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       731786                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     26821728                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total     26821728                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                27553514                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        15374                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           36                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          504                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          508                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       712940                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       713112                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -942,18 +887,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total       735468                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    107290240                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total    107290240                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            108025708                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               117209339                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              7964000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total       735662                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    107286912                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total    107286912                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total            108022574                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               117209343                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              7968000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              1511000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              1514000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               126000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               127000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -961,7 +906,7 @@ system.iobus.reqLayer5.occupancy                 8000                       # La
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy            358810000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy            358898000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
@@ -993,11 +938,11 @@ system.iobus.reqLayer22.occupancy                8000                       # La
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy         13411280000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy         13410864000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           728824000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           729010000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         33525822000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         33767373000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -1022,25 +967,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7997782                       # DTB read hits
-system.cpu0.dtb.read_misses                      6203                       # DTB read misses
-system.cpu0.dtb.write_hits                    6595987                       # DTB write hits
-system.cpu0.dtb.write_misses                     1983                       # DTB write misses
+system.cpu0.dtb.read_hits                     7995700                       # DTB read hits
+system.cpu0.dtb.read_misses                      6195                       # DTB read misses
+system.cpu0.dtb.write_hits                    6594454                       # DTB write hits
+system.cpu0.dtb.write_misses                     1984                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         556                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                676                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid                675                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    5673                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    5669                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   123                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   121                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      209                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 8003985                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6597970                       # DTB write accesses
+system.cpu0.dtb.read_accesses                 8001895                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6596438                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14593769                       # DTB hits
-system.cpu0.dtb.misses                           8186                       # DTB misses
-system.cpu0.dtb.accesses                     14601955                       # DTB accesses
+system.cpu0.dtb.hits                         14590154                       # DTB hits
+system.cpu0.dtb.misses                           8179                       # DTB misses
+system.cpu0.dtb.accesses                     14598333                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1062,433 +1007,468 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    32336935                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3451                       # ITB inst misses
+system.cpu0.itb.inst_hits                    32327896                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3449                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         556                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                676                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid                675                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2628                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2626                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                32340386                       # ITB inst accesses
-system.cpu0.itb.hits                         32336935                       # DTB hits
-system.cpu0.itb.misses                           3451                       # DTB misses
-system.cpu0.itb.accesses                     32340386                       # DTB accesses
-system.cpu0.numCycles                       113724377                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                32331345                       # ITB inst accesses
+system.cpu0.itb.hits                         32327896                       # DTB hits
+system.cpu0.itb.misses                           3449                       # DTB misses
+system.cpu0.itb.accesses                     32331345                       # DTB accesses
+system.cpu0.numCycles                       113683212                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31861763                       # Number of instructions committed
-system.cpu0.committedOps                     42032224                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             37415212                       # Number of integer alu accesses
+system.cpu0.committedInsts                   31852389                       # Number of instructions committed
+system.cpu0.committedOps                     42022034                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             37405417                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  4937                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1199152                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4246542                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    37415212                       # number of integer instructions
+system.cpu0.num_func_calls                    1199046                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4246321                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    37405417                       # number of integer instructions
 system.cpu0.num_fp_insts                         4937                       # number of float instructions
-system.cpu0.num_int_register_reads          193939915                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          39523913                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          193890675                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          39514617                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3572                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1366                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     15261638                       # number of memory refs
-system.cpu0.num_load_insts                    8366552                       # Number of load instructions
-system.cpu0.num_store_insts                   6895086                       # Number of store instructions
-system.cpu0.num_idle_cycles              110931893.434026                       # Number of idle cycles
-system.cpu0.num_busy_cycles              2792483.565974                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.024555                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.975445                       # Percentage of idle cycles
-system.cpu0.Branches                          5615139                       # Number of branches fetched
+system.cpu0.num_mem_refs                     15257672                       # number of memory refs
+system.cpu0.num_load_insts                    8364380                       # Number of load instructions
+system.cpu0.num_store_insts                   6893292                       # Number of store instructions
+system.cpu0.num_idle_cycles              110986808.765580                       # Number of idle cycles
+system.cpu0.num_busy_cycles              2696403.234420                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.023719                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.976281                       # Percentage of idle cycles
+system.cpu0.Branches                          5614656                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                14792      0.04%      0.04% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 26773719     63.60%     63.63% # Class of executed instruction
+system.cpu0.op_class::IntMult                   49650      0.12%     63.75% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     63.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              1431      0.00%     63.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     63.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     63.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     63.76% # Class of executed instruction
+system.cpu0.op_class::MemRead                 8364380     19.87%     83.63% # Class of executed instruction
+system.cpu0.op_class::MemWrite                6893292     16.37%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                  42097264                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   82892                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           891249                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.602369                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           43668526                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           891761                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            48.968867                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       8187850250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   494.923201                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     7.626935                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst     9.052233                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.966647                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.014896                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.017680                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999223                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           891512                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.602542                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           43658005                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           892024                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            48.942635                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       8184230000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   494.829489                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst     7.587272                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst     9.185782                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.966464                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.014819                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.017941                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999224                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          166                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         45475856                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        45475856                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     31863243                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      8064619                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      3740664                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       43668526                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     31863243                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      8064619                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      3740664                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        43668526                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     31863243                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      8064619                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      3740664                       # number of overall hits
-system.cpu0.icache.overall_hits::total       43668526                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       476340                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       130939                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       308276                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       915555                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       476340                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       130939                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       308276                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        915555                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       476340                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       130939                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       308276                       # number of overall misses
-system.cpu0.icache.overall_misses::total       915555                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1766616750                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4157487812                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   5924104562                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1766616750                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4157487812                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   5924104562                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1766616750                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4157487812                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   5924104562                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     32339583                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      8195558                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      4048940                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     44584081                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     32339583                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      8195558                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      4048940                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     44584081                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     32339583                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      8195558                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      4048940                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     44584081                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014729                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015977                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.076137                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.020535                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014729                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015977                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.076137                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.020535                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014729                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015977                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.076137                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.020535                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13491.906537                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13486.251969                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6470.506482                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13491.906537                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13486.251969                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6470.506482                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13491.906537                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13486.251969                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6470.506482                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4144                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         45465874                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        45465874                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     31854091                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      8059411                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      3744503                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       43658005                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     31854091                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      8059411                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      3744503                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        43658005                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     31854091                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      8059411                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      3744503                       # number of overall hits
+system.cpu0.icache.overall_hits::total       43658005                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       476451                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       130983                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       308401                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       915835                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       476451                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       130983                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       308401                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        915835                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       476451                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       130983                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       308401                       # number of overall misses
+system.cpu0.icache.overall_misses::total       915835                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1767573750                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4161599099                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   5929172849                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1767573750                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4161599099                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   5929172849                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1767573750                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4161599099                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   5929172849                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     32330542                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      8190394                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      4052904                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     44573840                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     32330542                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      8190394                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      4052904                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     44573840                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     32330542                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      8190394                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      4052904                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     44573840                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014737                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015992                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.076094                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.020546                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014737                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015992                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.076094                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.020546                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014737                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015992                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.076094                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.020546                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13494.680607                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13494.116747                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6474.062303                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13494.680607                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13494.116747                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6474.062303                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13494.680607                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13494.116747                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6474.062303                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         2820                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              217                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              202                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.096774                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.960396                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23779                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        23779                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        23779                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        23779                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        23779                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        23779                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       130939                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       284497                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       415436                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       130939                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       284497                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       415436                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       130939                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       284497                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       415436                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1504362250                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3384633315                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   4888995565                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1504362250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3384633315                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   4888995565                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1504362250                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3384633315                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   4888995565                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015977                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.070265                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009318                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015977                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.070265                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009318                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015977                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.070265                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009318                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11489.031152                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11896.903359                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11768.348350                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11489.031152                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11896.903359                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11768.348350                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11489.031152                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11896.903359                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11768.348350                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23800                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        23800                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        23800                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        23800                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        23800                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        23800                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       130983                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       284601                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       415584                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       130983                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       284601                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       415584                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       130983                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       284601                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       415584                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1505220250                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3386666286                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   4891886536                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1505220250                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3386666286                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   4891886536                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1505220250                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3386666286                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   4891886536                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015992                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.070222                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009323                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015992                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.070222                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009323                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015992                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.070222                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009323                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11491.722208                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11899.699179                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11771.113748                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11491.722208                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11899.699179                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11771.113748                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11491.722208                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11899.699179                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11771.113748                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           629883                       # number of replacements
+system.cpu0.dcache.tags.replacements           629833                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997118                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           23225674                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           630395                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            36.843049                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           23224733                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           630345                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            36.844479                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         21768000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.048952                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     8.104316                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.843850                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970799                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015829                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013367                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.042290                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     8.061376                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.893452                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970786                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015745                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013464                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          300                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         98832175                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        98832175                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6866825                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1820637                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4638025                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13325487                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5964516                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1315550                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2131525                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       9411591                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       131816                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        33033                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        73362                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       238211                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       138281                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        34792                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        74313                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247386                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12831341                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      3136187                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6769550                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        22737078                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12831341                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      3136187                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6769550                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       22737078                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       177037                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        63884                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       270059                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       510980                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       167967                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        28702                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       608180                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       804849                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6465                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1759                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3713                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        11937                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses         98835293                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        98835293                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6864775                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1819119                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      4641948                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13325842                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5963046                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      1314313                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      2132881                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       9410240                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       131790                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        33007                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        73476                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       238273                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       138256                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        34751                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        74378                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247385                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     12827821                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      3133432                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      6774829                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        22736082                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     12827821                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      3133432                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      6774829                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       22736082                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       177118                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        63752                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       270474                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       511344                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       167883                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        28676                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       609650                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       806209                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6466                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1744                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3730                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11940                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu2.data            4                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       345004                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data        92586                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       878239                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1315829                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       345004                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data        92586                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data       878239                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1315829                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    910211000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3890836807                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   4801047807                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1008525490                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22983455032                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  23991980522                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     23124000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     49531749                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     72655749                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        64501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total        64501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   1918736490                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  26874291839                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  28793028329                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   1918736490                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  26874291839                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  28793028329                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7043862                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1884521                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4908084                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13836467                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      6132483                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1344252                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2739705                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10216440                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       138281                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        34792                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        77075                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       250148                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       138281                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        34792                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        74317                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247390                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13176345                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      3228773                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7647789                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     24052907                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13176345                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      3228773                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7647789                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     24052907                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025134                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033899                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.055023                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.036930                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027390                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_misses::cpu0.data       345001                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data        92428                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data       880124                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1317553                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       345001                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data        92428                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data       880124                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1317553                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    907525000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3898427279                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   4805952279                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data    994225242                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22938892543                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  23933117785                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     22894750                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     49919498                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     72814248                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        52000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total        52000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   1901750242                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  26837319822                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  28739070064                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   1901750242                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  26837319822                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  28739070064                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7041893                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1882871                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4912422                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13837186                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      6130929                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1342989                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2742531                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10216449                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       138256                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        34751                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        77206                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       250213                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       138256                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        34751                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        74382                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247389                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13172822                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      3225860                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7654953                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     24053635                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13172822                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      3225860                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7654953                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     24053635                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025152                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033859                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.055059                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.036954                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027383                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.021352                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.221987                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.078780                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046753                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.050558                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.048174                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047720                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.222295                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.078913                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046768                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.050186                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.048312                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047719                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000054                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000016                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026184                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028675                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.114836                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.054706                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026184                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028675                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.114836                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.054706                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14247.871141                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14407.358418                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  9395.764623                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35137.812348                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37790.547259                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 29809.294069                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13146.105742                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13340.088608                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6086.600402                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16125.250000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16125.250000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20723.829629                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30600.203178                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 21882.044193                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20723.829629                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30600.203178                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 21882.044193                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         7912                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         2132                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs              872                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             43                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.073394                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    49.581395                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026190                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028652                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.114974                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.054776                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026190                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028652                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.114974                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.054776                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14235.239679                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14413.316175                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  9398.667588                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34670.987655                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37626.330752                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29685.996789                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.723624                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13383.243432                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6098.345729                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20575.477583                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30492.657651                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 21812.458447                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20575.477583                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30492.657651                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 21812.458447                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         8069                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         3116                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs              905                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             48                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.916022                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    64.916667                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       597704                       # number of writebacks
-system.cpu0.dcache.writebacks::total           597704                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       139099                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       139099                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       554931                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       554931                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          402                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total          402                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       694030                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       694030                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       694030                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       694030                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        63884                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       130960                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       194844                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        28702                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        53249                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total        81951                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1759                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3311                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5070                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       597632                       # number of writebacks
+system.cpu0.dcache.writebacks::total           597632                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       139480                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       139480                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       556328                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       556328                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          406                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          406                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       695808                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       695808                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       695808                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       695808                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        63752                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       130994                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       194746                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        28676                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        53322                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total        81998                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1744                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3324                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5068                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            4                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        92586                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       184209                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       276795                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data        92586                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       184209                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       276795                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    782254000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1693207098                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2475461098                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data    948597510                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   1850547743                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2799145253                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     19606000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     38066251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57672251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        56499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        56499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1730851510                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3543754841                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   5274606351                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1730851510                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3543754841                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   5274606351                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27378129500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  28579482250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  55957611750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1439295977                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  13341687506                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  14780983483                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28817425477                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  41921169756                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  70738595233                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033899                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.026683                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.014082                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        92428                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       184316                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       276744                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data        92428                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       184316                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       276744                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    779830000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1694363864                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2474193864                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data    934250758                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   1848694495                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2782945253                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     19406250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     38393502                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57799752                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        44000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        44000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1714080758                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3543058359                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   5257139117                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1714080758                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3543058359                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   5257139117                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27392049000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  28579464500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  55971513500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1440396400                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  13339396963                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  14779793363                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28832445400                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  41918861463                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  70751306863                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033859                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.026666                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.014074                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.021352                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.019436                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008021                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050558                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.042958                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.020268                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.019443                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008026                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050186                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.043054                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.020255                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000054                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028675                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.024087                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.011508                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028675                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024087                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.011508                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12244.912654                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12929.192868                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.836166                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33049.874922                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34752.722924                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34156.328208                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11146.105742                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.904561                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.197436                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18694.527358                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19237.685678                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19056.003002                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18694.527358                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19237.685678                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19056.003002                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028652                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.024078                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.011505                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028652                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024078                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.011505                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12232.243694                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12934.667725                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.722377                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32579.535430                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34670.389239                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33939.184529                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.436927                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11550.391697                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11404.844515                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18545.037846                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19222.738986                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.397815                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18545.037846                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19222.738986                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.397815                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1522,25 +1502,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     2097642                       # DTB read hits
+system.cpu1.dtb.read_hits                     2096038                       # DTB read hits
 system.cpu1.dtb.read_misses                      2089                       # DTB read misses
-system.cpu1.dtb.write_hits                    1419704                       # DTB write hits
-system.cpu1.dtb.write_misses                      373                       # DTB write misses
+system.cpu1.dtb.write_hits                    1418402                       # DTB write hits
+system.cpu1.dtb.write_misses                      376                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         554                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                221                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1767                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1770                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                    39                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                    37                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                       79                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 2099731                       # DTB read accesses
-system.cpu1.dtb.write_accesses                1420077                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 2098127                       # DTB read accesses
+system.cpu1.dtb.write_accesses                1418778                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          3517346                       # DTB hits
-system.cpu1.dtb.misses                           2462                       # DTB misses
-system.cpu1.dtb.accesses                      3519808                       # DTB accesses
+system.cpu1.dtb.hits                          3514440                       # DTB hits
+system.cpu1.dtb.misses                           2465                       # DTB misses
+system.cpu1.dtb.accesses                      3516905                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1562,8 +1542,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     8195558                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1195                       # ITB inst misses
+system.cpu1.itb.inst_hits                     8190394                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1200                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1572,51 +1552,86 @@ system.cpu1.itb.flush_tlb                         554                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                221                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     946                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     949                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 8196753                       # ITB inst accesses
-system.cpu1.itb.hits                          8195558                       # DTB hits
-system.cpu1.itb.misses                           1195                       # DTB misses
-system.cpu1.itb.accesses                      8196753                       # DTB accesses
-system.cpu1.numCycles                       584703165                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 8191594                       # ITB inst accesses
+system.cpu1.itb.hits                          8190394                       # DTB hits
+system.cpu1.itb.misses                           1200                       # DTB misses
+system.cpu1.itb.accesses                      8191594                       # DTB accesses
+system.cpu1.numCycles                       584767176                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7984738                       # Number of instructions committed
-system.cpu1.committedOps                     10135701                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              9107037                       # Number of integer alu accesses
+system.cpu1.committedInsts                    7979697                       # Number of instructions committed
+system.cpu1.committedOps                     10128513                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              9101420                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  2019                       # Number of float alu accesses
-system.cpu1.num_func_calls                     304651                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1115193                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     9107037                       # number of integer instructions
+system.cpu1.num_func_calls                     304592                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1114093                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     9101420                       # number of integer instructions
 system.cpu1.num_fp_insts                         2019                       # number of float instructions
-system.cpu1.num_int_register_reads           53092313                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           9899825                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           53054873                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           9892627                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1441                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                580                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      3684662                       # number of memory refs
-system.cpu1.num_load_insts                    2190856                       # Number of load instructions
-system.cpu1.num_store_insts                   1493806                       # Number of store instructions
-system.cpu1.num_idle_cycles              548865377.428164                       # Number of idle cycles
-system.cpu1.num_busy_cycles              35837787.571836                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.061292                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.938708                       # Percentage of idle cycles
-system.cpu1.Branches                          1448177                       # Number of branches fetched
+system.cpu1.num_mem_refs                      3681879                       # number of memory refs
+system.cpu1.num_load_insts                    2189240                       # Number of load instructions
+system.cpu1.num_store_insts                   1492639                       # Number of store instructions
+system.cpu1.num_idle_cycles              548440957.661697                       # Number of idle cycles
+system.cpu1.num_busy_cycles              36326218.338303                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.062121                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.937879                       # Percentage of idle cycles
+system.cpu1.Branches                          1446987                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                 5386      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  6616988     64.14%     64.19% # Class of executed instruction
+system.cpu1.op_class::IntMult                   11601      0.11%     64.31% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc               298      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.31% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2189240     21.22%     85.53% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1492639     14.47%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                  10316152                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups                4782343                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          3901882                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           223184                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             3184465                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                2528356                       # Number of BTB hits
+system.cpu2.branchPred.lookups                4788852                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          3906949                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           223643                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             3181584                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                2530711                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            79.396571                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 413120                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             21664                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            79.542486                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 413887                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             21714                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1640,25 +1655,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    10925413                       # DTB read hits
-system.cpu2.dtb.read_misses                     23157                       # DTB read misses
-system.cpu2.dtb.write_hits                    3347832                       # DTB write hits
-system.cpu2.dtb.write_misses                     6500                       # DTB write misses
+system.cpu2.dtb.read_hits                    10930564                       # DTB read hits
+system.cpu2.dtb.read_misses                     23215                       # DTB read misses
+system.cpu2.dtb.write_hits                    3350483                       # DTB write hits
+system.cpu2.dtb.write_misses                     6482                       # DTB write misses
 system.cpu2.dtb.flush_tlb                         552                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid                542                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_mva_asid                543                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    2330                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      739                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.flush_entries                    2337                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      733                       # Number of TLB faults due to alignment restrictions
 system.cpu2.dtb.prefetch_faults                   153                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      476                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                10948570                       # DTB read accesses
-system.cpu2.dtb.write_accesses                3354332                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      461                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                10953779                       # DTB read accesses
+system.cpu2.dtb.write_accesses                3356965                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         14273245                       # DTB hits
-system.cpu2.dtb.misses                          29657                       # DTB misses
-system.cpu2.dtb.accesses                     14302902                       # DTB accesses
+system.cpu2.dtb.hits                         14281047                       # DTB hits
+system.cpu2.dtb.misses                          29697                       # DTB misses
+system.cpu2.dtb.accesses                     14310744                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1680,159 +1695,159 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.inst_hits                     4050371                       # ITB inst hits
-system.cpu2.itb.inst_misses                      4655                       # ITB inst misses
+system.cpu2.itb.inst_hits                     4054306                       # ITB inst hits
+system.cpu2.itb.inst_misses                      4589                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.itb.flush_tlb                         552                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid                542                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_mva_asid                543                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                    1717                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                    1707                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                      991                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                      958                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                 4055026                       # ITB inst accesses
-system.cpu2.itb.hits                          4050371                       # DTB hits
-system.cpu2.itb.misses                           4655                       # DTB misses
-system.cpu2.itb.accesses                      4055026                       # DTB accesses
-system.cpu2.numCycles                        88306923                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                 4058895                       # ITB inst accesses
+system.cpu2.itb.hits                          4054306                       # DTB hits
+system.cpu2.itb.misses                           4589                       # DTB misses
+system.cpu2.itb.accesses                      4058895                       # DTB accesses
+system.cpu2.numCycles                        88316329                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9346989                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      32490356                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                    4782343                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           2941476                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                      6854845                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                1758076                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     51100                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles              19188137                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles                 264                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles              924                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        33833                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       718254                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          435                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  4048944                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               289644                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2020                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          37402774                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.043825                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.431125                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9351504                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      32524106                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    4788852                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           2944598                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                      6861719                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                1761177                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     50498                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles              19190819                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles                 265                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles              860                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        33145                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles       719724                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          402                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  4052907                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               289738                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2002                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          37419321                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.044533                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.431855                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                30553136     81.69%     81.69% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  385541      1.03%     82.72% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  516309      1.38%     84.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  819811      2.19%     86.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  629209      1.68%     87.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  341976      0.91%     88.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                 1043472      2.79%     91.68% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  229749      0.61%     92.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 2883571      7.71%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                30562706     81.68%     81.68% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  385991      1.03%     82.71% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  516133      1.38%     84.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  820285      2.19%     86.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  630351      1.68%     87.96% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  341631      0.91%     88.88% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                 1045289      2.79%     91.67% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  230176      0.62%     92.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 2886759      7.71%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            37402774                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.054156                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.367925                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 9974482                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             19754417                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  6192036                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               324676                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               1156258                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              608942                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                52938                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              36945008                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts               178323                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               1156258                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                10522715                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                6823267                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles      11427905                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  5953488                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              1518249                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              34855169                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                   93                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                324878                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents               884563                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents             125                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands           37394312                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            160859531                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       148302897                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups             3365                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             26531284                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                10863027                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            285247                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        261616                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3319534                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6621271                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3899723                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           529692                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          779693                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  32174765                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             504636                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 34747602                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            55361                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        7180763                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     19089893                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        148627                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     37402774                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.929011                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.590003                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            37419321                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.054224                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.368268                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 9979534                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             19757337                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  6196813                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               326068                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles               1158658                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              609699                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                52950                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              36983425                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts               178083                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles               1158658                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                10528432                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                6814826                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles      11435729                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  5959486                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              1521262                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              34891179                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                   96                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                325442                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents               887620                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents             163                       # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands           37432161                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            161024301                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       148452649                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups             3370                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             26548024                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                10884136                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            285664                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        261962                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3325772                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6628163                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3904378                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           525369                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          781342                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  32207136                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             505175                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 34773283                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            55288                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        7195240                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     19128466                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        148705                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     37419321                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.929287                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.589860                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           24715445     66.08%     66.08% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            3980638     10.64%     76.72% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            2310084      6.18%     82.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            1974798      5.28%     88.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            2777209      7.43%     95.60% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             968528      2.59%     98.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             496348      1.33%     99.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             144954      0.39%     99.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              34770      0.09%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           24716493     66.05%     66.05% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            3990546     10.66%     76.72% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            2313548      6.18%     82.90% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            1974351      5.28%     88.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            2779950      7.43%     95.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             967650      2.59%     98.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             497474      1.33%     99.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             144778      0.39%     99.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              34531      0.09%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       37402774                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       37419321                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  19778      1.30%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      1.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead               1391818     91.56%     92.86% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               108581      7.14%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  19609      1.29%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     1      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      1.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead               1392955     91.52%     92.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               109452      7.19%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             8338      0.02%      0.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             19786480     56.94%     56.97% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               28071      0.08%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass             8340      0.02%      0.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             19803061     56.95%     56.97% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               28127      0.08%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     57.05% # Type of FU issued
@@ -1845,129 +1860,164 @@ system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     57.05% # Ty
 system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  5      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  3      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              5      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              3      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     57.05% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc           384      0.00%     57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead            11408808     32.83%     89.88% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3515506     10.12%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc           386      0.00%     57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead            11414599     32.83%     89.88% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3518761     10.12%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              34747602                       # Type of FU issued
-system.cpu2.iq.rate                          0.393487                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    1520177                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.043749                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         108495492                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         39865371                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     28048299                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads               7541                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes              3951                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses         3361                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              36255412                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                   4029                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          205816                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              34773283                       # Type of FU issued
+system.cpu2.iq.rate                          0.393736                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    1522017                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.043770                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         108565265                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         39912731                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     28072202                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads               7477                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes              4009                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses         3345                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              36282976                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                   3984                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          206198                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1533232                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1949                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         9487                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       562230                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1536367                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         2104                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         9509                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       563915                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads      5287398                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       344554                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads      5287425                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       344896                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               1156258                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                5195373                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                88422                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           32761739                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            61550                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6621271                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3899723                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            362828                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 29785                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents                 2577                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          9487                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        107399                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect        89296                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              196695                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             33832847                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts             11137918                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           914755                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles               1158658                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                5187034                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                87972                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           32794480                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            61964                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6628163                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3904378                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            362952                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 29501                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                 2651                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          9509                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        107755                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect        89629                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              197384                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             33857007                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts             11143266                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           916276                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        82338                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    14620271                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 3761250                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3482353                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.383128                       # Inst execution rate
-system.cpu2.iew.wb_sent                      33431998                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     28051660                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 16098716                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 29087027                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        82169                       # number of nop insts executed
+system.cpu2.iew.exec_refs                    14628489                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 3765120                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3485223                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.383361                       # Inst execution rate
+system.cpu2.iew.wb_sent                      33455826                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     28075547                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 16112995                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 29113416                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.317661                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.553467                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.317898                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.553456                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        7131660                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         356009                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           171002                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     36246314                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     0.700075                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.737192                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        7147493                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         356470                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           171471                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     36260461                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.700277                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.736744                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     27334959     75.41%     75.41% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4433375     12.23%     87.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1255912      3.46%     91.11% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3       639801      1.77%     92.88% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       511761      1.41%     94.29% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       317445      0.88%     95.16% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       418775      1.16%     96.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       310656      0.86%     97.18% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      1023630      2.82%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     27338017     75.39%     75.39% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4438533     12.24%     87.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1258858      3.47%     91.11% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3       640995      1.77%     92.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       514559      1.42%     94.29% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       318215      0.88%     95.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       418287      1.15%     96.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       309870      0.85%     97.18% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1023127      2.82%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     36246314                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            20540563                       # Number of instructions committed
-system.cpu2.commit.committedOps              25375153                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     36260461                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            20554943                       # Number of instructions committed
+system.cpu2.commit.committedOps              25392373                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8425532                       # Number of memory references committed
-system.cpu2.commit.loads                      5088039                       # Number of loads committed
-system.cpu2.commit.membars                      94081                       # Number of memory barriers committed
-system.cpu2.commit.branches                   3238597                       # Number of branches committed
+system.cpu2.commit.refs                       8432259                       # Number of memory references committed
+system.cpu2.commit.loads                      5091796                       # Number of loads committed
+system.cpu2.commit.membars                      94283                       # Number of memory barriers committed
+system.cpu2.commit.branches                   3240263                       # Number of branches committed
 system.cpu2.commit.fp_insts                      3299                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 22633154                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              295425                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events              1023630                       # number cycles where commit BW limit reached
+system.cpu2.commit.int_insts                 22648524                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              295510                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        16933133     66.69%     66.69% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          26595      0.10%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc          386      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5091796     20.05%     86.84% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       3340463     13.16%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::total         25392373                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              1023127                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                    67208837                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   66213984                       # The number of ROB writes
-system.cpu2.timesIdled                         359252                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       50904149                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  3546216081                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   20485207                       # Number of Instructions Simulated
-system.cpu2.committedOps                     25319797                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total             20485207                       # Number of Instructions Simulated
-system.cpu2.cpi                              4.310765                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        4.310765                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.231977                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.231977                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               156999830                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               29869338                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    46882                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   45194                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads               67020139                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                296788                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                    67255841                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   66282532                       # The number of ROB writes
+system.cpu2.timesIdled                         358696                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                       50897008                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  3546076715                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   20499567                       # Number of Instructions Simulated
+system.cpu2.committedOps                     25336997                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total             20499567                       # Number of Instructions Simulated
+system.cpu2.cpi                              4.308205                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        4.308205                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.232115                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.232115                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               157113831                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               29893796                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    46822                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   45178                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads               67223937                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                297064                       # number of misc regfile writes
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
@@ -1984,10 +2034,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1539425711000                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1539425711000                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1539425711000                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1539425711000                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1535534030000                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1535534030000                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1535534030000                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1535534030000                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index ef9bf74a4..2ae3638d8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,166 +1,154 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.550648                       # Number of seconds simulated
-sim_ticks                                2550647964000                       # Number of ticks simulated
-final_tick                               2550647964000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.550603                       # Number of seconds simulated
+sim_ticks                                2550603285500                       # Number of ticks simulated
+final_tick                               2550603285500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  57676                       # Simulator instruction rate (inst/s)
-host_op_rate                                    74213                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2439007396                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 470664                       # Number of bytes of host memory used
-host_seconds                                  1045.77                       # Real time elapsed on the host
-sim_insts                                    60315890                       # Number of instructions simulated
-sim_ops                                      77609880                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  56179                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72287                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2375661490                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 471120                       # Number of bytes of host memory used
+host_seconds                                  1073.64                       # Real time elapsed on the host
+sim_insts                                    60315997                       # Number of instructions simulated
+sim_ops                                      77609994                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker         2048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         1984                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           483008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5043284                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           315584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4051356                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131006576                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       483008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       315584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          798592                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3785856                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1521376                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1494724                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6801956                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst           487168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5091220                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           310848                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4002308                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131004952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       487168                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       310848                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          798016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3785472                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1521388                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1494684                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6801544                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker           32                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           31                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              7547                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             78836                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              4931                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             63309                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15293483                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59154                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           380344                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           373681                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813179                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47482259                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           803                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst              7612                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             79585                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           12                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              4857                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             62537                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15293452                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59148                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           380347                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           373671                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               813166                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47483091                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           778                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              189367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1977256                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           251                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              123727                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1588363                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51362077                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         189367                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         123727                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             313094                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1484272                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             596466                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             586017                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2666756                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1484272                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47482259                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          803                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              191001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1996085                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           301                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              121872                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1569161                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51362340                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         191001                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         121872                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             312873                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1484148                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             596482                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             586012                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2666641                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1484148                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47483091                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          778                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             189367                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            2573722                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          251                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             123727                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2174381                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54028833                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15293483                       # Number of read requests accepted
-system.physmem.writeReqs                       813179                       # Number of write requests accepted
-system.physmem.readBursts                    15293483                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813179                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                976671488                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   2111424                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6834624                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131006576                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6801956                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    32991                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706366                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4694                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              955809                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              953120                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              953063                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              953290                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              955524                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              952811                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              952747                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              952554                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              956154                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              953015                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             952848                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             952579                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             956184                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             953741                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             953594                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             953459                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6616                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6407                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6542                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6564                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6491                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6761                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6753                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6706                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7029                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6806                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6476                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6118                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7056                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst             191001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            2592566                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          301                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             121872                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2155173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54028981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15293452                       # Number of read requests accepted
+system.physmem.writeReqs                       813166                       # Number of write requests accepted
+system.physmem.readBursts                    15293452                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     813166                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                977025792                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   1755136                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6829888                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131004952                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6801544                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    27424                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706426                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4680                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              955870                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              953353                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              953267                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              953402                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              955744                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              953745                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              953482                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              953247                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              956258                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              953771                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             953551                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             953111                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             956206                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             953857                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             953612                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             953552                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6609                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6381                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6537                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6560                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6488                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6754                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6745                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6685                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7023                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6801                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6470                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6120                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7060                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               6677                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6959                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6830                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6963                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6844                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2550646795500                       # Total gap between requests
+system.physmem.totGap                    2550602119500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                      44                       # Read request sizes (log2)
+system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
 system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154623                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154598                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                 754025                       # Write request sizes (log2)
+system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59154                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1055042                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    994364                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    947765                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    947544                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    945397                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    945218                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2783572                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2783267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3699218                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     24042                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    23218                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    23233                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    22770                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    22263                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    21886                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    21619                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       50                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       16                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  59148                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1066844                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1005139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    964469                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1068011                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    971384                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1033822                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2692544                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2602827                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3401172                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    112530                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   102949                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    95927                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    92392                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19066                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18545                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18331                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       57                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -174,61 +162,61 @@ system.physmem.rdQLenPdf::29                        0                       # Wh
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                       297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3959                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4958                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5855                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4875                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4842                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      982                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1034                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      918                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      853                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      851                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      846                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      844                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4792                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6078                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6458                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6079                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6047                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6081                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5943                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5894                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5982                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5778                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
@@ -237,93 +225,76 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       965273                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     1013.486813                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     999.850047                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev      92.541667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           4202      0.44%      0.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         3517      0.36%      0.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1855      0.19%      0.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1291      0.13%      1.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          949      0.10%      1.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          717      0.07%      1.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          589      0.06%      1.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          765      0.08%      1.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       951388     98.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         965273                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5001                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      3051.486103                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    52637.524815                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535          4974     99.46%     99.46% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::65536-131071            1      0.02%     99.48% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::131072-196607            8      0.16%     99.64% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143            6      0.12%     99.76% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::393216-458751            1      0.02%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::589824-655359            2      0.04%     99.82% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.84% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            7      0.14%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1010962                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      973.187598                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     908.669037                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     201.227455                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22588      2.23%      2.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        20116      1.99%      4.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8785      0.87%      5.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2331      0.23%      5.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2167      0.21%      5.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1761      0.17%      5.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9115      0.90%      6.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          858      0.08%      6.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       943241     93.30%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1010962                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6071                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2514.580135                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    47785.198367                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          6044     99.56%     99.56% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::65536-131071            1      0.02%     99.57% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::131072-196607            8      0.13%     99.70% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143            6      0.10%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::393216-458751            1      0.02%     99.82% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::589824-655359            2      0.03%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.87% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            7      0.12%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5001                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5001                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.353929                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.695200                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        9.701170                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1                   8      0.16%      0.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2                   2      0.04%      0.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3                   3      0.06%      0.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4                   1      0.02%      0.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5                   8      0.16%      0.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6                   1      0.02%      0.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7                   1      0.02%      0.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8                   3      0.06%      0.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9                   5      0.10%      0.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10                  2      0.04%      0.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::11                  5      0.10%      0.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12                  2      0.04%      0.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13                  1      0.02%      0.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14                  1      0.02%      0.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15                 10      0.20%      1.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2816     56.31%     57.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 26      0.52%     57.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                135      2.70%     60.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                879     17.58%     78.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 49      0.98%     79.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 23      0.46%     79.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 15      0.30%     79.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 25      0.50%     80.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 14      0.28%     80.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 18      0.36%     81.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  7      0.14%     81.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 15      0.30%     81.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 16      0.32%     81.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 18      0.36%     82.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                 15      0.30%     82.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  8      0.16%     82.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                 16      0.32%     82.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                 10      0.20%     83.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  1      0.02%     83.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  1      0.02%     83.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  3      0.06%     83.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                243      4.86%     88.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                480      9.60%     97.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                 27      0.54%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                 20      0.40%     98.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                 27      0.54%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                 21      0.42%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                 16      0.32%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  2      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5001                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   577566851750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              682115428000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  76302460000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 28246116250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       37847.20                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1850.93                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            6071                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6071                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.578158                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.392553                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.387042                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1                   4      0.07%      0.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   4      0.07%      0.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   2      0.03%      0.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   7      0.12%      0.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   2      0.03%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6                   2      0.03%      0.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7                   3      0.05%      0.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8                   4      0.07%      0.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9                   6      0.10%      0.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10                  2      0.03%      0.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11                  3      0.05%      0.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13                  2      0.03%      0.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14                  4      0.07%      0.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                 12      0.20%      0.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2739     45.12%     46.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 35      0.58%     46.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1542     25.40%     72.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1308     21.55%     93.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 93      1.53%     95.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 45      0.74%     95.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 49      0.81%     96.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 58      0.96%     97.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 25      0.41%     98.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 17      0.28%     98.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 20      0.33%     98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 16      0.26%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 13      0.21%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 14      0.23%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                 14      0.23%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 16      0.26%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                 10      0.16%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6071                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   393355196000                       # Total ticks spent queuing
+system.physmem.totMemAccLat              679593221000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76330140000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25766.70                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44698.13                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         382.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44516.70                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         383.06                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.68                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       51.36                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.67                       # Average system write bandwidth in MiByte/s
@@ -331,299 +302,308 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           3.01                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.99                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.73                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        15.38                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14274135                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     91331                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.54                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.51                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158359.74                       # Average gap between requests
-system.physmem.pageHitRate                      93.48                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.60                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     54969038                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16346130                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16346133                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763365                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763365                       # Transaction distribution
-system.membus.trans_dist::Writeback             59154                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4693                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4694                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131434                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131434                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq             3                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq              3                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp             3                       # Transaction distribution
+system.physmem.avgRdQLen                         6.51                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        15.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14270645                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     91138                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.38                       # Row buffer hit rate for writes
+system.physmem.avgGap                       158357.40                       # Average gap between requests
+system.physmem.pageHitRate                      93.42                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2202343950500                       # Time in different power states
+system.physmem.memoryStateTime::REF       85170020000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      263082705750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     54969203                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16346092                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16346092                       # Transaction distribution
+system.membus.trans_dist::WriteReq             763361                       # Transaction distribution
+system.membus.trans_dist::WriteResp            763361                       # Transaction distribution
+system.membus.trans_dist::Writeback             59148                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4680                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4680                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131444                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131444                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383060                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3790                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1885926                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4272780                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1885816                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4272670                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34550412                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34550302                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390486                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7580                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16698004                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     19096138                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16695968                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     19094102                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           140206666                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              140206666                       # Total data (bytes)
+system.membus.tot_pkt_size::total           140204630                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              140204630                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1487459000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1486938500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3645000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3616000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17565357500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17564463000                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4737629056                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4735162713                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37816335199                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        37454635709                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    64394                       # number of replacements
-system.l2c.tags.tagsinuse                51423.269942                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1904392                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   129782                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    14.673776                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             2513283956500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36971.606132                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    22.825180                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000372                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4577.267389                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3052.603978                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.951997                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3614.635006                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3176.379887                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.564142                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000348                       # Average percentage of cache occupancy
+system.l2c.tags.replacements                    64370                       # number of replacements
+system.l2c.tags.tagsinuse                51446.531370                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1904863                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   129760                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    14.679894                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle             2513258094500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   36996.902854                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    21.266230                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000371                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4638.850911                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3223.219228                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    10.615555                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3561.358912                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2994.317308                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.564528                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000324                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.069844                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.046579                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000121                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.055155                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.048468                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.784657                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023           21                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65367                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu0.inst       0.070783                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.049182                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000162                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.054342                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.045690                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.785012                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023           22                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65368                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3070                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6838                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55080                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000320                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.997421                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 18929537                       # Number of tag accesses
-system.l2c.tags.data_accesses                18929537                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        32378                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         6463                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             508619                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             187861                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        31368                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         7240                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             462078                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             199585                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1435592                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          608227                       # number of Writeback hits
-system.l2c.Writeback_hits::total               608227                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              20                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              19                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  39                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data             5                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data             6                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                11                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            60126                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            52843                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               112969                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         32378                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          6463                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              508619                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              247987                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         31368                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          7240                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              462078                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              252428                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1548561                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        32378                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         6463                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             508619                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             247987                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        31368                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         7240                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             462078                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             252428                       # number of overall hits
-system.l2c.overall_hits::total                1548561                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker           32                       # number of ReadReq misses
+system.l2c.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          347                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3064                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6835                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55083                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000336                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997437                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 18932032                       # Number of tag accesses
+system.l2c.tags.data_accesses                18932032                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        32158                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         6860                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             505744                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             187679                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        31450                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         7231                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             465794                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             199404                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1436320                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          607907                       # number of Writeback hits
+system.l2c.Writeback_hits::total               607907                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              19                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              15                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  34                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data             2                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data             5                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 7                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            58462                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            54465                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               112927                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         32158                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          6860                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              505744                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              246141                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         31450                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          7231                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              465794                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              253869                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1549247                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        32158                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         6860                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             505744                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             246141                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        31450                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         7231                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             465794                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             253869                       # number of overall hits
+system.l2c.overall_hits::total                1549247                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker           31                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             7439                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6013                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker           10                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             4938                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             4716                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                23150                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1629                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1286                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2915                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          73716                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          59496                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133212                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker           32                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu0.inst             7502                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6162                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker           12                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             4864                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             4544                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                23117                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1628                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1276                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2904                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          74336                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          58884                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133220                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker           31                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7439                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             79729                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              4938                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             64212                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                156362                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker           32                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst              7502                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             80498                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           12                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              4864                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             63428                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                156337                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker           31                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7439                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            79729                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           10                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             4938                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            64212                       # number of overall misses
-system.l2c.overall_misses::total               156362                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2459000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker       158000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    535184750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    452595249                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       747500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    359066750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    362580750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1712791999                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data       209991                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       255489                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       465480                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   5481304360                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4400908112                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9882212472                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker      2459000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       158000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    535184750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   5933899609                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker       747500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    359066750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   4763488862                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     11595004471                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker      2459000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       158000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    535184750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   5933899609                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker       747500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    359066750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   4763488862                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    11595004471                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        32410                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         6465                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         516058                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         193874                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        31378                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         7240                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         467016                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         204301                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1458742                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       608227                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           608227                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1649                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1305                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2954                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data            6                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data            6                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            12                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       133842                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       112339                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           246181                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        32410                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6465                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          516058                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          327716                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        31378                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         7240                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          467016                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          316640                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1704923                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        32410                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6465                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         516058                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         327716                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        31378                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         7240                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         467016                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         316640                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1704923                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000987                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000309                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014415                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.031015                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000319                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010574                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.023084                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015870                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.987871                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.985441                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.986798                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.166667                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.083333                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.550769                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.529611                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.541114                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000987                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000309                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014415                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.243287                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000319                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010574                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.202792                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.091712                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000987                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000309                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014415                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.243287                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000319                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010574                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.202792                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.091712                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 76843.750000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        79000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71943.103912                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 75269.457675                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72715.016201                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 76883.110687                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 73986.695421                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   128.907919                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   198.669518                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   159.684391                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74357.050844                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73969.814979                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 74184.101072                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 76843.750000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 71943.103912                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 74425.862722                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72715.016201                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 74183.779698                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 74154.874400                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 76843.750000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 71943.103912                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 74425.862722                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72715.016201                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 74183.779698                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 74154.874400                       # average overall miss latency
+system.l2c.overall_misses::cpu0.inst             7502                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            80498                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           12                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             4864                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            63428                       # number of overall misses
+system.l2c.overall_misses::total               156337                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2994000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker       368000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    537467000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    452401999                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       913750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    350167750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    341997500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1686309999                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data       186492                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       326986                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       513478                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5509515842                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4330037632                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   9839553474                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      2994000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       368000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    537467000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   5961917841                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       913750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    350167750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   4672035132                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     11525863473                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      2994000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       368000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    537467000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   5961917841                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       913750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    350167750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   4672035132                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    11525863473                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        32189                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         6862                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         513246                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         193841                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        31462                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         7231                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         470658                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         203948                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1459437                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       607907                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           607907                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1647                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1291                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2938                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data            5                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             7                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       132798                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       113349                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           246147                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        32189                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6862                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          513246                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          326639                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        31462                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7231                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          470658                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          317297                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1705584                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        32189                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6862                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         513246                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         326639                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        31462                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7231                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         470658                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         317297                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1705584                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000963                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000291                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014617                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.031789                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.010334                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.022280                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.015840                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.988464                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.988381                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.988428                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.559767                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.519493                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.541221                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000963                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000291                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014617                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.246443                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.010334                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.199901                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.091662                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000963                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000291                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014617                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.246443                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.010334                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.199901                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.091662                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96580.645161                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       184000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71643.161824                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 73418.045927                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76145.833333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71991.724918                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 75263.534331                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 72946.749102                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   114.552826                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   256.258621                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   176.817493                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74116.388318                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73535.045717                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 73859.431572                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96580.645161                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker       184000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 71643.161824                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 74062.931265                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76145.833333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 71991.724918                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 73658.875134                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 73724.476439                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96580.645161                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker       184000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 71643.161824                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 74062.931265                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76145.833333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 71991.724918                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 73658.875134                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 73724.476439                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -632,166 +612,154 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               59154                       # number of writebacks
-system.l2c.writebacks::total                    59154                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            40                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks               59148                       # number of writebacks
+system.l2c.writebacks::total                    59148                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data            42                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            22                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                78                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             40                       # number of demand (read+write) MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data            24                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                81                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             42                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             22                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 78                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            40                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             24                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 81                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            42                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            22                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                78                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           32                       # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::cpu1.data            24                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                81                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           31                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         7430                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         5973                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         4931                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         4694                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           23072                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1629                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1286                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2915                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        73716                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        59496                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133212                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker           32                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         7494                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         6120                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           12                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         4857                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         4520                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           23036                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         1628                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1276                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2904                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        74336                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        58884                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133220                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           31                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         7430                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        79689                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         4931                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        64190                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           156284                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           32                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         7494                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        80456                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           12                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         4857                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        63404                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           156256                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker           31                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         7430                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        79689                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           10                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         4931                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        64190                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          156284                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2062500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       133500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    441209000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    375003749                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    296681500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    302775000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1418490249                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     16291629                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     12864285                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     29155914                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4563686640                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3660844388                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8224531028                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2062500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    441209000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   4938690389                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    296681500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   3963619388                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   9643021277                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2062500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       133500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    441209000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   4938690389                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    296681500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   3963619388                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   9643021277                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6566249                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83827031250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83117321750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 166950919249                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8951884751                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8422103999                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  17373988750                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       116250                       # number of LoadLockedReq MSHR uncacheable cycles
-system.l2c.LoadLockedReq_mshr_uncacheable_latency::total       116250                       # number of LoadLockedReq MSHR uncacheable cycles
-system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        60000                       # number of StoreCondReq MSHR uncacheable cycles
-system.l2c.StoreCondReq_mshr_uncacheable_latency::total        60000                       # number of StoreCondReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6566249                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92778916001                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91539425749                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184324907999                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000987                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000309                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014398                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.030809                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000319                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010559                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.022976                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.015816                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987871                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.985441                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.986798                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.166667                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.083333                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.550769                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.529611                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.541114                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000987                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000309                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014398                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.243165                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000319                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010559                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.202722                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.091666                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000987                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000309                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014398                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.243165                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000319                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010559                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.202722                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.091666                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59382.099596                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62783.149004                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60166.599067                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64502.556455                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 61481.026742                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_misses::cpu0.inst         7494                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        80456                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           12                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         4857                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        63404                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          156256                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2611500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       343500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    442660000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    373109249                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       763750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    288530250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    284079000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1392097249                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     16281628                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     12763275                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     29044903                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4584247158                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3597170868                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8181418026                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2611500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       343500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    442660000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4957356407                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       763750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    288530250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   3881249868                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   9573515275                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2611500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       343500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    442660000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4957356407                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       763750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    288530250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   3881249868                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   9573515275                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6521499                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83889052500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83054276000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166949849999                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8950146108                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8426611000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  17376757108                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6521499                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92839198608                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91480887000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184326607107                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000963                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000291                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014601                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.031572                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010320                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.022163                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.015784                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.988464                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.988381                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.988428                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.559767                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.519493                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.541221                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000963                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000291                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014601                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.246315                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010320                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.199825                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.091614                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000963                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000291                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014601                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.246315                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010320                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.199825                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.091614                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       171750                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59068.588204                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60965.563562                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59405.033972                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62849.336283                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 60431.379102                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.332037                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.028816                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61909.037929                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61530.932970                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 61740.166261                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59382.099596                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61974.555949                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60166.599067                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61748.237856                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 61701.909837                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59382.099596                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61974.555949                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60166.599067                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61748.237856                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 61701.909837                       # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.566614                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.688361                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61669.274080                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61089.105156                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61412.836106                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       171750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59068.588204                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61615.745339                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59405.033972                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61214.590057                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61268.145063                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       171750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59068.588204                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61615.745339                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59405.033972                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61214.590057                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61268.145063                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
@@ -799,10 +767,6 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
-system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
-system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
-system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
@@ -814,43 +778,40 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    58424320                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2676714                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2676716                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            763365                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           763365                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           608227                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2954                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            12                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2966                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           246181                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          246181                       # Transaction distribution
-system.toL2Bus.trans_dist::LoadLockedReq            3                       # Transaction distribution
-system.toL2Bus.trans_dist::StoreCondReq             3                       # Transaction distribution
-system.toL2Bus.trans_dist::StoreCondResp            3                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1967568                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5797861                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37552                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       149979                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7952960                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     62924224                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     85579658                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        54820                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       255152                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          148813854                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             148813854                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          206020                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4963822946                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    58427348                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2677396                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2677395                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            763361                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           763361                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           607907                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2938                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             7                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2945                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           246147                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          246147                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1969203                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5796633                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        38454                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       149595                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7953885                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     62977408                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     85532246                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        56372                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       254604                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          148820630                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             148820630                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          204356                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4962673723                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4432706696                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4436346984                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4484503287                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4483051170                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          23902881                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          24406904                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          86618127                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          86367392                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      48419467                       # Throughput (bytes/s)
+system.iobus.throughput                      48420315                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq             16322169                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            16322169                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8177                       # Transaction distribution
@@ -960,17 +921,17 @@ system.iobus.reqLayer25.occupancy         15138816000                       # La
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374883000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         37825687801                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         38146923291                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                7508483                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted          5992866                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           375676                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             4822577                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                3918936                       # Number of BTB hits
+system.cpu0.branchPred.lookups                7527303                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted          6005482                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           376664                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             4812068                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                3910560                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            81.262279                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 722501                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             39246                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            81.265685                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 724420                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             38989                       # Number of incorrect RAS predictions.
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -994,25 +955,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    25709068                       # DTB read hits
-system.cpu0.dtb.read_misses                     39624                       # DTB read misses
-system.cpu0.dtb.write_hits                    6152335                       # DTB write hits
-system.cpu0.dtb.write_misses                    10221                       # DTB write misses
+system.cpu0.dtb.read_hits                    25762472                       # DTB read hits
+system.cpu0.dtb.read_misses                     39475                       # DTB read misses
+system.cpu0.dtb.write_hits                    6143291                       # DTB write hits
+system.cpu0.dtb.write_misses                    10324                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         514                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                760                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid                752                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    5608                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1406                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   264                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    5580                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1376                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   262                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      646                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                25748692                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6162556                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      639                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                25801947                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6153615                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         31861403                       # DTB hits
-system.cpu0.dtb.misses                          49845                       # DTB misses
-system.cpu0.dtb.accesses                     31911248                       # DTB accesses
+system.cpu0.dtb.hits                         31905763                       # DTB hits
+system.cpu0.dtb.misses                          49799                       # DTB misses
+system.cpu0.dtb.accesses                     31955562                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1034,687 +995,714 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                     5876098                       # ITB inst hits
-system.cpu0.itb.inst_misses                      7014                       # ITB inst misses
+system.cpu0.itb.inst_hits                     5893431                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7431                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         514                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                760                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid                752                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2644                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2617                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1469                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1506                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                 5883112                       # ITB inst accesses
-system.cpu0.itb.hits                          5876098                       # DTB hits
-system.cpu0.itb.misses                           7014                       # DTB misses
-system.cpu0.itb.accesses                      5883112                       # DTB accesses
-system.cpu0.numCycles                       242192321                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                 5900862                       # ITB inst accesses
+system.cpu0.itb.hits                          5893431                       # DTB hits
+system.cpu0.itb.misses                           7431                       # DTB misses
+system.cpu0.itb.accesses                      5900862                       # DTB accesses
+system.cpu0.numCycles                       242264674                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          15567613                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      45445847                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                    7508483                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           4641437                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     10272972                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                2435180                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                     81106                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles              50250706                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                1544                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             1986                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles        48114                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles      1489776                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          378                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  5874191                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               367063                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   2900                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples          79394723                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.721041                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.068559                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          15531926                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      45587183                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    7527303                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           4634980                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     10285875                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                2434733                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                     89107                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles              50171859                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles                1648                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             2068                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles        54478                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles      1474048                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          435                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  5891523                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               366856                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3025                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples          79291736                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.723314                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.072188                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                69128739     87.07%     87.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  676261      0.85%     87.92% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                  870795      1.10%     89.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 1169302      1.47%     90.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1115285      1.40%     91.90% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  553948      0.70%     92.59% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 1287197      1.62%     94.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  378519      0.48%     94.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4214677      5.31%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                69012854     87.04%     87.04% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  680232      0.86%     87.89% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                  874808      1.10%     89.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 1172230      1.48%     90.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1090891      1.38%     91.85% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  557599      0.70%     92.56% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 1295199      1.63%     94.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  379880      0.48%     94.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4228043      5.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            79394723                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.031002                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.187644                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                16658432                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             51288095                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  9197431                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               656874                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1591763                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1006093                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                91406                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              54494283                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               303520                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1591763                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                17551658                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               20345183                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      27653568                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  8896202                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              3354292                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              51932303                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                  196                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                500448                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              2179621                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents             261                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands           53595851                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            240832893                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       219678051                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             5082                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             39195467                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                14400384                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts            591696                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        540219                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  6961736                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            10014185                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6974197                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1050889                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1353332                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  48232956                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1025841                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 61971057                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            88766                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        9957722                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     24611703                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        275811                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     79394723                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.780544                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.499047                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            79291736                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.031071                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.188171                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                16635366                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             51194908                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  9213198                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               653944                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1592125                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1010665                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                90813                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              54600074                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               300654                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1592125                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                17527482                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               20299787                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      27625200                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  8910460                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              3334547                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              52031373                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                  331                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                485563                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              2176301                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents             182                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands           53736698                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            241285167                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       220106334                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             4864                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             39390817                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                14345881                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            590593                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        539084                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  6947132                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            10055649                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6962422                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1056834                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1358453                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  48348288                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1003135                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 62086915                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            89013                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        9905639                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     24691410                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        254686                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     79291736                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.783019                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.501466                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           56910995     71.68%     71.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            7345017      9.25%     80.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3503110      4.41%     85.34% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2918035      3.68%     89.02% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            6157997      7.76%     96.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1482939      1.87%     98.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             783446      0.99%     99.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             227116      0.29%     99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              66068      0.08%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           56790483     71.62%     71.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            7331291      9.25%     80.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3517102      4.44%     85.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2900884      3.66%     88.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            6182474      7.80%     96.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1488398      1.88%     98.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             785922      0.99%     99.63% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             230106      0.29%     99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              65076      0.08%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       79394723                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       79291736                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  29670      0.67%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     1      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4193006     94.32%     94.99% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               222912      5.01%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  31039      0.70%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     1      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4198728     94.33%     95.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               221343      4.97%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass            15869      0.03%      0.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             29065604     46.90%     46.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               46869      0.08%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                 10      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          1239      0.00%     47.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     47.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            26385475     42.58%     89.58% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            6455974     10.42%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass            14970      0.02%      0.02% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             29137192     46.93%     46.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               47374      0.08%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                 11      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          1226      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            26440432     42.59%     89.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            6445693     10.38%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              61971057                       # Type of FU issued
-system.cpu0.iq.rate                          0.255875                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    4445589                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.071737                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         207909567                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         59225484                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     43186225                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              11292                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              6130                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         5133                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              66394829                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   5948                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          311727                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              62086915                       # Type of FU issued
+system.cpu0.iq.rate                          0.256277                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    4451111                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.071692                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         208044448                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         59266351                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     43285904                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              10871                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              5830                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         4924                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              66517304                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   5752                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          316537                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2130667                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         3740                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        15655                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       850179                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2144033                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         4052                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        15721                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       849604                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads     17067257                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       348827                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads     17082730                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       349385                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1591763                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               15715155                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               239745                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           49373573                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           105603                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             10014185                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6974197                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            727713                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 55741                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 4727                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         15655                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        183161                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       144870                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              328031                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             60906320                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             26058550                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          1064737                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1592125                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               15682380                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               239912                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           49471978                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           105539                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             10055649                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6962422                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            704937                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 56286                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 4027                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         15721                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        184221                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       145235                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              329456                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             61023718                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             26110824                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1063197                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       114776                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    32455686                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 5967734                       # Number of branches executed
-system.cpu0.iew.exec_stores                   6397136                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.251479                       # Inst execution rate
-system.cpu0.iew.wb_sent                      60414213                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     43191358                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 23287316                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 42834885                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       120555                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    32498156                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 5982225                       # Number of branches executed
+system.cpu0.iew.exec_stores                   6387332                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.251889                       # Inst execution rate
+system.cpu0.iew.wb_sent                      60528797                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     43290828                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 23369621                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 42956226                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.178335                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.543653                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.178692                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.544033                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        9785836                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         750030                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           285660                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     77802960                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.502286                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.465598                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        9786876                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         748449                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           287258                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     77699611                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.504830                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.472024                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     63388396     81.47%     81.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7400911      9.51%     90.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      1988257      2.56%     93.54% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1098992      1.41%     94.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4       865715      1.11%     96.07% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       575312      0.74%     96.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       733525      0.94%     97.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       350428      0.45%     98.20% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1401424      1.80%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     63277588     81.44%     81.44% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7407512      9.53%     90.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      1967451      2.53%     93.50% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1105852      1.42%     94.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4       852897      1.10%     96.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       576328      0.74%     96.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       737114      0.95%     97.72% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       349768      0.45%     98.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1425101      1.83%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     77802960                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            29900744                       # Number of instructions committed
-system.cpu0.commit.committedOps              39079359                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     77699611                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            30084753                       # Number of instructions committed
+system.cpu0.commit.committedOps              39225066                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      14007536                       # Number of memory references committed
-system.cpu0.commit.loads                      7883518                       # Number of loads committed
-system.cpu0.commit.membars                     209346                       # Number of memory barriers committed
-system.cpu0.commit.branches                   5162239                       # Number of branches committed
-system.cpu0.commit.fp_insts                      5086                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 34792812                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              507721                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1401424                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      14024434                       # Number of memory references committed
+system.cpu0.commit.loads                      7911616                       # Number of loads committed
+system.cpu0.commit.membars                     209739                       # Number of memory barriers committed
+system.cpu0.commit.branches                   5192960                       # Number of branches committed
+system.cpu0.commit.fp_insts                      4874                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 34907078                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              509367                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        25154804     64.13%     64.13% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          44602      0.11%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     64.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         1226      0.00%     64.25% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     64.25% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.25% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.25% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        7911616     20.17%     84.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       6112818     15.58%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::total         39225066                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1425101                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   124291086                       # The number of ROB reads
-system.cpu0.rob.rob_writes                   99365166                       # The number of ROB writes
-system.cpu0.timesIdled                         908697                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                      162797598                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2248209209                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   29823122                       # Number of Instructions Simulated
-system.cpu0.committedOps                     39001737                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             29823122                       # Number of Instructions Simulated
-system.cpu0.cpi                              8.120958                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        8.120958                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.123138                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.123138                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               276680521                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               43875243                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    44965                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   42348                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads              137565982                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                581037                       # number of misc regfile writes
-system.cpu0.icache.tags.replacements           983714                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.569506                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           10510100                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           984226                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.678543                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       7060452000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   317.023627                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   194.545879                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.619187                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.379972                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999159                       # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads                   124324951                       # The number of ROB reads
+system.cpu0.rob.rob_writes                   99658992                       # The number of ROB writes
+system.cpu0.timesIdled                         907419                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                      162972938                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2247980405                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   30002566                       # Number of Instructions Simulated
+system.cpu0.committedOps                     39142879                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             30002566                       # Number of Instructions Simulated
+system.cpu0.cpi                              8.074798                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        8.074798                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.123842                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.123842                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               277224657                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               43993248                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    44815                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   42286                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads              137449038                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                580454                       # number of misc regfile writes
+system.cpu0.icache.tags.replacements           984532                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.571226                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           10502635                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           985044                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.662097                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       7040991250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   317.697202                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   193.874025                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.620502                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.378660                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999163                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          163                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         12559701                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        12559701                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      5314791                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      5195309                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       10510100                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      5314791                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      5195309                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        10510100                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      5314791                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      5195309                       # number of overall hits
-system.cpu0.icache.overall_hits::total       10510100                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       559278                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       506065                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1065343                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       559278                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       506065                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1065343                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       559278                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       506065                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1065343                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7693667190                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6830219775                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14523886965                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   7693667190                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   6830219775                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14523886965                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   7693667190                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   6830219775                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14523886965                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      5874069                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      5701374                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     11575443                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      5874069                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      5701374                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     11575443                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      5874069                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      5701374                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     11575443                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.095211                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.088762                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.092035                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.095211                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.088762                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.092035                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.095211                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.088762                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.092035                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13756.427376                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13496.724284                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13633.061807                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13756.427376                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13496.724284                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13633.061807                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13756.427376                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13496.724284                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13633.061807                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         6850                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              406                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.871921                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses         12553911                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        12553911                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      5335132                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      5167503                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       10502635                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      5335132                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      5167503                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        10502635                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      5335132                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      5167503                       # number of overall hits
+system.cpu0.icache.overall_hits::total       10502635                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       556266                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       509949                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1066215                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       556266                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       509949                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1066215                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       556266                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       509949                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1066215                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7659182978                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6870398274                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14529581252                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7659182978                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   6870398274                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14529581252                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7659182978                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   6870398274                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14529581252                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      5891398                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      5677452                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     11568850                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      5891398                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      5677452                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     11568850                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      5891398                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      5677452                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     11568850                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.094420                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.089820                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.092163                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.094420                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.089820                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.092163                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.094420                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.089820                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.092163                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13768.921663                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13472.716436                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13627.252714                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13768.921663                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13472.716436                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13627.252714                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13768.921663                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13472.716436                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13627.252714                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         6572                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          144                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              397                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.554156                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          144                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42606                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        38478                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        81084                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        42606                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        38478                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        81084                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        42606                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        38478                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        81084                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       516672                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       467587                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       984259                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       516672                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       467587                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       984259                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       516672                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       467587                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       984259                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6254333936                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5558733090                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11813067026                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6254333936                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5558733090                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11813067026                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6254333936                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5558733090                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11813067026                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9017250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9017250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9017250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total      9017250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087958                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.082013                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085030                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087958                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.082013                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.085030                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087958                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.082013                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.085030                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12105.037502                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11888.125825                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12001.990356                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12105.037502                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11888.125825                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12001.990356                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12105.037502                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11888.125825                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12001.990356                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42425                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        38728                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        81153                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        42425                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        38728                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        81153                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        42425                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        38728                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        81153                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       513841                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       471221                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       985062                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       513841                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       471221                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       985062                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       513841                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       471221                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       985062                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6224566388                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5591223594                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11815789982                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6224566388                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5591223594                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11815789982                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6224566388                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5591223594                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11815789982                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8993000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8993000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8993000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total      8993000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087219                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.082999                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085148                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087219                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.082999                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.085148                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087219                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.082999                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.085148                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12113.798603                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11865.395630                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11994.970857                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12113.798603                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11865.395630                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11994.970857                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12113.798603                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11865.395630                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11994.970857                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           643844                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.993221                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           21529454                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           644356                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            33.412359                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         43687250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   256.274589                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   255.718633                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.500536                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.499450                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           643424                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.993257                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           21526419                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           643936                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            33.429439                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         43468250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   254.820066                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   257.173192                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.497695                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.502291                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          190                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        101648096                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       101648096                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      7014056                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      6760706                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13774762                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3747600                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      3513292                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       7260892                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116614                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       126440                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       243054                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       119391                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       128245                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247636                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10761656                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     10273998                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        21035654                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10761656                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     10273998                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       21035654                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       333491                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       414863                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       748354                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1635288                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1327358                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2962646                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7514                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6065                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13579                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            6                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1968779                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      1742221                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3711000                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1968779                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1742221                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3711000                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5348440293                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6102853229                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  11451293522                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  83999211786                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  64837852526                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 148837064312                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    107360498                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     81153996                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    188514494                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        90501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        78000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       168501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  89347652079                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  70940705755                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 160288357834                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  89347652079                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  70940705755                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 160288357834                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7347547                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      7175569                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     14523116                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5382888                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      4840650                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10223538                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124128                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       132505                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       256633                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       119397                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       128251                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247648                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12730435                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     12016219                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     24746654                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12730435                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     12016219                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     24746654                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.045388                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.057816                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.051528                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.303794                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.274211                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.289787                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060534                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.045772                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052912                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000050                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000047                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.154651                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.144989                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.149960                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.154651                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.144989                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.149960                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16037.735030                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.526677                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15301.974095                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51366.616636                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 48847.298563                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 50237.883403                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14288.062018                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13380.708326                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13882.796524                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        101635836                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       101635836                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      7044250                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      6727132                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13771382                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3751595                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      3509581                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       7261176                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116856                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       126271                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       243127                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       119516                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       128128                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247644                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10795845                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     10236713                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        21032558                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10795845                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     10236713                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       21032558                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       335526                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       413210                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       748736                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1620906                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1341470                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2962376                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7397                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6130                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        13527                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data            5                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1956432                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      1754680                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3711112                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1956432                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      1754680                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3711112                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5370959618                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6018353236                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11389312854                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  84349105443                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  64286693931                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 148635799374                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    105098996                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     82392993                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    187491989                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        26000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        65000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total        91000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  89720065061                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  70305047167                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 160025112228                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  89720065061                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  70305047167                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 160025112228                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7379776                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      7140342                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     14520118                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5372501                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      4851051                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10223552                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124253                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       132401                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       256654                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       119518                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       128133                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247651                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12752277                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     11991393                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     24743670                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12752277                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     11991393                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     24743670                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.045466                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.057870                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.051565                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.301704                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.276532                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.289760                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059532                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.046299                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052705                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000017                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000039                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000028                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.153418                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.146328                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.149982                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.153418                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.146328                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.149982                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16007.580986                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14564.877994                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15211.386729                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 52038.246168                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47922.572947                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 50174.521862                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14208.327160                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13440.945024                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13860.574333                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14041.750000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45382.265901                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40718.545899                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 43192.766864                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45382.265901                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40718.545899                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 43192.766864                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs        37128                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        22269                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs             3473                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            273                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.690469                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    81.571429                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45859.025543                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40067.161629                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 43120.528895                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45859.025543                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40067.161629                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 43120.528895                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs        36695                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        25289                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs             3463                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            288                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.596304                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    87.809028                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       608227                       # number of writebacks
-system.cpu0.dcache.writebacks::total           608227                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       146313                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       215949                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       362262                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1499850                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1213774                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      2713624                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          765                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          618                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1383                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1646163                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1429723                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3075886                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1646163                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1429723                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3075886                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       187178                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       198914                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       386092                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       135438                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       113584                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       249022                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6749                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5447                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12196                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            6                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       322616                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       312498                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       635114                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       322616                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       312498                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       635114                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2596085748                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2657791594                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5253877342                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6365986816                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5155346718                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11521333534                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     84972752                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62985504                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    147958256                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        78499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        66000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       144499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8962072564                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7813138312                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  16775210876                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8962072564                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7813138312                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16775210876                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91546998750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90791256750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182338255500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13710487847                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13068639684                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26779127531                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       155750                       # number of LoadLockedReq MSHR uncacheable cycles
-system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       155750                       # number of LoadLockedReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        96000                       # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        96000                       # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105257486597                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103859896434                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209117383031                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025475                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027721                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026585                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025161                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.023465                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024358                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.054371                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.041108                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047523                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000050                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000047                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025342                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026006                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.025665                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025342                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.026006                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.025665                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13869.609399                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.510975                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13607.837878                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47002.959406                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45387.965893                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46266.328011                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12590.421099                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11563.338351                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.703509                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       607907                       # number of writebacks
+system.cpu0.dcache.writebacks::total           607907                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       148329                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       214670                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       362999                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1486511                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1226891                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      2713402                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          703                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          661                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1364                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1634840                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1441561                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3076401                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1634840                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1441561                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3076401                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       187197                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       198540                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       385737                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       134395                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       114579                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       248974                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6694                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5469                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12163                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            5                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       321592                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       313119                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       634711                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       321592                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       313119                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       634711                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2595681199                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2634071602                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5229752801                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6377279279                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5102642760                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11479922039                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     83521753                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     63731007                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    147252760                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        55000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        77000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8972960478                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7736714362                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  16709674840                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8972960478                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7736714362                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16709674840                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91614967500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90722197000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182337164500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13706653581                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13072228739                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26778882320                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105321621081                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103794425739                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209116046820                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025366                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027805                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026566                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025015                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.023619                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024353                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.053874                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.041306                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047391                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000017                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000039                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025218                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026112                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.025651                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025218                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.026112                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.025651                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13866.040583                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13267.208633                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13557.819968                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47451.759954                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44533.839185                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46108.919160                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12477.106812                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11653.137137                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12106.615144                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12041.583333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27779.380328                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25002.202612                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26412.913077                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27779.380328                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25002.202612                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26412.913077                       # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27901.690583                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24708.543276                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26326.430202                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27901.690583                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24708.543276                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26326.430202                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                7323132                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          5902490                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           346200                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             4511574                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                3765481                       # Number of BTB hits
+system.cpu1.branchPred.lookups                7300035                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          5887077                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           345091                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             4651296                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                3771120                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            83.462690                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 676459                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             34463                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            81.076758                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 673548                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             34495                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1738,25 +1726,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    25506602                       # DTB read hits
-system.cpu1.dtb.read_misses                     36488                       # DTB read misses
-system.cpu1.dtb.write_hits                    5558527                       # DTB write hits
-system.cpu1.dtb.write_misses                     8439                       # DTB write misses
+system.cpu1.dtb.read_hits                    25450161                       # DTB read hits
+system.cpu1.dtb.read_misses                     36388                       # DTB read misses
+system.cpu1.dtb.write_hits                    5568332                       # DTB write hits
+system.cpu1.dtb.write_misses                     8538                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         510                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                679                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid                687                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    5463                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     2276                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   232                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    5495                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     2244                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   247                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      679                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                25543090                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5566966                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      710                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                25486549                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5576870                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         31065129                       # DTB hits
-system.cpu1.dtb.misses                          44927                       # DTB misses
-system.cpu1.dtb.accesses                     31110056                       # DTB accesses
+system.cpu1.dtb.hits                         31018493                       # DTB hits
+system.cpu1.dtb.misses                          44926                       # DTB misses
+system.cpu1.dtb.accesses                     31063419                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1778,294 +1766,329 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     5703436                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7020                       # ITB inst misses
+system.cpu1.itb.inst_hits                     5679651                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6870                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                         510                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                679                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid                687                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2688                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2692                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1487                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1570                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 5710456                       # ITB inst accesses
-system.cpu1.itb.hits                          5703436                       # DTB hits
-system.cpu1.itb.misses                           7020                       # DTB misses
-system.cpu1.itb.accesses                      5710456                       # DTB accesses
-system.cpu1.numCycles                       237056909                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 5686521                       # ITB inst accesses
+system.cpu1.itb.hits                          5679651                       # DTB hits
+system.cpu1.itb.misses                           6870                       # DTB misses
+system.cpu1.itb.accesses                      5686521                       # DTB accesses
+system.cpu1.numCycles                       236844574                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          14419718                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      45234990                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    7323132                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           4441940                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      9947853                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                2287798                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     84999                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles              49482147                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                1272                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             1896                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles        44871                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles      1235484                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          189                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  5701379                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               352457                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3064                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          76794959                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.726229                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.078871                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          14466322                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      45074741                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    7300035                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           4444668                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      9928510                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                2284755                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     83810                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles              49428019                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles                1085                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             1865                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles        44064                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles      1232877                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          132                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  5677454                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               353029                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3058                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          76760101                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.724873                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.076516                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                66855647     87.06%     87.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  632615      0.82%     87.88% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  843009      1.10%     88.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 1133482      1.48%     90.45% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1002056      1.30%     91.76% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  554704      0.72%     92.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 1272745      1.66%     94.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  372184      0.48%     94.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4128517      5.38%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                66839787     87.08%     87.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  628644      0.82%     87.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  837705      1.09%     88.99% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 1128430      1.47%     90.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1025116      1.34%     91.79% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  549692      0.72%     92.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 1265677      1.65%     94.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  371391      0.48%     94.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4113659      5.36%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            76794959                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.030892                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.190819                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                15530724                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             50222847                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  8895356                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               650267                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1493551                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              963840                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                85500                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              53154493                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               286161                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1493551                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                16374919                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               19306160                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      27715779                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  8656578                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              3245827                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              50687701                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  339                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                605911                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents              2002092                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents             648                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands           53113804                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            234485879                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       214384735                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             5365                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             39540919                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13572884                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            579809                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        536931                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  6499660                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             9772559                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            6360216                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           888468                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         1099515                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  47171321                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             962588                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 61070577                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            91971                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        9248404                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     23463374                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        229936                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     76794959                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.795242                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.505673                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            76760101                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.030822                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.190314                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                15575790                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             50164874                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  8875530                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               651724                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1490012                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              958602                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                85804                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              53028773                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               286820                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1490012                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                16419373                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               19259514                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      27698423                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  8639214                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              3251470                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              50560580                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  221                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                607469                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents              2007282                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents             572                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands           52946210                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            233908561                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       213841042                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             5698                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             39345682                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13600527                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            580708                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        537933                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  6505084                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             9729570                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            6369599                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           877361                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         1114434                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  47034811                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             984793                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 60942495                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            91566                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        9279731                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     23349761                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        250555                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     76760101                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.793935                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.504235                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           54534134     71.01%     71.01% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            7328500      9.54%     80.56% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            3483988      4.54%     85.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            2874889      3.74%     88.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            6131286      7.98%     96.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1377966      1.79%     98.61% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             776904      1.01%     99.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             225300      0.29%     99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              61992      0.08%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           54532875     71.04%     71.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            7326090      9.54%     80.59% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            3469207      4.52%     85.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            2884980      3.76%     88.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            6118042      7.97%     96.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1370862      1.79%     98.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             772587      1.01%     99.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             222613      0.29%     99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              62845      0.08%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       76794959                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       76760101                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  29712      0.67%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     3      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4180230     94.88%     95.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               195658      4.44%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  29035      0.66%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     5      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4177111     94.84%     95.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               198082      4.50%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass            12649      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             28971083     47.44%     47.46% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               46630      0.08%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc           875      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            26162080     42.84%     90.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            5877234      9.62%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass            13548      0.02%      0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             28887832     47.40%     47.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               46127      0.08%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                 14      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc             11      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc           887      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            26105748     42.84%     90.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            5888317      9.66%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              61070577                       # Type of FU issued
-system.cpu1.iq.rate                          0.257620                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    4405603                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.072140                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         203466895                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         57390461                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     42382296                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              11528                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              6422                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         5160                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              65457468                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   6063                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          311906                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              60942495                       # Type of FU issued
+system.cpu1.iq.rate                          0.257310                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    4404233                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.072269                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         203173539                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         57307144                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     42269826                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              12116                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              6726                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         5381                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              65326800                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   6380                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          306796                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      1999074                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         3048                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        15122                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       750838                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      1984154                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         3003                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        15089                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       749009                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads     17042744                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       332080                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads     17027364                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       331342                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1493551                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               14864582                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               222698                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           48241525                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            96453                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              9772559                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             6360216                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            687199                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 48610                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 4313                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         15122                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        168053                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       134565                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              302618                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             60042253                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             25845364                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          1028324                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1490012                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               14823463                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               222107                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           48121220                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            96425                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              9729570                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             6369599                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            709638                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 48371                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 4239                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         15089                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        167591                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       133565                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              301156                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             59912848                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             25789830                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          1029647                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       107616                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    31671376                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 5872062                       # Number of branches executed
-system.cpu1.iew.exec_stores                   5826012                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.253282                       # Inst execution rate
-system.cpu1.iew.wb_sent                      59578158                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     42387456                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 23643387                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 43005248                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       101616                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    31626536                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 5854246                       # Number of branches executed
+system.cpu1.iew.exec_stores                   5836706                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.252963                       # Inst execution rate
+system.cpu1.iew.wb_sent                      59450905                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     42275207                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 23556720                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 42880647                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.178807                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.549779                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.178493                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.549356                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        9166908                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         732652                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           262014                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     75301408                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.513681                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.486972                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        9147109                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         734238                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           260548                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     75270089                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.511960                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.483838                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     60995111     81.00%     81.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      7470337      9.92%     90.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      1928698      2.56%     93.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      1074141      1.43%     94.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       820415      1.09%     96.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       494186      0.66%     96.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       699344      0.93%     97.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       371316      0.49%     98.08% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1447860      1.92%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     60996835     81.04%     81.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      7463530      9.92%     90.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1923766      2.56%     93.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      1066165      1.42%     94.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       822611      1.09%     96.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       493470      0.66%     96.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       696092      0.92%     97.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       369554      0.49%     98.09% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1438066      1.91%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     75301408                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            30565527                       # Number of instructions committed
-system.cpu1.commit.committedOps              38680902                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     75270089                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            30381625                       # Number of instructions committed
+system.cpu1.commit.committedOps              38535309                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      13382863                       # Number of memory references committed
-system.cpu1.commit.loads                      7773485                       # Number of loads committed
-system.cpu1.commit.membars                     194338                       # Number of memory barriers committed
-system.cpu1.commit.branches                   5145142                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5126                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 34406663                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              483721                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events              1447860                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                      13366006                       # Number of memory references committed
+system.cpu1.commit.loads                      7745416                       # Number of loads committed
+system.cpu1.commit.membars                     193947                       # Number of memory barriers committed
+system.cpu1.commit.branches                   5114433                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5338                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 34292499                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              482077                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        25125071     65.20%     65.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          43345      0.11%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc          887      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        7745416     20.10%     85.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       5620590     14.59%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::total         38535309                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1438066                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   120827478                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   97232532                       # The number of ROB writes
-system.cpu1.timesIdled                         865086                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                      160261950                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  2316983227                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   30492768                       # Number of Instructions Simulated
-system.cpu1.committedOps                     38608143                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             30492768                       # Number of Instructions Simulated
-system.cpu1.cpi                              7.774201                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        7.774201                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.128631                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.128631                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               272500909                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               43779735                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    45015                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   42294                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads              133085319                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                592959                       # number of misc regfile writes
+system.cpu1.rob.rob_reads                   120626402                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   96898257                       # The number of ROB writes
+system.cpu1.timesIdled                         866184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                      160084473                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  2317121408                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   30313431                       # Number of Instructions Simulated
+system.cpu1.committedOps                     38467115                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             30313431                       # Number of Instructions Simulated
+system.cpu1.cpi                              7.813189                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        7.813189                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.127989                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.127989                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               271901021                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               43646883                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    45279                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   42402                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads              133121444                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                593543                       # number of misc regfile writes
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
@@ -2082,17 +2105,17 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736889440801                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1736889440801                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736889440801                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1736889440801                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734475259291                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1734475259291                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734475259291                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1734475259291                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   83061                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   83062                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index 094868576..cce768d16 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -1,147 +1,159 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.629695                       # Number of seconds simulated
-sim_ticks                                2629694709500                       # Number of ticks simulated
-final_tick                               2629694709500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.631271                       # Number of seconds simulated
+sim_ticks                                2631271319500                       # Number of ticks simulated
+final_tick                               2631271319500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 422902                       # Simulator instruction rate (inst/s)
-host_op_rate                                   538135                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18468797106                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 466428                       # Number of bytes of host memory used
-host_seconds                                   142.39                       # Real time elapsed on the host
-sim_insts                                    60215255                       # Number of instructions simulated
-sim_ops                                      76622777                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 354699                       # Simulator instruction rate (inst/s)
+host_op_rate                                   451347                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15499898557                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 465856                       # Number of bytes of host memory used
+host_seconds                                   169.76                       # Real time elapsed on the host
+sim_insts                                    60213853                       # Number of instructions simulated
+sim_ops                                      76620850                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd    124256256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           291720                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4684888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           299528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4518680                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           412356                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4375828                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            134021240                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       291720                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       412356                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          704076                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3689664                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1522876                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1493404                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6705944                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst           404800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4542464                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            134021920                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       299528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       404800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          704328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3690624                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1524152                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1491920                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6706696                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15532032                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10770                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73237                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10892                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             70640                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6459                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             68407                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15690908                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57651                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           380719                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           373351                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811721                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47251210                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst              6325                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             70976                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15690868                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57666                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           381038                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           372980                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811684                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47222898                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              110933                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1781533                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              113834                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1717299                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            24                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              156808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1664006                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50964562                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         110933                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         156808                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             267741                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1403077                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             579108                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             567900                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2550085                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1403077                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47251210                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              153842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1726338                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50934284                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         113834                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         153842                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             267676                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1402601                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             579245                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             566996                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2548842                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1402601                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47222898                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             110933                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            2360641                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             113834                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            2296545                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             156808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2231906                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53514647                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15690908                       # Number of read requests accepted
-system.physmem.writeReqs                       811721                       # Number of write requests accepted
-system.physmem.readBursts                    15690908                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     811721                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM               1004216192                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      1920                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6737024                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 134021240                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6705944                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       30                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706455                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::cpu1.inst             153842                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2293334                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53483126                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15690868                       # Number of read requests accepted
+system.physmem.writeReqs                       811684                       # Number of write requests accepted
+system.physmem.readBursts                    15690868                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     811684                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM               1004214848                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       704                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6724608                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 134021920                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6706696                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       11                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706598                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs           4517                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0              980391                       # Per bank write bursts
 system.physmem.perBankRdBursts::1              980206                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              980218                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              980431                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              980222                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              980428                       # Per bank write bursts
 system.physmem.perBankRdBursts::4              986950                       # Per bank write bursts
 system.physmem.perBankRdBursts::5              980708                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              980610                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              980421                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              980611                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              980420                       # Per bank write bursts
 system.physmem.perBankRdBursts::8              980615                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              980431                       # Per bank write bursts
 system.physmem.perBankRdBursts::10             979815                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             979558                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             980154                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             980093                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             980167                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             979544                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             980153                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             980076                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             980177                       # Per bank write bursts
 system.physmem.perBankRdBursts::15             980110                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6645                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6506                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6513                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6561                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6643                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6949                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6933                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6786                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                6904                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6725                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6221                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6029                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6513                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6297                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6626                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6496                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6497                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6558                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6634                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6937                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6920                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6772                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6893                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6718                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6212                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6014                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6499                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6274                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               6516                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6525                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6506                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2629690290000                       # Total gap between requests
+system.physmem.totGap                    2631266900000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                    6718                       # Read request sizes (log2)
+system.physmem.readPktSize::2                    6664                       # Read request sizes (log2)
 system.physmem.readPktSize::3                15532032                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  152158                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  152172                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                 754070                       # Write request sizes (log2)
+system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  57651                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1128915                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    971082                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    971066                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    973046                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    971647                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    972454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2865167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2865325                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3808659                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     25323                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    23577                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    23920                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    23318                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    22983                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    22230                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    22150                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       16                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  57666                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1139961                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    982153                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    987606                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1093203                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    997403                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1062031                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2774379                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2684271                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3510460                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    111897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   101929                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    96137                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    92760                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19230                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18784                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18633                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       20                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -157,60 +169,60 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       352                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                       346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       344                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       342                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       342                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       339                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                       339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       328                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       337                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       334                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       329                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      323                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      318                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                      316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2695                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4449                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4320                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      313                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     4037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5848                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5837                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5822                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5807                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5788                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5755                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5749                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5727                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5704                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5659                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5646                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
@@ -221,373 +233,350 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       990183                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     1014.719065                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1002.794597                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev      86.877825                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           3622      0.37%      0.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         3291      0.33%      0.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1715      0.17%      0.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1178      0.12%      0.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          920      0.09%      1.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          703      0.07%      1.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          532      0.05%      1.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          420      0.04%      1.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       977802     98.75%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         990183                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4537                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      3458.425832                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    54557.622307                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535          4511     99.43%     99.43% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::131072-196607            8      0.18%     99.60% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143            4      0.09%     99.69% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::393216-458751            2      0.04%     99.74% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::589824-655359            3      0.07%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.82% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            6      0.13%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1040545                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      971.548041                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     905.383017                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     204.411888                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22983      2.21%      2.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22832      2.19%      4.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9281      0.89%      5.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2277      0.22%      5.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2320      0.22%      5.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1623      0.16%      5.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9470      0.91%      6.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          703      0.07%      6.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       969056     93.13%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1040545                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6005                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2612.962531                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    47489.703553                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          5977     99.53%     99.53% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::131072-196607           11      0.18%     99.72% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143            3      0.05%     99.77% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::393216-458751            2      0.03%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::589824-655359            3      0.05%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.87% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            6      0.10%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4537                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4537                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.201675                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       21.361663                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        9.873768                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1                   5      0.11%      0.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2                   7      0.15%      0.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3                   5      0.11%      0.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4                   2      0.04%      0.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5                   2      0.04%      0.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6                   4      0.09%      0.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7                   6      0.13%      0.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8                   3      0.07%      0.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9                   3      0.07%      0.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10                  3      0.07%      0.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::11                  3      0.07%      0.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12                  2      0.04%      0.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13                  4      0.09%      1.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14                  7      0.15%      1.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15                 17      0.37%      1.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               1491     32.86%     34.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                339      7.47%     41.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                208      4.58%     46.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1050     23.14%     69.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 16      0.35%     70.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 12      0.26%     70.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 20      0.44%     70.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 24      0.53%     71.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 18      0.40%     71.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 14      0.31%     71.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 18      0.40%     72.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 18      0.40%     72.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 19      0.42%     73.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 13      0.29%     73.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                 11      0.24%     73.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 12      0.26%     73.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                 11      0.24%     74.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  3      0.07%     74.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  2      0.04%     74.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.02%     74.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39               1015     22.37%     96.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                 76      1.68%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                 13      0.29%     98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                 42      0.93%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  5      0.11%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  5      0.11%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  5      0.11%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4537                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   592300556750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              700300341750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  78454390000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 29545395000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       37748.08                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1882.97                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            6005                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6005                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.497419                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.315574                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.169730                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1                   7      0.12%      0.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   6      0.10%      0.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   6      0.10%      0.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   4      0.07%      0.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   3      0.05%      0.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6                   1      0.02%      0.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7                   3      0.05%      0.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8                   3      0.05%      0.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9                   4      0.07%      0.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10                  3      0.05%      0.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11                  4      0.07%      0.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12                  8      0.13%      0.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13                  3      0.05%      0.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14                  4      0.07%      0.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                 16      0.27%      1.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               1890     31.47%     32.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 59      0.98%     33.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3765     62.70%     96.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 21      0.35%     96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 14      0.23%     96.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 16      0.27%     97.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 19      0.32%     97.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 20      0.33%     97.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 12      0.20%     98.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  6      0.10%     98.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 23      0.38%     98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 21      0.35%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 18      0.30%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 14      0.23%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                 10      0.17%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 11      0.18%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                 11      0.18%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6005                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   402822623250                       # Total ticks spent queuing
+system.physmem.totMemAccLat              697026192000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  78454285000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25672.44                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44631.05                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         381.88                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44422.44                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         381.65                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.56                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       50.96                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       50.93                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.55                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         7.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        14.89                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14676487                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89750                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.54                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.26                       # Row buffer hit rate for writes
-system.physmem.avgGap                       159349.78                       # Average gap between requests
-system.physmem.pageHitRate                      93.48                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.16                       # Percentage of time for which DRAM has all the banks in precharge state
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54426652                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16743677                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16743677                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763441                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763441                       # Transaction distribution
-system.membus.trans_dist::Writeback             57651                       # Transaction distribution
+system.physmem.avgRdQLen                         6.85                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        14.68                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14667283                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     88101                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  83.84                       # Row buffer hit rate for writes
+system.physmem.avgGap                       159446.06                       # Average gap between requests
+system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2257272287500                       # Time in different power states
+system.physmem.memoryStateTime::REF       87863880000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      286133845000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     54394584                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16743630                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16743630                       # Transaction distribution
+system.membus.trans_dist::WriteReq             763389                       # Transaction distribution
+system.membus.trans_dist::WriteResp            763389                       # Transaction distribution
+system.membus.trans_dist::Writeback             57666                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4517                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4517                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131342                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131342                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131349                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131349                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383092                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3860                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1892577                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4279541                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1892408                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4279372                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     31064064                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     31064064                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               35343605                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               35343436                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390550                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7720                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16470928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     18869222                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16472360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     18870654                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    124256256                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           143125478                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              143125478                       # Total data (bytes)
+system.membus.tot_pkt_size::total           143126910                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              143126910                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1225762000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1225776000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3755500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3753500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         18171181500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         18171055500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4987933108                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4987830629                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        38819144750                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        38455776750                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    62041                       # number of replacements
-system.l2c.tags.tagsinuse                51600.507824                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1699332                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   127423                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.336148                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             2574803290500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   38204.625202                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000702                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2677.995545                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3048.557344                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.000187                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4342.999627                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3326.329216                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.582956                       # Average percentage of cache occupancy
+system.l2c.tags.replacements                    62060                       # number of replacements
+system.l2c.tags.tagsinuse                51620.522057                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1699511                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   127448                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    13.334937                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle             2576403565500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   38224.293292                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000700                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2572.111888                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3079.413643                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.000186                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4449.101058                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3295.601290                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.583256                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.040863                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.046517                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.039247                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.046988                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.066269                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.050756                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.787361                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65382                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2132                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6447                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        56751                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.997650                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 17277037                       # Number of tag accesses
-system.l2c.tags.data_accesses                17277037                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         9996                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         3617                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             411271                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             183421                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         9883                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         3502                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             433200                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             187065                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1241955                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          596489                       # number of Writeback hits
-system.l2c.Writeback_hits::total               596489                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              12                       # number of UpgradeReq hits
+system.l2c.tags.occ_percent::cpu1.inst       0.067888                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.050287                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.787667                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65388                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2135                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6611                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        56587                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997742                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 17278044                       # Number of tag accesses
+system.l2c.tags.data_accesses                17278044                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        10108                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         3664                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             418356                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             187332                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         9807                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         3568                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             426125                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             183124                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1242084                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          596476                       # number of Writeback hits
+system.l2c.Writeback_hits::total               596476                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              15                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              11                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            55903                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            58636                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               114539                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          9996                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          3617                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              411271                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              239324                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          9883                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          3502                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              433200                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              245701                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1356494                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         9996                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         3617                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             411271                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             239324                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         9883                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         3502                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             433200                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             245701                       # number of overall hits
-system.l2c.overall_hits::total                1356494                       # number of overall hits
+system.l2c.ReadExReq_hits::cpu0.data            57771                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            56762                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               114533                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         10108                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          3664                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              418356                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              245103                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          9807                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          3568                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              426125                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              239886                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1356617                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        10108                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         3664                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             418356                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             245103                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         9807                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         3568                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             426125                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             239886                       # number of overall hits
+system.l2c.overall_hits::total                1356617                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             4144                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             5204                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             4266                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             5262                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             6442                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             5023                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20816                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1406                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1477                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2883                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          68791                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          64185                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             132976                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu1.inst             6325                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             4967                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                20823                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1468                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1421                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2889                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          66168                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          66809                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             132977                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              4144                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             73995                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              4266                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             71430                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              6442                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             69208                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153792                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              6325                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             71776                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                153800                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             4144                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            73995                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             4266                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            71430                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             6442                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            69208                       # number of overall misses
-system.l2c.overall_misses::total               153792                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             6325                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            71776                       # number of overall misses
+system.l2c.overall_misses::total               153800                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    292011000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    389009500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    299478000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    388418000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        89250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    455480250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    379549000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1516288500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data       256489                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       208991                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       465480                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   4825847704                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4517645162                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9343492866                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    441554500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    374768000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1504457250                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data       209991                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       255989                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       465980                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   4604837922                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4645007200                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   9249845122                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    292011000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   5214857204                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    299478000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   4993255922                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.dtb.walker        89250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    455480250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   4897194162                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     10859781366                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    441554500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   5019775200                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     10754302372                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    292011000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   5214857204                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    299478000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   4993255922                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker        89250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    455480250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   4897194162                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    10859781366                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         9996                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         3619                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         415415                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         188625                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         9884                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         3502                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         439642                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         192088                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1262771                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       596489                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           596489                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1420                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1489                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2909                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       124694                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       122821                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247515                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         9996                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         3619                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          415415                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          313319                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         9884                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         3502                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          439642                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          314909                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1510286                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         9996                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         3619                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         415415                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         313319                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         9884                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         3502                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         439642                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         314909                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1510286                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000553                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.009976                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.027589                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000101                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.014653                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.026149                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016484                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990141                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991941                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.991062                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.551679                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.522590                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.537244                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000553                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.009976                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.236165                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000101                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.014653                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.219771                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.101830                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000553                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.009976                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.236165                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000101                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.014653                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.219771                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.101830                       # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu1.inst    441554500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   5019775200                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    10754302372                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        10108                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         3666                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         422622                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         192594                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         9808                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         3568                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         432450                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         188091                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1262907                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       596476                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           596476                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1483                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1432                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2915                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       123939                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       123571                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247510                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        10108                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         3666                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          422622                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          316533                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         9808                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         3568                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          432450                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          311662                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1510417                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        10108                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         3666                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         422622                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         316533                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         9808                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         3568                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         432450                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         311662                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1510417                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000546                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.010094                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.027322                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000102                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.014626                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.026407                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016488                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989885                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992318                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991081                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.533876                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.540653                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.537259                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000546                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.010094                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.225664                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000102                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.014626                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.230301                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.101826                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000546                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.010094                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.225664                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000102                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.014626                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.230301                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.101826                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70465.974903                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 74752.017679                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70201.125176                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 73815.659445                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        89250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70704.788885                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 75562.213816                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 72842.452921                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   182.424609                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   141.496953                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   161.456816                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70152.312134                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70384.749739                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 70264.505369                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69810.988142                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 75451.580431                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 72249.783893                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   143.045640                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   180.147080                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   161.294566                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69593.125408                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69526.668563                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 69559.736812                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 70465.974903                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 70475.805176                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 70201.125176                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 69904.184824                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        89250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 70704.788885                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 70760.521356                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 70613.434808                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 69810.988142                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 69936.680785                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 69923.942601                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 70465.974903                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 70475.805176                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 70201.125176                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 69904.184824                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        89250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 70704.788885                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 70760.521356                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 70613.434808                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 69810.988142                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 69936.680785                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 69923.942601                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -596,132 +585,129 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57651                       # number of writebacks
-system.l2c.writebacks::total                    57651                       # number of writebacks
+system.l2c.writebacks::writebacks               57666                       # number of writebacks
+system.l2c.writebacks::total                    57666                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         4144                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         5204                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         4266                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         5262                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         6442                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         5023                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           20816                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1406                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1477                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2883                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        68791                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        64185                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        132976                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         6325                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         4967                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           20823                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         1468                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1421                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2889                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        66168                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        66809                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        132977                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         4144                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        73995                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         4266                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        71430                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         6442                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        69208                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           153792                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         6325                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        71776                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           153800                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         4144                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        73995                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         4266                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        71430                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         6442                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        69208                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          153792                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         6325                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        71776                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          153800                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    239540000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    324214500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    245455500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    322888500                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    373802250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    316907500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1254665500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     14061406                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     14772477                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     28833883                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3946484796                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3696331838                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   7642816634                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    361377500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    312814000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1242736750                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     14681468                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     14215421                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     28896889                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3759009578                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3789807300                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   7548816878                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    239540000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   4270699296                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    245455500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4081898078                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    373802250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   4013239338                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   8897482134                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    361377500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   4102621300                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   8791553628                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    239540000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   4270699296                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    245455500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4081898078                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    373802250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   4013239338                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   8897482134                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    351469750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  82683235750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst       856250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  84002858250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167038420000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8408462374                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8295509001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  16703971375                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    351469750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  91091698124                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst       856250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  92298367251                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 183742391375                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000553                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.009976                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.027589                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000101                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014653                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.026149                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016484                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.990141                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991941                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.991062                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.551679                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.522590                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.537244                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000553                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009976                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.236165                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000101                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014653                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.219771                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.101830                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000553                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009976                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.236165                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000101                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014653                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.219771                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.101830                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu1.inst    361377500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   4102621300                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   8791553628                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    349718500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83155205750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83528725500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167033649750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8440426101                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8262522003                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  16702948104                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    349718500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  91595631851                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91791247503                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183736597854                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000546                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.010094                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.027322                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000102                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014626                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.026407                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016488                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.989885                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.992318                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991081                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.533876                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.540653                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.537259                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000546                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010094                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.225664                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000102                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014626                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.230301                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.101826                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000546                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010094                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.225664                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000102                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014626                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.230301                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.101826                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57804.054054                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62301.018447                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57537.623066                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61362.314709                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58025.807203                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63091.280111                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 60274.092045                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57134.782609                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62978.457822                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 59680.965759                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.677048                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.346861                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57369.202308                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57588.717582                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 57475.158179                       # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.814919                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.384562                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56810.083092                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56725.999491                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56767.838634                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57804.054054                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57716.052382                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57537.623066                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57145.430183                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58025.807203                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57988.084297                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 57853.998478                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57134.782609                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57158.678388                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57162.247256                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57804.054054                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57716.052382                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57537.623066                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57145.430183                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58025.807203                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57988.084297                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57853.998478                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57134.782609                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57158.678388                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57162.247256                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -729,7 +715,6 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
@@ -739,39 +724,39 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    52790847                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2471761                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2471761                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            763441                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           763441                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           596489                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2909                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2909                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           247515                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          247515                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1725013                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5754007                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20046                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        50514                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7549580                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54750240                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     83796742                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28484                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        79520                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          138654986                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             138654986                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          168824                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4808734000                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    52759012                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2471877                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2471877                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            763389                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           763389                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           596476                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2915                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2915                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           247510                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          247510                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1725028                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5753762                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20291                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        50582                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7549663                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54751132                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     83793442                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28936                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        79664                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          138653174                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             138653174                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          170100                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4808682000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3865148750                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        3865303000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4420266392                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4420412121                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          12925000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          13057000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          30634250                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          30666250                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      48160270                       # Throughput (bytes/s)
+system.iobus.throughput                      48131413                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq             16715394                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            16715394                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8184                       # Transaction distribution
@@ -881,7 +866,7 @@ system.iobus.reqLayer25.occupancy         15532032000                       # La
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374908000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         38823243250                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         39139813250                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -906,25 +891,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7344844                       # DTB read hits
-system.cpu0.dtb.read_misses                      6860                       # DTB read misses
-system.cpu0.dtb.write_hits                    5551128                       # DTB write hits
-system.cpu0.dtb.write_misses                     1832                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        2493                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                     7447963                       # DTB read hits
+system.cpu0.dtb.read_misses                      7119                       # DTB read misses
+system.cpu0.dtb.write_hits                    5549645                       # DTB write hits
+system.cpu0.dtb.write_misses                     1815                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        2495                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                699                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    6351                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid                725                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     29                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    6552                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   137                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   134                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      220                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7351704                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5552960                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      230                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 7455082                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5551460                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         12895972                       # DTB hits
-system.cpu0.dtb.misses                           8692                       # DTB misses
-system.cpu0.dtb.accesses                     12904664                       # DTB accesses
+system.cpu0.dtb.hits                         12997608                       # DTB hits
+system.cpu0.dtb.misses                           8934                       # DTB misses
+system.cpu0.dtb.accesses                     13006542                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -946,125 +931,160 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    30211154                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3603                       # ITB inst misses
+system.cpu0.itb.inst_hits                    30500446                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3756                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        2493                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        2495                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                699                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2758                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid                725                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     29                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2854                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                30214757                       # ITB inst accesses
-system.cpu0.itb.hits                         30211154                       # DTB hits
-system.cpu0.itb.misses                           3603                       # DTB misses
-system.cpu0.itb.accesses                     30214757                       # DTB accesses
-system.cpu0.numCycles                      2627736532                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                30504202                       # ITB inst accesses
+system.cpu0.itb.hits                         30500446                       # DTB hits
+system.cpu0.itb.misses                           3756                       # DTB misses
+system.cpu0.itb.accesses                     30504202                       # DTB accesses
+system.cpu0.numCycles                      2629256644                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   29624937                       # Number of instructions committed
-system.cpu0.committedOps                     37728426                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             34074958                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4583                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1045164                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      3935196                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    34074958                       # number of integer instructions
-system.cpu0.num_fp_insts                         4583                       # number of float instructions
-system.cpu0.num_int_register_reads          197582111                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          36713164                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3288                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1298                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     13470170                       # number of memory refs
-system.cpu0.num_load_insts                    7667939                       # Number of load instructions
-system.cpu0.num_store_insts                   5802231                       # Number of store instructions
-system.cpu0.num_idle_cycles              2282002616.045546                       # Number of idle cycles
-system.cpu0.num_busy_cycles              345733915.954454                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.131571                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.868429                       # Percentage of idle cycles
-system.cpu0.Branches                          5074688                       # Number of branches fetched
+system.cpu0.committedInsts                   29876886                       # Number of instructions committed
+system.cpu0.committedOps                     37981807                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             34283991                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4842                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1058651                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3976280                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    34283991                       # number of integer instructions
+system.cpu0.num_fp_insts                         4842                       # number of float instructions
+system.cpu0.num_int_register_reads          198984803                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          36984019                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3491                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1354                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     13572889                       # number of memory refs
+system.cpu0.num_load_insts                    7771976                       # Number of load instructions
+system.cpu0.num_store_insts                   5800913                       # Number of store instructions
+system.cpu0.num_idle_cycles              2280913483.245505                       # Number of idle cycles
+system.cpu0.num_busy_cycles              348343160.754495                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.132487                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.867513                       # Percentage of idle cycles
+system.cpu0.Branches                          5129174                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                12846      0.03%      0.03% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 24984996     64.70%     64.73% # Class of executed instruction
+system.cpu0.op_class::IntMult                   44336      0.11%     64.85% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc               930      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.85% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7771976     20.13%     84.98% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5800913     15.02%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                  38615997                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   83029                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           856147                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.849495                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           60652706                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           856659                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            70.801458                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      20216402250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   158.742483                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   352.107012                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.310044                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.687709                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997753                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   83028                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements           856182                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.863139                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           60651276                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           856694                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            70.796896                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      20196898250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   155.776297                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   355.086842                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.304251                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.693529                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997780                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          266                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         62366026                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        62366026                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29795008                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     30857698                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       60652706                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29795008                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     30857698                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        60652706                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29795008                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     30857698                       # number of overall hits
-system.cpu0.icache.overall_hits::total       60652706                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       416146                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       440514                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       856660                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       416146                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       440514                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        856660                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       416146                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       440514                       # number of overall misses
-system.cpu0.icache.overall_misses::total       856660                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5672028500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6130116250                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  11802144750                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   5672028500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   6130116250                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  11802144750                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   5672028500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   6130116250                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  11802144750                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     30211154                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     31298212                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     61509366                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     30211154                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     31298212                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     61509366                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     30211154                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     31298212                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     61509366                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013775                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014075                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.013927                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013775                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014075                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.013927                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013775                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014075                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.013927                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13629.900323                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13915.826171                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.929879                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13629.900323                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13915.826171                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13776.929879                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13629.900323                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13915.826171                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13776.929879                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         62364664                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        62364664                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     30077042                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     30574234                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       60651276                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     30077042                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     30574234                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        60651276                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     30077042                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     30574234                       # number of overall hits
+system.cpu0.icache.overall_hits::total       60651276                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       423404                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       433290                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       856694                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       423404                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       433290                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        856694                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       423404                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       433290                       # number of overall misses
+system.cpu0.icache.overall_misses::total       856694                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5772656000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6023287000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  11795943000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   5772656000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   6023287000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  11795943000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   5772656000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   6023287000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  11795943000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     30500446                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     31007524                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     61507970                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     30500446                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     31007524                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     61507970                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     30500446                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     31007524                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     61507970                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013882                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.013974                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.013928                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013882                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.013974                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.013928                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013882                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.013974                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.013928                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13633.919377                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13901.283205                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13769.143942                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13633.919377                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13901.283205                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13769.143942                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13633.919377                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13901.283205                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13769.143942                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1073,169 +1093,165 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       416146                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       440514                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       856660                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       416146                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       440514                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       856660                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       416146                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       440514                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       856660                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4838197500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5246649750                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10084847250                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4838197500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5246649750                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10084847250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4838197500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5246649750                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10084847250                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    442799750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      1085250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    443885000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    442799750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst      1085250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    443885000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013775                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014075                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013927                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013775                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014075                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.013927                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013775                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014075                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.013927                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11626.202102                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11910.290592                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11772.286847                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11626.202102                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11910.290592                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11772.286847                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11626.202102                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11910.290592                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11772.286847                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       423404                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       433290                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       856694                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       423404                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       433290                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       856694                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       423404                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       433290                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       856694                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4924249000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5154307000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10078556000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4924249000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5154307000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10078556000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4924249000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5154307000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10078556000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    441046000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    441046000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    441046000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    441046000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013882                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013974                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013928                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013882                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.013974                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.013928                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013882                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.013974                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.013928                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11630.142842                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.744190                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11764.475997                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11630.142842                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.744190                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11764.475997                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11630.142842                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.744190                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11764.475997                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           627716                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.875867                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           23661613                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           628228                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            37.664053                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        671680250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   152.516115                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   359.359751                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.297883                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.701875                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           627683                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.876343                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           23661001                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           628195                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            37.665058                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        669376250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   147.481748                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   364.394596                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.288050                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.711708                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999758                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          331                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          109                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         97787592                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        97787592                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6450546                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      6749057                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13199603                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4919460                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      5055668                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       9975128                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       118398                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       117802                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       236200                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       124425                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       123348                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247773                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11370006                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     11804725                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        23174731                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11370006                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     11804725                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       23174731                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       182595                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       186544                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       369139                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       126114                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       124310                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       250424                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6030                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5544                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        11574                       # number of LoadLockedReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       308709                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       310854                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        619563                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       308709                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       310854                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       619563                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2721600000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2760360750                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5481960750                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5821979202                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   5534732315                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  11356711517                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     81055000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     79345250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    160400250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8543579202                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   8295093065                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  16838672267                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8543579202                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   8295093065                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  16838672267                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6633141                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      6935601                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13568742                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5045574                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      5179978                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10225552                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124428                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       123346                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       247774                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       124425                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       123348                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247773                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     11678715                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     12115579                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     23794294                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11678715                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     12115579                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     23794294                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027528                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.026897                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.027205                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.024995                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.023998                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.024490                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048462                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044947                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046712                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026433                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025657                       # miss rate for demand accesses
+system.cpu0.dcache.tags.tag_accesses         97784979                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        97784979                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6545596                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      6653610                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13199206                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4917377                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      5057557                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       9974934                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       119123                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       117066                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       236189                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       125242                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       122515                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247757                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11462973                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     11711167                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        23174140                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11462973                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     11711167                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       23174140                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       186473                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       182643                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       369116                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       125422                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       125003                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       250425                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6121                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5448                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11569                       # number of LoadLockedReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       311895                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       307646                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        619541                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       311895                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       307646                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       619541                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2771059250                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2705059750                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5476119000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5617953546                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   5645844221                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  11263797767                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     82277250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     78257750                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    160535000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8389012796                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   8350903971                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  16739916767                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8389012796                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   8350903971                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  16739916767                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6732069                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      6836253                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13568322                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5042799                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      5182560                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10225359                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       125244                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       122514                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       247758                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       125242                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       122515                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247757                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11774868                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     12018813                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     23793681                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11774868                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     12018813                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     23793681                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027699                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.026717                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.027204                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.024872                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.024120                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.024491                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048873                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044468                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046695                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026488                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025597                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.026038                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026433                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.025657                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026488                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.025597                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     0.026038                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14905.117884                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14797.370862                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.668041                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46164.416338                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44523.628952                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 45349.932582                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.956882                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.913781                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13858.670295                       # average LoadLockedReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27675.186671                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26684.852262                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 27178.305139                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27675.186671                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26684.852262                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 27178.305139                       # average overall miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14860.377910                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14810.640156                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14835.767076                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44792.409195                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45165.669792                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44978.727232                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.798726                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14364.491557                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13876.307373                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26896.913371                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27144.523156                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 27019.869173                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26896.913371                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27144.523156                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 27019.869173                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1244,77 +1260,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       596489                       # number of writebacks
-system.cpu0.dcache.writebacks::total           596489                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       182595                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       186544                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       369139                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       126114                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       124310                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       250424                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6030                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5544                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11574                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       308709                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       310854                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       619563                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       308709                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       310854                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       619563                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2355168000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2386207250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4741375250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5543852798                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5262622685                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10806475483                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     68990000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     68208750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137198750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7899020798                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7648829935                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  15547850733                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7899020798                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7648829935                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  15547850733                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  90318421750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  91762441000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080862750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13218125626                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13022508499                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26240634125                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103536547376                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104784949499                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208321496875                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.027528                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026897                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.027205                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.024995                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.023998                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024490                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.048462                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.044947                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046712                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026433                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025657                       # mshr miss rate for demand accesses
+system.cpu0.dcache.writebacks::writebacks       596476                       # number of writebacks
+system.cpu0.dcache.writebacks::total           596476                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       186473                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       182643                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       369116                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       125422                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       125003                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       250425                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6121                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5448                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11569                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       311895                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       307646                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       619541                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       311895                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       307646                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       619541                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2396807750                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2338699250                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4735507000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5342161454                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5370757779                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10712919233                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     70030750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     67311250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137342000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7738969204                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7709457029                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  15448426233                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7738969204                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7709457029                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  15448426233                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  90834275250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  91243928750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078204000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13255943399                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  12983118997                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26239062396                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104090218649                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104227047747                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317266396                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.027699                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026717                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.027204                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.024872                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024120                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024491                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.048873                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.044468                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046695                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026488                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025597                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::total     0.026038                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026433                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025657                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026488                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025597                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total     0.026038                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12898.315945                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12791.659072                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12844.417008                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43959.059248                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42334.668852                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43152.714927                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.127695                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12303.165584                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.047866                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25587.270854                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24605.859777                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25094.866435                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25587.270854                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24605.859777                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25094.866435                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12853.376896                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12804.757094                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12829.319238                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42593.495990                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42965.031071                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42778.952712                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.063552                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12355.222100                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11871.553289                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24812.738915                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25059.506800                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24935.276653                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24812.738915                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25059.506800                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24935.276653                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1348,25 +1364,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     7655819                       # DTB read hits
-system.cpu1.dtb.read_misses                      7243                       # DTB read misses
-system.cpu1.dtb.write_hits                    5681899                       # DTB write hits
-system.cpu1.dtb.write_misses                     1828                       # DTB write misses
+system.cpu1.dtb.read_hits                     7552227                       # DTB read hits
+system.cpu1.dtb.read_misses                      6971                       # DTB read misses
+system.cpu1.dtb.write_hits                    5683121                       # DTB write hits
+system.cpu1.dtb.write_misses                     1859                       # DTB write misses
 system.cpu1.dtb.flush_tlb                        2493                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                740                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    6711                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid                714                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     34                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    6603                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   143                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   141                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      232                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 7663062                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5683727                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      222                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 7559198                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5684980                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         13337718                       # DTB hits
-system.cpu1.dtb.misses                           9071                       # DTB misses
-system.cpu1.dtb.accesses                     13346789                       # DTB accesses
+system.cpu1.dtb.hits                         13235348                       # DTB hits
+system.cpu1.dtb.misses                           8830                       # DTB misses
+system.cpu1.dtb.accesses                     13244178                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1388,50 +1404,85 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    31298229                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3696                       # ITB inst misses
+system.cpu1.itb.inst_hits                    31007524                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3606                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                        2493                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                740                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2898                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid                714                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     34                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    2820                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                31301925                       # ITB inst accesses
-system.cpu1.itb.hits                         31298229                       # DTB hits
-system.cpu1.itb.misses                           3696                       # DTB misses
-system.cpu1.itb.accesses                     31301925                       # DTB accesses
-system.cpu1.numCycles                      2631652887                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                31011130                       # ITB inst accesses
+system.cpu1.itb.hits                         31007524                       # DTB hits
+system.cpu1.itb.misses                           3606                       # DTB misses
+system.cpu1.itb.accesses                     31011130                       # DTB accesses
+system.cpu1.numCycles                      2633285995                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   30590318                       # Number of instructions committed
-system.cpu1.committedOps                     38894351                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             35148183                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5686                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1095318                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      4014750                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    35148183                       # number of integer instructions
-system.cpu1.num_fp_insts                         5686                       # number of float instructions
-system.cpu1.num_int_register_reads          203876321                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          37823170                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                4205                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1482                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     13931138                       # number of memory refs
-system.cpu1.num_load_insts                    7996929                       # Number of load instructions
-system.cpu1.num_store_insts                   5934209                       # Number of store instructions
-system.cpu1.num_idle_cycles              2293790821.520695                       # Number of idle cycles
-system.cpu1.num_busy_cycles              337862065.479305                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.128384                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.871616                       # Percentage of idle cycles
-system.cpu1.Branches                          5235663                       # Number of branches fetched
+system.cpu1.committedInsts                   30336967                       # Number of instructions committed
+system.cpu1.committedOps                     38639043                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             34937438                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5427                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1081754                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3973481                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    34937438                       # number of integer instructions
+system.cpu1.num_fp_insts                         5427                       # number of float instructions
+system.cpu1.num_int_register_reads          202463130                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          37550545                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4002                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1426                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                     13827657                       # number of memory refs
+system.cpu1.num_load_insts                    7892397                       # Number of load instructions
+system.cpu1.num_store_insts                   5935260                       # Number of store instructions
+system.cpu1.num_idle_cycles              2291893093.755996                       # Number of idle cycles
+system.cpu1.num_busy_cycles              341392901.244004                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.129645                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.870355                       # Percentage of idle cycles
+system.cpu1.Branches                          5180924                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                15672      0.04%      0.04% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 25411566     64.66%     64.70% # Class of executed instruction
+system.cpu1.op_class::IntMult                   43588      0.11%     64.81% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              1181      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::MemRead                 7892397     20.08%     84.90% # Class of executed instruction
+system.cpu1.op_class::MemWrite                5935260     15.10%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                  39299664                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.iocache.tags.replacements                    0                       # number of replacements
@@ -1450,10 +1501,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1783080197250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1783080197250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1783080197250                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1783080197250                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779915025250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1779915025250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779915025250                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1779915025250                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 6ae80aee8..e98e38022 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,135 +1,135 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.137972                       # Number of seconds simulated
-sim_ticks                                5137971999000                       # Number of ticks simulated
-final_tick                               5137971999000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.141960                       # Number of seconds simulated
+sim_ticks                                5141959613000                       # Number of ticks simulated
+final_tick                               5141959613000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 151274                       # Simulator instruction rate (inst/s)
-host_op_rate                                   299020                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1905679647                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 770140                       # Number of bytes of host memory used
-host_seconds                                  2696.14                       # Real time elapsed on the host
-sim_insts                                   407854776                       # Number of instructions simulated
-sim_ops                                     806198141                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 152486                       # Simulator instruction rate (inst/s)
+host_op_rate                                   301416                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1922658876                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 770128                       # Number of bytes of host memory used
+host_seconds                                  2674.40                       # Real time elapsed on the host
+sim_insts                                   407807707                       # Number of instructions simulated
+sim_ops                                     806107146                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2477120                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1034624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10750336                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             14265472                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1034624                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1034624                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9529024                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9529024                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        38705                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           49                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16166                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             167974                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                222898                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          148891                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               148891                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       482120                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            610                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               201368                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2092331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2776479                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          201368                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             201368                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1854627                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1854627                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1854627                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       482120                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              201368                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2092331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4631107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        222898                       # Number of read requests accepted
-system.physmem.writeReqs                       148891                       # Number of write requests accepted
-system.physmem.readBursts                      222898                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     148891                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 14252672                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     12800                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9527360                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  14265472                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9529024                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      200                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::pc.south_bridge.ide      2476992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1035072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10749056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             14265280                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1035072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1035072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9521344                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9521344                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        38703                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           60                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16173                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             167954                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                222895                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          148771                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               148771                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       481721                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            747                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               201299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2090459                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2774289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          201299                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             201299                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1851696                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1851696                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1851696                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       481721                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           747                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              201299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2090459                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4625984                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        222895                       # Number of read requests accepted
+system.physmem.writeReqs                       148771                       # Number of write requests accepted
+system.physmem.readBursts                      222895                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     148771                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 14256576                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8704                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9520064                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  14265280                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9521344                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      136                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1701                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               14548                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               13887                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               14162                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               13520                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14300                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               13581                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               13426                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13413                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               13607                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               13662                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              13602                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              13631                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              14336                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              14588                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              14340                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              14095                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9881                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9301                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9417                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9104                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9702                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8858                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8862                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8906                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8978                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9056                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9081                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9102                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9605                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9854                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9646                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9512                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           1680                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               14406                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               13692                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               14137                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               13444                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14027                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               13372                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               13359                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               13805                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               13762                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               13592                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              13956                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              13564                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              14528                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              14698                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              14291                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              14126                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9807                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9166                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9421                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8835                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9422                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8917                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8763                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9221                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9116                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9134                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9470                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8904                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9718                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9806                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9580                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9471                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5137971883500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5141959559500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  222898                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  222895                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 148891                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    173419                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     13832                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      4649                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      2839                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2570                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4077                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3447                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3320                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      2968                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1935                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1479                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1288                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1096                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      836                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      757                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      725                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      696                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      691                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      416                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       25                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 148771                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    173187                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     13769                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      5947                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      3181                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      3035                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      3711                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3299                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3149                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      2487                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1947                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1694                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1507                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1113                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1005                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      833                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      764                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      718                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      557                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      456                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      376                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       24                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -156,224 +156,223 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6088                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8587                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8595                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2877                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2092                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1654                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      892                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      352                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        49868                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      381.994064                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     221.175651                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     374.202346                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15813     31.71%     31.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11064     22.19%     53.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5080     10.19%     64.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2824      5.66%     69.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1980      3.97%     73.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1284      2.57%     76.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          922      1.85%     78.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          716      1.44%     79.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        10185     20.42%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          49868                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          8142                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.350037                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      531.765782                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           8141     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1818                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6295                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6807                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7687                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7974                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8492                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8899                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9209                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     9322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     9232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     9176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1906                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1843                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      845                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        74587                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      318.776409                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     185.138812                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     338.199277                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          28275     37.91%     37.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        16828     22.56%     60.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7503     10.06%     70.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4244      5.69%     76.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3057      4.10%     80.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2068      2.77%     83.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1382      1.85%     84.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1175      1.58%     86.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10055     13.48%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          74587                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          8285                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.884007                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      527.034010                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           8284     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            8142                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          8142                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.283591                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.627324                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.611364                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            6056     74.38%     74.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            1276     15.67%     90.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21             101      1.24%     91.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              41      0.50%     91.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              52      0.64%     92.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              70      0.86%     93.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29              65      0.80%     94.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31              71      0.87%     94.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33              51      0.63%     95.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35              44      0.54%     96.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37              56      0.69%     96.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39              33      0.41%     97.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41              34      0.42%     97.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43              29      0.36%     98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45              35      0.43%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47              23      0.28%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49              19      0.23%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51              12      0.15%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53              12      0.15%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               9      0.11%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               6      0.07%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59               7      0.09%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61               2      0.02%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63              13      0.16%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-65              13      0.16%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::66-67               1      0.01%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::70-71               1      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-73               4      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::74-75               3      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-77               2      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-81               1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            8142                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5275412250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9510468500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1113490000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  3121566250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       23688.64                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14017.04                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            8285                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          8285                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.954255                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.428609                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        5.676130                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            6158     74.33%     74.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            1338     16.15%     90.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              52      0.63%     91.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              77      0.93%     92.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              47      0.57%     92.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              55      0.66%     93.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29             103      1.24%     94.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31              89      1.07%     95.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33              47      0.57%     96.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35              58      0.70%     96.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37              37      0.45%     97.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39              45      0.54%     97.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41              69      0.83%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43              27      0.33%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45              11      0.13%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47              16      0.19%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49              22      0.27%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               4      0.05%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               7      0.08%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               3      0.04%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               2      0.02%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59               3      0.04%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               5      0.06%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62-63               4      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-65               3      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::66-67               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-81               1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-89               1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            8285                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4923822749                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9100553999                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1113795000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22103.81                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  42705.68                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  40853.81                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.77                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.78                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.77                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.02                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     186969                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    110725                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.96                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.37                       # Row buffer hit rate for writes
-system.physmem.avgGap                     13819590.91                       # Average gap between requests
-system.physmem.pageHitRate                      80.11                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.14                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      5100645                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              662331                       # Transaction distribution
-system.membus.trans_dist::ReadResp             662323                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13764                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13764                       # Transaction distribution
-system.membus.trans_dist::Writeback            148891                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2168                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1718                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            179464                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           179461                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1643                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1643                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3286                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3286                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471038                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       475146                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721276                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       133006                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       133006                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1857568                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241802                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550149                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18330624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20122575                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5463872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5463872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            25593019                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               25593019                       # Total data (bytes)
-system.membus.snoop_data_through_bus           613952                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           250521000                       # Layer occupancy (ticks)
+system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.83                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     186870                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    110052                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.89                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.97                       # Row buffer hit rate for writes
+system.physmem.avgGap                     13834893.59                       # Average gap between requests
+system.physmem.pageHitRate                      79.92                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4934274417750                       # Time in different power states
+system.physmem.memoryStateTime::REF      171701140000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       35983950250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      5095093                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              662466                       # Transaction distribution
+system.membus.trans_dist::ReadResp             662464                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13782                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13782                       # Transaction distribution
+system.membus.trans_dist::Writeback            148771                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2188                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1699                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            179320                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           179319                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1645                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1645                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3290                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3290                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471084                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775082                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       475021                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721191                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       132996                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       132996                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1857477                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241828                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550161                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18322944                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20114933                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5463680                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      5463680                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            25585193                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               25585193                       # Total data (bytes)
+system.membus.snoop_data_through_bus           613568                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           250592000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           583253500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           583283000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3286000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3290000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1611616249                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1610033997                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy               10500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1643000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1645000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         3152435901                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         3152758703                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy          429736248                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy          429601748                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47579                       # number of replacements
-system.iocache.tags.tagsinuse                0.116331                       # Cycle average of tags in use
+system.iocache.tags.replacements                47571                       # number of replacements
+system.iocache.tags.tagsinuse                0.128712                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47595                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47587                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4992993838000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116331                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007271                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.007271                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4992977133000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.128712                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008045                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.008045                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428697                       # Number of tag accesses
-system.iocache.tags.data_accesses              428697                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          913                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              913                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428634                       # Number of tag accesses
+system.iocache.tags.data_accesses              428634                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          906                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              906                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47633                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47633                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47633                       # number of overall misses
-system.iocache.overall_misses::total            47633                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    149265435                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    149265435                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  11474717915                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  11474717915                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide  11623983350                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  11623983350                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide  11623983350                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  11623983350                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          913                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            913                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47626                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47626                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47626                       # number of overall misses
+system.iocache.overall_misses::total            47626                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    147491196                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    147491196                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  11109159898                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  11109159898                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide  11256651094                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  11256651094                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide  11256651094                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  11256651094                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          906                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            906                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47633                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47633                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47633                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47633                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47626                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47626                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47626                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47626                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -382,40 +381,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163488.975904                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 163488.975904                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245606.119756                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 245606.119756                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244032.148930                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 244032.148930                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244032.148930                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 244032.148930                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        177888                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162793.814570                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 162793.814570                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 237781.675899                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 237781.675899                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 236355.165120                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 236355.165120                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 236355.165120                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 236355.165120                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        159859                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                14382                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                14672                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.368794                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.895515                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           46668                       # number of writebacks
-system.iocache.writebacks::total                46668                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          913                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          913                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           46667                       # number of writebacks
+system.iocache.writebacks::total                46667                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          906                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          906                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47633                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47633                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47633                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47633                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    101762935                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    101762935                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   9043225919                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   9043225919                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   9144988854                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   9144988854                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   9144988854                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   9144988854                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47626                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47626                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47626                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47626                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    100353196                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    100353196                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   8677810402                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   8677810402                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   8778163598                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8778163598                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   8778163598                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8778163598                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -424,18 +423,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111459.950712                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 111459.950712                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193562.198609                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 193562.198609                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 191988.513300                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 191988.513300                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110765.116998                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 110765.116998                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 185740.804837                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 185740.804837                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 184314.525637                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 184314.525637                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
@@ -445,16 +444,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.throughput                        637649                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq               225561                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              225561                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57591                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57591                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1643                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1643                       # Transaction distribution
+system.iobus.throughput                        637150                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               225562                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              225562                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57606                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57606                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1645                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1645                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
@@ -470,15 +469,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       471038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95266                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95266                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3286                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3286                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  569590                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       471084                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95252                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95252                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3290                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3290                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  569626                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
@@ -494,20 +493,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total       241802                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027848                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027848                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              3276222                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 3276222                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              3918904                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total       241828                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027792                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027792                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6580                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              3276200                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 3276200                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              3930346                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              8851000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -537,155 +536,155 @@ system.iobus.reqLayer16.occupancy                9000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           425268102                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           424685346                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           460167000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           460198000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            53403752                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            53671252                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1643000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1645000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                85606951                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          85606951                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            878900                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             79252981                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                77536604                       # Number of BTB hits
+system.cpu.branchPred.lookups                85633263                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          85633263                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            884686                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             79267379                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                77548662                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.834306                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1442152                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             179942                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.831747                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1440338                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             180105                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        453123649                       # number of cpu cycles simulated
+system.cpu.numCycles                        453234333                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           25513299                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      422793316                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85606951                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           78978756                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     162666775                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3977899                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     109317                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               70887668                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                43514                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         89257                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          186                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8479758                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                384207                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    2414                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          262364646                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.182537                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.411732                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           25483623                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      422835891                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85633263                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           78989000                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     162683938                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4002747                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     108573                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               70983982                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                43526                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         92374                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          193                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8487571                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                384793                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    2466                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          262469836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.181706                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.411661                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                100112047     38.16%     38.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1537808      0.59%     38.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 71834602     27.38%     66.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   894624      0.34%     66.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1560586      0.59%     67.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2393199      0.91%     67.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1018516      0.39%     68.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1331320      0.51%     68.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81681944     31.13%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                100201994     38.18%     38.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1531970      0.58%     38.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 71824716     27.36%     66.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   909581      0.35%     66.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1572022      0.60%     67.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2391233      0.91%     67.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1015593      0.39%     68.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1327813      0.51%     68.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81694914     31.13%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            262364646                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.188926                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.933064                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 29407134                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              68048451                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 158512522                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3341909                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3054630                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              832669874                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   887                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3054630                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 32105381                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                42832622                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       12466754                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 158806940                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13098319                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              829768905                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 20738                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                6073581                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               5148249                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           991466417                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1800660067                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1107048961                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               106                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             964157062                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27309353                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             454429                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         460129                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  29597584                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             16731616                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             9822119                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1090956                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           912656                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  824999655                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1185445                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 821065367                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            147374                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        19153823                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     29264539                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         130709                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     262364646                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         3.129482                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.399412                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            262469836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.188938                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.932930                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 29410093                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              68121182                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 158520657                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3344277                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3073627                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              832752013                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   987                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3073627                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 32108860                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                42947155                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       12423337                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 158815296                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13101561                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              829828808                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 20476                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                6069323                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               5155919                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           991491995                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1800757525                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1107104494                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               110                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             964043985                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 27448008                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             454148                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         459927                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  29603104                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             16744391                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             9834089                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1098610                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           922271                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  825029586                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1184674                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 821050392                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            152353                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        19282759                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     29404306                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         129800                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     262469836                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         3.128170                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.399623                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            75980319     28.96%     28.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            15750588      6.00%     34.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10556494      4.02%     38.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7365908      2.81%     41.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            75746368     28.87%     70.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3736962      1.42%     72.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72307682     27.56%     99.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              774907      0.30%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              145418      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            76068971     28.98%     28.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            15764450      6.01%     34.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10561557      4.02%     39.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7380977      2.81%     41.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            75732754     28.85%     70.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3744713      1.43%     72.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72297753     27.55%     99.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              770490      0.29%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              148171      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       262364646                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       262469836                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  352804     33.38%     33.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                    241      0.02%     33.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                     895      0.08%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 548620     51.91%     85.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                154313     14.60%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  351121     33.32%     33.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    242      0.02%     33.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                     235      0.02%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 548827     52.08%     85.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                153397     14.56%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            307554      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             793584898     96.65%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               150109      0.02%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                124066      0.02%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            310274      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             793553745     96.65%     96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150127      0.02%     96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                124319      0.02%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.72% # Type of FU issued
@@ -712,297 +711,332 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.72% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             17676623      2.15%     98.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9222117      1.12%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             17682976      2.15%     98.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9228951      1.12%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              821065367                       # Type of FU issued
-system.cpu.iq.rate                           1.812012                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1056873                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001287                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1905808819                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         845349453                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    817155578                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 173                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                180                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           48                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              821814606                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      80                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1693534                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              821050392                       # Type of FU issued
+system.cpu.iq.rate                           1.811536                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1053822                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001284                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1905885622                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         845507474                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    817131376                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 174                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                198                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           50                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              821793858                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      82                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1694774                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2731831                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        17734                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        12108                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1395931                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2743773                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        18703                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        12097                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1404751                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      1932011                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         12232                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      1931902                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         12205                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3054630                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                30960729                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2157350                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           826185100                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            241589                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              16731616                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              9822119                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             690497                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1620390                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 12858                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          12108                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         495281                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       506440                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1001721                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             819661058                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17373288                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1404308                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3073627                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                31062869                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2159597                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           826214260                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            248339                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              16744391                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              9834089                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             689465                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1620816                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 13300                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          12097                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         498594                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       510068                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1008662                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             819639552                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              17378500                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1410839                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     26412112                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83101028                       # Number of branches executed
-system.cpu.iew.exec_stores                    9038824                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.808913                       # Inst execution rate
-system.cpu.iew.wb_sent                      819257147                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     817155626                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 638657480                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1044041746                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     26423310                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83104184                       # Number of branches executed
+system.cpu.iew.exec_stores                    9044810                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.808423                       # Inst execution rate
+system.cpu.iew.wb_sent                      819235043                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     817131426                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 638623234                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1043962608                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.803383                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.611716                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.802890                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.611730                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        19877862                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1054736                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            888910                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    259310016                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     3.109013                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.863250                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        19998130                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1054874                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            894775                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    259396209                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     3.107629                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.863349                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     87730314     33.83%     33.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11862694      4.57%     38.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3835821      1.48%     39.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74768182     28.83%     68.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2381229      0.92%     69.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1479438      0.57%     70.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       861979      0.33%     70.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     70857593     27.33%     97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5532766      2.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     87828444     33.86%     33.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11868241      4.58%     38.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3842531      1.48%     39.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74752258     28.82%     68.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2384729      0.92%     69.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1479281      0.57%     70.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       859408      0.33%     70.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     70845236     27.31%     97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5536081      2.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    259310016                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407854776                       # Number of instructions committed
-system.cpu.commit.committedOps              806198141                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    259396209                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407807707                       # Number of instructions committed
+system.cpu.commit.committedOps              806107146                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22425972                       # Number of memory references committed
-system.cpu.commit.loads                      13999784                       # Number of loads committed
-system.cpu.commit.membars                      474669                       # Number of memory barriers committed
-system.cpu.commit.branches                   82177261                       # Number of branches committed
+system.cpu.commit.refs                       22429955                       # Number of memory references committed
+system.cpu.commit.loads                      14000617                       # Number of loads committed
+system.cpu.commit.membars                      474711                       # Number of memory barriers committed
+system.cpu.commit.branches                   82167469                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 735033306                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155486                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5532766                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                 734952495                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155627                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       174437      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783236239     97.16%     97.18% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          144862      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121653      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        14000617      1.74%     98.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8429338      1.05%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total         806107146                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5536081                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1079774887                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1655221365                       # The number of ROB writes
-system.cpu.timesIdled                         1257777                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       190759003                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9822826051                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407854776                       # Number of Instructions Simulated
-system.cpu.committedOps                     806198141                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             407854776                       # Number of Instructions Simulated
-system.cpu.cpi                               1.110993                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.110993                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.900096                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.900096                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1088904390                       # number of integer regfile reads
-system.cpu.int_regfile_writes               653903158                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        48                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 415697548                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                321557341                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               264102486                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 402568                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                53587278                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        3014875                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3014340                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13764                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13764                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1579042                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       336648                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       289942                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1911181                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6131826                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18757                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       150026                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8211790                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61153920                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207959183                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       582080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5191488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      274886671                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         274861071                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       468864                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4035423910                       # Layer occupancy (ticks)
+system.cpu.rob.rob_reads                   1079887016                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1655298855                       # The number of ROB writes
+system.cpu.timesIdled                         1259672                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       190764497                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9830690598                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407807707                       # Number of Instructions Simulated
+system.cpu.committedOps                     806107146                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             407807707                       # Number of Instructions Simulated
+system.cpu.cpi                               1.111392                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.111392                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.899772                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.899772                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1088844162                       # number of integer regfile reads
+system.cpu.int_regfile_writes               653876789                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        50                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 415644137                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                321521730                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               264115519                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 402672                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                53624827                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        3015737                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3015197                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13782                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13782                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1584798                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2253                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2253                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       336401                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       289692                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1908205                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6128379                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        19318                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       159676                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8215578                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61059136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207801717                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       607680                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5615104                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      275083637                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         275059381                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       677312                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     4044441846                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       600000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       568500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1436807344                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1434613560                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3142634309                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3141764506                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      14495745                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      14738244                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     103414152                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     107967138                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            955079                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.954947                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7470392                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            955591                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.817562                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      147668859250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.954947                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996006                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996006                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            953583                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.342760                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7479724                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            954095                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.839601                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      147639960250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.342760                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994810                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994810                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          175                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          177                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           9435405                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          9435405                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7470392                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7470392                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7470392                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7470392                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7470392                       # number of overall hits
-system.cpu.icache.overall_hits::total         7470392                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1009362                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1009362                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1009362                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1009362                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1009362                       # number of overall misses
-system.cpu.icache.overall_misses::total       1009362                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14063763284                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14063763284                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14063763284                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14063763284                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14063763284                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14063763284                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8479754                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8479754                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8479754                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8479754                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8479754                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8479754                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.119032                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.119032                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.119032                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.119032                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.119032                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.119032                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13933.319546                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13933.319546                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13933.319546                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13933.319546                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13933.319546                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13933.319546                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4512                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses           9441724                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          9441724                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7479724                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7479724                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7479724                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7479724                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7479724                       # number of overall hits
+system.cpu.icache.overall_hits::total         7479724                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1007844                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1007844                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1007844                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1007844                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1007844                       # number of overall misses
+system.cpu.icache.overall_misses::total       1007844                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14035582232                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14035582232                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14035582232                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14035582232                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14035582232                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14035582232                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8487568                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8487568                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8487568                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8487568                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8487568                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8487568                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.118744                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.118744                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.118744                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.118744                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.118744                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.118744                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13926.343990                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13926.343990                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13926.343990                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13926.343990                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13926.343990                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13926.343990                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         4168                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               173                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               190                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    26.080925                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.936842                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53711                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        53711                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        53711                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        53711                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        53711                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        53711                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       955651                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       955651                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       955651                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       955651                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       955651                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       955651                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11613116903                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11613116903                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11613116903                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11613116903                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11613116903                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11613116903                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112698                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112698                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112698                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.112698                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112698                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.112698                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12152.048083                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12152.048083                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12152.048083                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12152.048083                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12152.048083                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12152.048083                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53688                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        53688                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        53688                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        53688                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        53688                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        53688                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       954156                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       954156                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       954156                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       954156                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       954156                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       954156                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11587558437                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11587558437                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11587558437                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11587558437                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11587558437                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11587558437                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112418                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112418                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112418                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.112418                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112418                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.112418                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12144.301809                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12144.301809                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12144.301809                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12144.301809                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12144.301809                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12144.301809                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements         8788                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     5.050842                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        20362                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs         8802                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     2.313338                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5105053160000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     5.050842                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.315678                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.315678                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.replacements         8939                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.031288                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        21114                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs         8953                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     2.358316                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5104803925000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.031288                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376956                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.376956                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        69716                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        69716                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        20363                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        20363                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.tag_accesses        71741                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        71741                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        21134                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        21134                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        20365                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        20365                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        20365                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        20365                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9662                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         9662                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9662                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         9662                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9662                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         9662                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    109674498                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    109674498                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    109674498                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    109674498                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    109674498                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    109674498                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        30025                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        30025                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        21136                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        21136                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        21136                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        21136                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9823                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         9823                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9823                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         9823                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9823                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         9823                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    107949749                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    107949749                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    107949749                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    107949749                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    107949749                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    107949749                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        30957                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        30957                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        30027                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        30027                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        30027                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        30027                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.321799                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.321799                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.321777                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.321777                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.321777                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.321777                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11351.117574                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11351.117574                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11351.117574                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11351.117574                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11351.117574                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11351.117574                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        30959                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        30959                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        30959                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        30959                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.317311                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.317311                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.317291                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.317291                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.317291                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.317291                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10989.488853                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10989.488853                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10989.488853                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10989.488853                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10989.488853                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10989.488853                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1011,85 +1045,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         1311                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         1311                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9662                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9662                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9662                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         9662                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9662                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         9662                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     90345008                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     90345008                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     90345008                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     90345008                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     90345008                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     90345008                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.321799                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.321799                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.321777                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.321777                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.321777                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.321777                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9350.549369                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9350.549369                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9350.549369                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9350.549369                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9350.549369                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9350.549369                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         1983                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         1983                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9823                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9823                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9823                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         9823                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9823                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         9823                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     88296261                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     88296261                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     88296261                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     88296261                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     88296261                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     88296261                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.317311                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.317311                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.317291                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.317291                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.317291                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.317291                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8988.726560                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8988.726560                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8988.726560                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8988.726560                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8988.726560                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8988.726560                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        67950                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    13.831671                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        92323                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        67966                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.358370                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5101646178000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    13.831671                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.864479                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.864479                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements        70861                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    12.940736                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        90199                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        70877                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.272613                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5101635052500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    12.940736                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.808796                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.808796                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       391373                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       391373                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92323                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        92323                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92323                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        92323                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92323                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        92323                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        68909                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        68909                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        68909                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        68909                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        68909                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        68909                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    862549215                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    862549215                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    862549215                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    862549215                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    862549215                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    862549215                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       161232                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       161232                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       161232                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       161232                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       161232                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       161232                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.427390                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.427390                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.427390                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.427390                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.427390                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.427390                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12517.221481                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12517.221481                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12517.221481                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12517.221481                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12517.221481                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12517.221481                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses       396218                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       396218                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        90199                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        90199                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        90199                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        90199                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        90199                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        90199                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        71940                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        71940                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        71940                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        71940                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        71940                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        71940                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    878693205                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    878693205                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    878693205                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    878693205                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    878693205                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    878693205                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       162139                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       162139                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       162139                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       162139                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       162139                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       162139                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.443693                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.443693                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.443693                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.443693                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.443693                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.443693                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12214.250834                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12214.250834                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12214.250834                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12214.250834                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12214.250834                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12214.250834                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1098,153 +1132,153 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        16529                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        16529                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        68909                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        68909                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        68909                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        68909                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        68909                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        68909                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    724629911                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    724629911                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    724629911                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    724629911                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    724629911                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    724629911                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.427390                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.427390                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.427390                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.427390                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.427390                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.427390                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.751368                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.751368                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.751368                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        22838                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        22838                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        71940                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        71940                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        71940                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        71940                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        71940                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        71940                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    734698929                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    734698929                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    734698929                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    734698929                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    734698929                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    734698929                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.443693                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.443693                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.443693                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.443693                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.443693                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.443693                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10212.662344                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10212.662344                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10212.662344                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1659840                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.996448                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18992605                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1660352                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.438903                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          40084250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.996448                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999993                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1658766                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994288                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19002910                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1659278                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.452517                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          39778250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994288                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          87845319                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         87845319                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10889826                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10889826                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8100117                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8100117                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      18989943                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18989943                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18989943                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18989943                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2239768                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2239768                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       316527                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       316527                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2556295                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2556295                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2556295                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2556295                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32903838390                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32903838390                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11976667737                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11976667737                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  44880506127                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  44880506127                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  44880506127                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  44880506127                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13129594                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13129594                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8416644                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8416644                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21546238                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21546238                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21546238                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21546238                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170589                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.170589                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037607                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037607                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.118642                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.118642                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118642                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118642                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14690.735107                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14690.735107                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37837.744448                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37837.744448                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17556.857142                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17556.857142                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17556.857142                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17556.857142                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       388578                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          87874474                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         87874474                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10896738                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10896738                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8103479                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8103479                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      19000217                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19000217                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19000217                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19000217                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2237270                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2237270                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       316309                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       316309                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2553579                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2553579                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2553579                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2553579                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32758938054                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32758938054                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  12034849454                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  12034849454                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  44793787508                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  44793787508                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  44793787508                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  44793787508                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13134008                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13134008                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8419788                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8419788                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21553796                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21553796                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21553796                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21553796                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170342                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.170342                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037567                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037567                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.118475                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.118475                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.118475                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.118475                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14642.371307                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14642.371307                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38047.761695                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38047.761695                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17541.571069                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17541.571069                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17541.571069                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17541.571069                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       388234                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             42350                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             42159                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.175396                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.208805                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1561202                       # number of writebacks
-system.cpu.dcache.writebacks::total           1561202                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       869210                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       869210                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        24502                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        24502                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       893712                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       893712                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       893712                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       893712                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1370558                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1370558                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       292025                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       292025                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1662583                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1662583                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1662583                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1662583                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17741695710                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17741695710                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11080104948                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11080104948                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28821800658                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  28821800658                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28821800658                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28821800658                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97363380000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97363380000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2536381000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2536381000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99899761000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  99899761000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104387                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104387                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034696                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034696                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077163                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.077163                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077163                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.077163                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12944.870418                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12944.870418                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.316404                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.316404                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17335.555974                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17335.555974                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17335.555974                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17335.555974                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1559977                       # number of writebacks
+system.cpu.dcache.writebacks::total           1559977                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       867558                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       867558                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        24476                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        24476                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       892034                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       892034                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       892034                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       892034                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1369712                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1369712                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       291833                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       291833                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1661545                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1661545                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1661545                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1661545                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17680675970                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  17680675970                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11138475501                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11138475501                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28819151471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  28819151471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28819151471                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28819151471                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97364609500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97364609500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2539074000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2539074000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99903683500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  99903683500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104287                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104287                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034660                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034660                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077088                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.077088                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077088                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077088                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.316471                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.316471                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38167.292599                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38167.292599                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17344.791427                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17344.791427                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17344.791427                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17344.791427                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1252,150 +1286,150 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           111989                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64821.159717                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3780351                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176044                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            21.473899                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           111887                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64820.177016                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3787056                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176012                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            21.515897                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50592.226872                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.121398                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.097025                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2916.382816                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11302.331606                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.771976                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000154                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000001                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.044500                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.172460                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.989092                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64055                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          517                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3496                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6269                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53720                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977402                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         34623360                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        34623360                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        64539                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7780                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       939362                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1333943                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2345624                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1579042                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1579042                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          315                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          315                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       156902                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       156902                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        64539                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         7780                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       939362                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1490845                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2502526                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        64539                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         7780                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       939362                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1490845                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2502526                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           49                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            4                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        16168                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        35908                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        52129                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1443                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1443                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133016                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133016                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           49                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            4                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        16168                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       168924                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        185145                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           49                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            4                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        16168                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       168924                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       185145                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4159750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       369250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1243133741                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2836550442                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   4084213183                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17687795                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     17687795                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9175416141                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9175416141                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4159750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       369250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1243133741                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  12011966583                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13259629324                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4159750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       369250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1243133741                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  12011966583                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13259629324                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        64588                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7784                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       955530                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1369851                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2397753                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1579042                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1579042                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1758                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1758                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       289918                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       289918                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64588                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         7784                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       955530                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1659769                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2687671                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64588                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         7784                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       955530                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1659769                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2687671                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000759                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000514                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016920                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026213                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021741                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.820819                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.820819                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.458806                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.458806                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000759                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000514                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016920                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.101776                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.068887                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000759                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000514                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016920                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.101776                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.068887                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84892.857143                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 92312.500000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76888.529255                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78994.943801                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 78348.197414                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12257.654193                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12257.654193                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68979.792965                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68979.792965                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84892.857143                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 92312.500000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76888.529255                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71108.703222                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71617.539356                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84892.857143                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 92312.500000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76888.529255                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71108.703222                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71617.539356                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 50551.329322                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.553377                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.127382                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2956.401453                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11298.765482                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.771352                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000207                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.045111                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.172405                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.989077                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          513                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3391                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5259                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54885                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978470                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         34647865                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        34647865                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        64838                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7507                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       937874                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1332851                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2343070                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1584798                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1584798                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          327                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          327                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       156813                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       156813                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        64838                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         7507                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       937874                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1489664                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2499883                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        64838                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         7507                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       937874                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1489664                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2499883                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           60                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        16175                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        36023                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        52263                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1437                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1437                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       132861                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       132861                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           60                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        16175                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       168884                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        185124                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           60                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        16175                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       168884                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       185124                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      5066750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       378250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1233234983                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2788798959                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   4027478942                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17149821                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     17149821                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9234678927                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9234678927                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      5066750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       378250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1233234983                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  12023477886                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  13262157869                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      5066750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       378250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1233234983                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  12023477886                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  13262157869                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        64898                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7512                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       954049                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1368874                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2395333                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1584798                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1584798                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1764                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1764                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       289674                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       289674                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64898                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         7512                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       954049                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1658548                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2685007                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64898                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         7512                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       954049                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1658548                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2685007                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000925                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000666                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016954                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026316                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.021819                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.814626                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.814626                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.458657                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.458657                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000925                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000666                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016954                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.101826                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.068947                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000925                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000666                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016954                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.101826                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.068947                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84445.833333                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        75650                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76243.275611                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77417.176776                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 77061.763427                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11934.461378                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11934.461378                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69506.318084                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69506.318084                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84445.833333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        75650                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76243.275611                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71193.706248                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71639.322125                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84445.833333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        75650                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76243.275611                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71193.706248                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71639.322125                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1404,8 +1438,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       102223                       # number of writebacks
-system.cpu.l2cache.writebacks::total           102223                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       102104                       # number of writebacks
+system.cpu.l2cache.writebacks::total           102104                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
@@ -1415,88 +1449,88 @@ system.cpu.l2cache.demand_mshr_hits::total            4                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           49                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            4                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16166                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35906                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        52125                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1443                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1443                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133016                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133016                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           49                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            4                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16166                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       168922                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       185141                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           49                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            4                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16166                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       168922                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       185141                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3552250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       319250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1040184259                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2389977554                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3434033313                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15330925                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15330925                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7506177359                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7506177359                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3552250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       319250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1040184259                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9896154913                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10940210672                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3552250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       319250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1040184259                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9896154913                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10940210672                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89250256000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89250256000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2370696500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2370696500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91620952500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91620952500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000759                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000514                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016918                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026212                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021739                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.820819                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.820819                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.458806                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.458806                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000759                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000514                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016918                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101774                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.068885                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000759                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000514                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016918                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101774                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.068885                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79812.500000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64343.947730                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66562.066340                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65880.735022                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10624.341649                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10624.341649                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56430.635104                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56430.635104                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79812.500000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64343.947730                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58584.168510                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59091.236798                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79812.500000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64343.947730                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58584.168510                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59091.236798                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           60                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16173                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36021                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        52259                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1437                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1437                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132861                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       132861                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           60                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16173                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       168882                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       185120                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           60                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16173                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       168882                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       185120                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4324750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       315250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1030094767                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2339275539                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3374010306                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15289917                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15289917                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7567196573                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7567196573                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4324750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       315250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1030094767                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9906472112                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10941206879                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4324750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       315250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1030094767                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9906472112                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10941206879                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89251381500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89251381500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2373144500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2373144500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91624526000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91624526000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000925                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000666                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016952                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026314                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021817                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.814626                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.814626                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.458657                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.458657                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000925                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000666                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016952                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101825                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.068946                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000925                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000666                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016952                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101825                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.068946                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63692.250479                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64941.993254                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64563.238983                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10640.164927                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10640.164927                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56955.740006                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56955.740006                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63692.250479                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58659.135444                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59103.321516                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63692.250479                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58659.135444                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59103.321516                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
index cc51e20ce..69bdeab1f 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.304497                       # Nu
 sim_ticks                                5304496750000                       # Number of ticks simulated
 final_tick                               5304496750000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 156851                       # Simulator instruction rate (inst/s)
-host_op_rate                                   300747                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7785889362                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 816820                       # Number of bytes of host memory used
-host_seconds                                   681.30                       # Real time elapsed on the host
+host_inst_rate                                 145026                       # Simulator instruction rate (inst/s)
+host_op_rate                                   278074                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7198918941                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 818088                       # Number of bytes of host memory used
+host_seconds                                   736.85                       # Real time elapsed on the host
 sim_insts                                   106862058                       # Number of instructions simulated
 sim_ops                                     204897478                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -234,9 +234,7 @@ system.physmem.wrQLenPdf::63                        0                       # Wh
 system.physmem.totQLat                              0                       # Total ticks spent queuing
 system.physmem.totMemAccLat                         0                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                            0                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                           0                       # Total ticks spent accessing banks
 system.physmem.avgQLat                            nan                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                         nan                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                          nan                       # Average bus latency per DRAM burst
 system.physmem.avgMemAccLat                       nan                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           0.00                       # Average DRAM read bandwidth in MiByte/s
@@ -255,137 +253,11 @@ system.physmem.readRowHitRate                     nan                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                             nan                       # Average gap between requests
 system.physmem.pageHitRate                        nan                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.00                       # Percentage of time for which DRAM has all the banks in precharge state
-system.iobus.throughput                       383259                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq              858443                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             858443                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              37726                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             37726                       # Transaction distribution
-system.iobus.trans_dist::MessageReq             1924                       # Transaction distribution
-system.iobus.trans_dist::MessageResp            1924                       # Transaction distribution
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1702                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1646                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3348                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6438                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           88                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          956                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       934582                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          980                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio           90                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14492                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       743206                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          242                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1703384                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4650                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           92                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          408                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        33042                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          354                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        33130                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12176                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         5244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        89454                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                1796186                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3404                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3292                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6696                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3666                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          149                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          478                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       467291                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1960                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio           45                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7246                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1486406                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          484                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1972069                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3020                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           72                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        16521                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          708                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        16565                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6088                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          516                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port        10485                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        54229                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total             2032994                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                2032994                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy               45000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                7000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy            10111500                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              143500                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy             1076000                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy               95000                       # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy               57500                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy            30321000                       # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy           467293000                       # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy             1240500                       # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy           41494500                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization              0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy               2000                       # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization              0.0                       # Layer utilization (%)
-system.iobus.reqLayer12.occupancy           23487000                       # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization              0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy              12000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization              0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization              0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization              0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy              10500                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization              0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy          469626032                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization              0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy            7795368                       # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization              0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy            1328500                       # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization              0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            2413900                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy         1790216000                       # Layer occupancy (ticks)
-system.iobus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy           80190500                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization              0.0                       # Layer utilization (%)
+system.physmem.memoryStateTime::IDLE     5127363440000                       # Time in different power states
+system.physmem.memoryStateTime::REF      177128640000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT                 0                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.ruby.clk_domain.clock                      500                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  2                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  19                       # delay histogram for all message
@@ -590,6 +462,136 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
+system.iobus.throughput                        383259                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               858443                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              858443                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               37726                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              37726                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1924                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1924                       # Transaction distribution
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1702                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1646                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3348                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6438                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           88                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          956                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       934582                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          980                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio           90                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14492                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       743206                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          242                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1703384                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4650                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           92                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          408                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        33042                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          354                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        33130                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12176                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          258                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         5244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        89454                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 1796186                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3404                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3292                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6696                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3666                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          149                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          478                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       467291                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1960                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio           45                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7246                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1486406                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          484                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1972069                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3020                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           72                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          204                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        16521                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          708                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        16565                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6088                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          516                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port        10485                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        54229                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              2032994                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2032994                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy                45000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy                 7000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy             10111500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy               143500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy              1076000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer5.occupancy                95000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer6.occupancy                57500                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy             30321000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer8.occupancy            467293000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer9.occupancy              1240500                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy            41494500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer11.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer12.occupancy            23487000                       # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer17.occupancy           469626032                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer18.occupancy             7795368                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer20.occupancy             1328500                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy             2413900                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer2.occupancy          1790216000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer4.occupancy            80190500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
 system.cpu0.numCycles                     10608993500                       # number of cpu cycles simulated
@@ -617,6 +619,41 @@ system.cpu0.num_busy_cycles              526834059.049901
 system.cpu0.not_idle_fraction                0.049659                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.950341                       # Percentage of idle cycles
 system.cpu0.Branches                         11678784                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass               146088      0.13%      0.13% # Class of executed instruction
+system.cpu0.op_class::IntAlu                102315691     88.54%     88.66% # Class of executed instruction
+system.cpu0.op_class::IntMult                   88423      0.08%     88.74% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    60803      0.05%     88.79% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     88.79% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7847946      6.79%     95.58% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5106253      4.42%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                 115565204                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
@@ -645,6 +682,41 @@ system.cpu1.num_busy_cycles              320373991.077311
 system.cpu1.not_idle_fraction                0.030207                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.969793                       # Percentage of idle cycles
 system.cpu1.Branches                         10261767                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               160875      0.18%      0.18% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 75501866     84.52%     84.70% # Class of executed instruction
+system.cpu1.op_class::IntMult                   96299      0.11%     84.80% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    67676      0.08%     84.88% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     84.88% # Class of executed instruction
+system.cpu1.op_class::MemRead                 8734970      9.78%     94.66% # Class of executed instruction
+system.cpu1.op_class::MemWrite                4772103      5.34%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                  89333789                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.ruby.network.routers0.throttle0.link_utilization     0.041639                      
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 4c7c80e7e..66a37e2a3 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,159 +1,155 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.139775                       # Number of seconds simulated
-sim_ticks                                5139775442500                       # Number of ticks simulated
-final_tick                               5139775442500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.133875                       # Number of seconds simulated
+sim_ticks                                5133874673500                       # Number of ticks simulated
+final_tick                               5133874673500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 235748                       # Simulator instruction rate (inst/s)
-host_op_rate                                   468611                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4967362364                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 954112                       # Number of bytes of host memory used
-host_seconds                                  1034.71                       # Real time elapsed on the host
-sim_insts                                   243931071                       # Number of instructions simulated
-sim_ops                                     484875903                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 230895                       # Simulator instruction rate (inst/s)
+host_op_rate                                   458967                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4861072606                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 966208                       # Number of bytes of host memory used
+host_seconds                                  1056.12                       # Real time elapsed on the host
+sim_insts                                   243852608                       # Number of instructions simulated
+sim_ops                                     484724489                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2452480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           439552                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5834944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            98048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1717440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         1664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           432064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2820032                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13796608                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       439552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        98048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       432064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          969664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9118784                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9118784                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        38320                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6868                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             91171                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1532                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             26835                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           26                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              6751                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             44063                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                215572                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          142481                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142481                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       477157                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               85520                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1135253                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               19076                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              334147                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           324                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               84063                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              548668                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2684282                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          85520                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          19076                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          84063                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             188659                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1774160                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1774160                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1774160                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       477157                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              85520                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1135253                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              19076                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             334147                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          324                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              84063                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             548668                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4458442                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         98736                       # Number of read requests accepted
-system.physmem.writeReqs                        74818                       # Number of write requests accepted
-system.physmem.readBursts                       98736                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      74818                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  6312704                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6400                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4788352                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   6319104                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4788352                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      100                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::pc.south_bridge.ide      2445440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           500480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5911104                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           139776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1689280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           309696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2752128                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             13749568                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       500480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       139776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       309696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          949952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9083392                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9083392                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        38210                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              7820                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             92361                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2184                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             26395                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           21                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4839                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             43002                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                214837                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          141928                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               141928                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       476334                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               97486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1151392                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               27226                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              329046                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           262                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               60324                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              536072                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2678205                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          97486                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          27226                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          60324                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             185036                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1769305                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1769305                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1769305                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       476334                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              97486                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1151392                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              27226                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             329046                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          262                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              60324                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             536072                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4447510                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         96612                       # Number of read requests accepted
+system.physmem.writeReqs                        73475                       # Number of write requests accepted
+system.physmem.readBursts                       96612                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      73475                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  6177024                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6144                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4701248                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   6183168                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4702400                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       96                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            734                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                6153                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                6286                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                6219                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                6279                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                6331                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                6377                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5798                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                6202                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5707                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                6391                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5673                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               6223                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               6101                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6086                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6643                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6167                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4924                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4781                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4796                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4885                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4841                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4959                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4374                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4731                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4283                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4855                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4375                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4455                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4488                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4484                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5021                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4566                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            831                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5404                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5964                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                6149                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                6338                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5414                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                6001                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5201                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                6053                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5779                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                5783                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5919                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5801                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               6766                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6809                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6844                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               6291                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4307                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4604                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4694                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4750                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4088                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4371                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                3767                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4522                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4168                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4368                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4606                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4444                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               5448                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5248                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5481                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4591                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5135962999500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5132874544500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   98736                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   96612                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  74818                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     76556                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4428                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2029                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1295                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1291                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      2072                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1756                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1697                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1521                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1005                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      865                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      756                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      662                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      578                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      432                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      398                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      380                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      350                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      340                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      203                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       21                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  73475                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     73469                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4666                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2797                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1617                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1564                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      1988                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      1759                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1657                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1283                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       996                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      876                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      745                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      587                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      557                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      459                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      400                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      371                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      290                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      228                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      192                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -165,474 +161,464 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        57                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        55                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        52                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       53                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                       52                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1029                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1079                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3068                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     3317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     3341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     3777                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     3885                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1287                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1013                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      996                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      896                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      877                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      814                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      558                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      418                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        22863                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      371.369637                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     216.870030                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     366.414967                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7224     31.60%     31.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         5292     23.15%     54.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         2324     10.16%     64.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1423      6.22%     71.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          882      3.86%     74.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          607      2.65%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          442      1.93%     79.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          389      1.70%     81.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4280     18.72%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          22863                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4109                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.004867                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      117.614100                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255            4100     99.78%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511             6      0.15%     99.93% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::14                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      991                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3237                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3324                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     3456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     3620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     3779                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4441                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4453                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      921                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      974                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      979                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      929                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      852                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      724                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        35709                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      304.633118                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.344584                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     328.042030                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13828     38.72%     38.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8395     23.51%     62.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3582     10.03%     72.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1962      5.49%     77.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1409      3.95%     81.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          988      2.77%     84.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          701      1.96%     86.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          566      1.59%     88.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4278     11.98%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          35709                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4100                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.539756                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      117.618727                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255            4089     99.73%     99.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511             8      0.20%     99.93% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::512-767             1      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2560-2815            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-6911            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4109                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4109                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.208323                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.187975                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.583219                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-1                44      1.07%      1.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2-3                 6      0.15%      1.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-5                 4      0.10%      1.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6-7                 4      0.10%      1.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-9                 2      0.05%      1.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14-15               4      0.10%      1.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            2755     67.05%     68.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19             853     20.76%     89.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              55      1.34%     90.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              41      1.00%     91.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              36      0.88%     92.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              45      1.10%     93.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29              25      0.61%     94.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31              36      0.88%     95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33              20      0.49%     95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35              26      0.63%     96.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37              28      0.68%     96.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39              10      0.24%     97.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41              24      0.58%     97.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43              13      0.32%     98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45              21      0.51%     98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47              18      0.44%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               6      0.15%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               4      0.10%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53              10      0.24%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               1      0.02%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59               2      0.05%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61               1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63               4      0.10%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-65               9      0.22%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-69               1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-77               1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4109                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2553947750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4444375250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    493180000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1397247500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       25892.65                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14165.70                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            4100                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4100                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.916341                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.808533                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.372443                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-1                61      1.49%      1.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2-3                 8      0.20%      1.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-5                 2      0.05%      1.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6-7                 3      0.07%      1.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-9                 1      0.02%      1.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10-11               1      0.02%      1.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-13               1      0.02%      1.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14-15               5      0.12%      2.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            2769     67.54%     69.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19             821     20.02%     89.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              36      0.88%     90.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              38      0.93%     91.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              31      0.76%     92.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              30      0.73%     92.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              54      1.32%     94.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31              53      1.29%     95.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33              24      0.59%     96.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35              28      0.68%     96.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37              12      0.29%     97.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39              22      0.54%     97.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41              34      0.83%     98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43              16      0.39%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45              10      0.24%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47               6      0.15%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               8      0.20%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               2      0.05%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               4      0.10%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               5      0.12%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               2      0.05%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59               2      0.05%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62-63               8      0.20%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::66-67               1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::78-79               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4100                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2438372750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4248047750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    482580000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25263.92                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45058.35                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.23                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.93                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.23                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.93                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44013.92                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.20                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.92                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.20                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.92                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.06                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      80976                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     55952                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.78                       # Row buffer hit rate for writes
-system.physmem.avgGap                     29592881.75                       # Average gap between requests
-system.physmem.pageHitRate                      78.94                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.12                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      6444852                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              422305                       # Transaction distribution
-system.membus.trans_dist::ReadResp             422303                       # Transaction distribution
-system.membus.trans_dist::WriteReq               6370                       # Transaction distribution
-system.membus.trans_dist::WriteResp              6370                       # Transaction distribution
-system.membus.trans_dist::Writeback             74818                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              747                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             747                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             78043                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            78043                       # Transaction distribution
-system.membus.trans_dist::MessageReq              885                       # Transaction distribution
-system.membus.trans_dist::MessageResp             885                       # Transaction distribution
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         7.46                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      79177                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     55086                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.04                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.97                       # Row buffer hit rate for writes
+system.physmem.avgGap                     30177935.67                       # Average gap between requests
+system.physmem.pageHitRate                      78.98                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4939989046000                       # Time in different power states
+system.physmem.memoryStateTime::REF      171431260000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       22454250000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      6437004                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              422289                       # Transaction distribution
+system.membus.trans_dist::ReadResp             422287                       # Transaction distribution
+system.membus.trans_dist::WriteReq               6118                       # Transaction distribution
+system.membus.trans_dist::WriteResp              6118                       # Transaction distribution
+system.membus.trans_dist::Writeback             73475                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              843                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             843                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             76388                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            76388                       # Transaction distribution
+system.membus.trans_dist::MessageReq              850                       # Transaction distribution
+system.membus.trans_dist::MessageResp             850                       # Transaction distribution
 system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         1770                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         1770                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       309432                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio       497538                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       212160                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         1700                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         1700                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       308658                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio       497514                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       204215                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1019134                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        66106                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        66106                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1087010                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         3540                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total         3540                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       158682                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio       995073                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      8391680                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total      9545435                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2715776                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      2715776                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            12264751                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               32837413                       # Total data (bytes)
-system.membus.snoop_data_through_bus           287680                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           162853500                       # Layer occupancy (ticks)
+system.membus.pkt_count_system.l2c.mem_side::total      1010391                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        69253                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        69253                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1081344                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         3400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total         3400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       158115                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio       995025                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      8047552                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total      9200692                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2838016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      2838016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            12042108                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               32720690                       # Total data (bytes)
+system.membus.snoop_data_through_bus           326080                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           162128500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           315156500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           315102000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1770000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1700000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           821391499                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           806327999                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy             885000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy             850000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1625485201                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1598914090                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy          213559749                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy          224687998                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   104632                       # number of replacements
-system.l2c.tags.tagsinuse                64756.494280                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3664896                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168700                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.724339                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   103794                       # number of replacements
+system.l2c.tags.tagsinuse                64810.608353                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3657966                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   167984                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.775681                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   51511.220399                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131167                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1228.361726                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4265.224240                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      282.161159                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1465.784470                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    10.322385                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker     0.042344                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1365.490726                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     4627.755664                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.785999                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   51486.278563                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.125055                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1295.377972                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4270.696448                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      302.542141                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1483.932036                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker     7.824361                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1349.140567                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     4614.691210                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.785618                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.018743                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.065082                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.004305                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.022366                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000158                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.000001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.020836                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.070614                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.988106                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64068                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2732                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7219                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53790                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.977600                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 33688290                       # Number of tag accesses
-system.l2c.tags.data_accesses                33688290                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        22061                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        11615                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             344470                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             519863                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        10165                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5243                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             139799                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             221175                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        54188                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        10719                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             354261                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             566062                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2259621                       # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst       0.019766                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.065166                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.004616                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.022643                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000119                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.020586                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.070415                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.988931                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64190                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          474                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3206                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7166                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53256                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.979462                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 33587388                       # Number of tag accesses
+system.l2c.tags.data_accesses                33587388                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        20605                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        11266                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             339595                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             520668                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        10906                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         6430                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             151391                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             219548                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        53731                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker         8985                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             345046                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             563659                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2251830                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks         1545523                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1545523                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             137                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              46                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              93                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 276                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            73996                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            34699                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            57996                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               166691                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         22061                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         11617                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              344470                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              593859                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         10165                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5243                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              139799                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              255874                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         54188                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         10719                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              354261                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              624058                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2426314                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        22061                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        11617                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             344470                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             593859                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        10165                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5243                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             139799                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             255874                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        54188                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        10719                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             354261                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             624058                       # number of overall hits
-system.l2c.overall_hits::total                2426314                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             6868                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data            16704                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1533                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             3888                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           26                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             6752                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data            12246                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                48023                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data           754                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           206                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           371                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1331                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          74862                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          23137                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          32148                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             130147                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              6868                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             91566                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1533                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             27025                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker           26                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              6752                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             44394                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                178170                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             6868                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            91566                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1533                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            27025                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker           26                       # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             6752                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            44394                       # number of overall misses
-system.l2c.overall_misses::total               178170                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst    112485250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    293047996                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      2104000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker       149000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst    524939486                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data    946518491                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1879244223                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      2976906                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data      4826300                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      7803206                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1584451415                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   2283457099                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   3867908514                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    112485250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1877499411                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker      2104000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker       149000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    524939486                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   3229975590                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      5747152737                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    112485250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1877499411                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker      2104000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker       149000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    524939486                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   3229975590                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     5747152737                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        22061                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker        11619                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         351338                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         536567                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        10165                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         5243                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         141332                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         225063                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker        54214                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker        10721                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst         361013                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data         578308                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2307644                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_hits::writebacks         1542066                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1542066                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             135                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              52                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data              72                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 259                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            66169                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            39322                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            60638                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               166129                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         20605                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker         11268                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              339595                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              586837                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         10906                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          6430                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              151391                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              258870                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker         53731                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker          8985                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              345046                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              624297                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2417961                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        20605                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker        11268                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             339595                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             586837                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        10906                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         6430                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             151391                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             258870                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker        53731                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker         8985                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             345046                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             624297                       # number of overall hits
+system.l2c.overall_hits::total                2417961                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             7821                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data            15227                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2184                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             4071                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker           21                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst             4840                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data            13473                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                47642                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data           650                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           279                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data           401                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1330                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          77547                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          22505                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          29870                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             129922                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              7821                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             92774                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2184                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             26576                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker           21                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              4840                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             43343                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                177564                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             7821                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            92774                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2184                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            26576                       # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker           21                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             4840                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            43343                       # number of overall misses
+system.l2c.overall_misses::total               177564                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.inst    158048000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    307638493                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      1706500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    369793991                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data   1035932237                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1873119221                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      4516343                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data      3653343                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      8169686                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1564766446                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   2136302067                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   3701068513                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    158048000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1872404939                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker      1706500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    369793991                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   3172234304                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      5574187734                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    158048000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1872404939                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker      1706500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    369793991                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   3172234304                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     5574187734                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        20605                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker        11271                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         347416                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         535895                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        10906                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         6430                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         153575                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         223619                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker        53752                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker         8985                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst         349886                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data         577132                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2299472                       # number of ReadReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1545523                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1545523                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data          891                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          252                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data          464                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1607                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       148858                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        57836                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        90144                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           296838                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        22061                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker        11621                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          351338                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          685425                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        10165                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5243                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          141332                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          282899                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker        54214                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        10721                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          361013                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          668452                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2604484                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        22061                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker        11621                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         351338                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         685425                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        10165                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5243                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         141332                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         282899                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker        54214                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        10721                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         361013                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         668452                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2604484                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000344                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.019548                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.031131                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010847                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.017275                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000480                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000187                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.018703                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.021176                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.020810                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.846240                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.817460                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.799569                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.828251                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.502909                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.400045                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.356629                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.438445                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000344                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.019548                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.133590                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010847                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.095529                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000480                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.000187                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.018703                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.066413                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.068409                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000344                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.019548                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.133590                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010847                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.095529                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000480                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.000187                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.018703                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.066413                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.068409                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73375.896934                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 75372.426955                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 80923.076923                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77745.776955                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 77292.053813                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 39132.170481                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data        14451                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 13008.894879                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  5862.664162                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68481.281713                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71029.522801                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 29719.536478                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 73375.896934                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 69472.688659                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 80923.076923                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker        74500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 77745.776955                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 72757.030004                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 32256.568092                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 73375.896934                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 69472.688659                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 80923.076923                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker        74500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 77745.776955                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 72757.030004                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 32256.568092                       # average overall miss latency
+system.l2c.Writeback_accesses::writebacks      1542066                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1542066                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data          785                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          331                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data          473                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1589                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       143716                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        61827                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        90508                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           296051                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        20605                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker        11273                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          347416                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          679611                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        10906                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6430                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          153575                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          285446                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        53752                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker         8985                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          349886                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          667640                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2595525                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        20605                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker        11273                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         347416                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         679611                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        10906                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         6430                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         153575                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         285446                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker        53752                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker         8985                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         349886                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         667640                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2595525                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000444                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.022512                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.028414                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.014221                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.018205                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000391                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.013833                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.023345                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.020719                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.828025                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.842900                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.847780                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.837004                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.539585                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.364000                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.330026                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.438850                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000444                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.022512                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.136510                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.014221                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.093103                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000391                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.013833                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.064920                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.068412                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000444                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.022512                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.136510                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.014221                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.093103                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000391                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.013833                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.064920                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.068412                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72366.300366                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 75568.286170                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 81261.904762                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76403.717149                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 76889.500260                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 39316.553062                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16187.609319                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data  9110.581047                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6142.621053                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69529.724328                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71519.988852                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 28486.849902                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 72366.300366                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 70454.731299                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 81261.904762                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 76403.717149                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 73189.080221                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 31392.555552                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 72366.300366                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 70454.731299                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 81261.904762                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 76403.717149                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 73189.080221                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 31392.555552                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -641,131 +627,119 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95814                       # number of writebacks
-system.l2c.writebacks::total                    95814                       # number of writebacks
+system.l2c.writebacks::writebacks               95261                       # number of writebacks
+system.l2c.writebacks::total                    95261                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu2.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.inst         1533                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         3888                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           26                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         6751                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data        12246                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           24446                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          206                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          371                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          577                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        23137                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        32148                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         55285                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1533                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        27025                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           26                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         6751                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        44394                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            79731                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1533                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        27025                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           26                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         6751                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        44394                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           79731                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     93050250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    244480004                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      1780500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    440173014                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data    793487001                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1573095769                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      2610195                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      3849868                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      6460063                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1288379085                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1870619355                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   3158998440                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     93050250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1532859089                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      1780500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    440173014                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   2664106356                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   4732094209                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     93050250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1532859089                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      1780500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker       125000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    440173014                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   2664106356                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   4732094209                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28007446000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30457930500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  58465376500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    376483500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    742130500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1118614000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28383929500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31200061000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  59583990500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010847                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017275                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000480                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000187                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.018700                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.021176                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.010593                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.817460                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.799569                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.359054                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.400045                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.356629                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.186246                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010847                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.095529                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000480                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000187                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.018700                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.066413                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.030613                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010847                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.095529                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000480                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000187                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.018700                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.066413                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.030613                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60698.140900                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62880.659465                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 68480.769231                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65201.157458                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64795.606810                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 64349.822834                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12670.849515                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10377.002695                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11195.949740                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55684.794269                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58187.736562                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 57140.244913                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60698.140900                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56720.040296                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 68480.769231                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65201.157458                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60010.504933                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59350.744491                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60698.140900                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56720.040296                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 68480.769231                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65201.157458                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60010.504933                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59350.744491                       # average overall mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu1.inst         2184                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         4071                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           21                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         4839                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data        13473                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           24588                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          279                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data          401                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          680                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        22505                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        29870                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         52375                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2184                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        26576                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker           21                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         4839                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        43343                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            76963                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2184                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        26576                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           21                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         4839                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        43343                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           76963                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    130319000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    256773507                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      1447000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    309153509                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    867568261                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1565261277                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      3390267                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      4022901                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      7413168                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1276355554                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1752679887                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   3029035441                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    130319000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1533129061                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      1447000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    309153509                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   2620248148                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   4594296718                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    130319000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1533129061                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      1447000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    309153509                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   2620248148                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   4594296718                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28014543000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30421291000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  58435834000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    368226500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    707215000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1075441500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28382769500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31128506000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  59511275500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014221                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.018205                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000391                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.013830                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.023345                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.010693                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.842900                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.847780                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.427942                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.364000                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.330026                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.176912                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014221                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.093103                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000391                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.013830                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.064920                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.029652                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014221                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.093103                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000391                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.013830                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.064920                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.029652                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59669.871795                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63073.816507                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 68904.761905                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63887.891920                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64393.101833                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 63659.560639                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12151.494624                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10032.172070                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10901.717647                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56714.310331                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58676.929595                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 57833.612239                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59669.871795                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57688.480622                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 68904.761905                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63887.891920                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60453.779111                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59694.875694                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59669.871795                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57688.480622                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 68904.761905                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63887.891920                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60453.779111                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59694.875694                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -776,44 +750,44 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                47572                       # number of replacements
-system.iocache.tags.tagsinuse                0.107425                       # Cycle average of tags in use
+system.iocache.tags.replacements                47575                       # number of replacements
+system.iocache.tags.tagsinuse                0.089403                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47588                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47591                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000219024509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.107425                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006714                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.006714                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5000209950509                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.089403                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005588                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005588                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428643                       # Number of tag accesses
-system.iocache.tags.data_accesses              428643                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          907                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428670                       # Number of tag accesses
+system.iocache.tags.data_accesses              428670                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          910                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              910                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47627                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47627                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47627                       # number of overall misses
-system.iocache.overall_misses::total            47627                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    128792785                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    128792785                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   5668191006                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   5668191006                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   5796983791                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5796983791                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   5796983791                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5796983791                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          907                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47630                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47630                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47630                       # number of overall misses
+system.iocache.overall_misses::total            47630                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    131527041                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    131527041                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   5824382656                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   5824382656                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   5955909697                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5955909697                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   5955909697                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5955909697                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          910                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            910                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47627                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47627                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47627                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47627                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47630                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47630                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47630                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47630                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -822,56 +796,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 141998.660419                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 141998.660419                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 121322.581464                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 121322.581464                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 121716.332983                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 121716.332983                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 121716.332983                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 121716.332983                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         88529                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144535.209890                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 144535.209890                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 124665.724658                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 124665.724658                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 125045.343208                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125045.343208                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 125045.343208                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125045.343208                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         88795                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7334                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 8200                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.071039                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.828659                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          744                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          744                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        22928                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        22928                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        23672                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        23672                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        23672                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        23672                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     90079785                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     90079785                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4474936508                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   4474936508                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4565016293                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4565016293                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4565016293                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4565016293                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.820287                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.820287                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide     0.490753                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total     0.490753                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.497029                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.497029                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.497029                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.497029                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121074.979839                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 121074.979839                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195173.434578                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 195173.434578                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 192844.554453                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 192844.554453                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          733                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          733                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        24176                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        24176                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        24909                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        24909                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        24909                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        24909                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     93385041                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     93385041                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4566242660                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   4566242660                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4659627701                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4659627701                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4659627701                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4659627701                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.805495                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.805495                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide     0.517466                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total     0.517466                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.522969                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.522969                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.522969                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.522969                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127401.147340                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 127401.147340                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 188875.027300                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 188875.027300                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 187066.028383                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 187066.028383                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -885,476 +859,510 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    52329028                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            1794981                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           1794440                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              6370                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             6370                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           902417                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             716                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            716                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           170908                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          147982                       # Transaction distribution
+system.toL2Bus.throughput                    52260442                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            1795853                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           1795321                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq              6118                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp             6118                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           903975                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq             804                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            804                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           176511                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          152342                       # Transaction distribution
 system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1004724                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3613728                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        35279                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       136436                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               4790167                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     32150080                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119808027                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       127712                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       515032                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          152600851                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             268845429                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          114024                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         5038805323                       # Layer occupancy (ticks)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1006951                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3618137                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        34540                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       139444                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               4799072                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     32221504                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    120018356                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       123320                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       517264                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          152880444                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             268161042                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          137520                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         5048228823                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           931500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           945000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2262930320                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2267749080                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4696428413                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4703679799                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          19332464                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          19140467                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          72173756                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          74891774                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                       1276348                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq               149977                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              149977                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               28411                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              28411                       # Transaction distribution
-system.iobus.trans_dist::MessageReq               885                       # Transaction distribution
-system.iobus.trans_dist::MessageResp              885                       # Transaction distribution
+system.iobus.throughput                       1277477                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               149797                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              149797                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               29441                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              29441                       # Transaction distribution
+system.iobus.trans_dist::MessageReq               850                       # Transaction distribution
+system.iobus.trans_dist::MessageResp              850                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio         5752                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio         5466                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio          582                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           50                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio          558                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           38                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           18                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       287032                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio          332                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       287110                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio          224                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio           86                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        13448                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        13026                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio            4                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2064                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       309432                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        47344                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        47344                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         1770                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         1770                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  358546                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       308658                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        49818                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        49818                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         1700                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         1700                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  360176                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         3245                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         3084                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf            4                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          291                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           25                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          279                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           19                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           12                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio            9                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       143516                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio          664                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       143555                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio          448                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           43                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio         6724                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio         6513                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            2                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4128                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total       158682                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      1503808                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      1503808                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3540                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         3540                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              1666030                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 6560144                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              2116890                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total       158115                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      1583592                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      1583592                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3400                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         3400                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              1745107                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 6558405                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              2044244                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                28000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              4753000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              4518000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy               383000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy               367000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                42000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                33000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer7.occupancy                21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            143517000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            143556000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              264000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              178000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer11.occupancy               86000                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            10048000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy             9750000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                4000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           209101042                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           220209699                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy             1032000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           303949000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           303393000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            28759251                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            30099002                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy              885000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy              850000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                      1144797664                       # number of cpu cycles simulated
+system.cpu0.numCycles                      1160444400                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   72999922                       # Number of instructions committed
-system.cpu0.committedOps                    148305710                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            136279674                       # Number of integer alu accesses
+system.cpu0.committedInsts                   72635405                       # Number of instructions committed
+system.cpu0.committedOps                    147758080                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            135731001                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1016299                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14345558                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   136279674                       # number of integer instructions
+system.cpu0.num_func_calls                    1010341                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14309822                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   135731001                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          250792350                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         116890419                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          249546871                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         116495894                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            84577193                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           56435831                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     14370687                       # number of memory refs
-system.cpu0.num_load_insts                   10454117                       # Number of load instructions
-system.cpu0.num_store_insts                   3916570                       # Number of store instructions
-system.cpu0.num_idle_cycles              1087719763.352511                       # Number of idle cycles
-system.cpu0.num_busy_cycles              57077900.647489                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.049859                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.950141                       # Percentage of idle cycles
-system.cpu0.Branches                         15728655                       # Number of branches fetched
+system.cpu0.num_cc_register_reads            84252648                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           56217158                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     14168966                       # number of memory refs
+system.cpu0.num_load_insts                   10366088                       # Number of load instructions
+system.cpu0.num_store_insts                   3802878                       # Number of store instructions
+system.cpu0.num_idle_cycles              1101978015.213226                       # Number of idle cycles
+system.cpu0.num_busy_cycles              58466384.786774                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.050383                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.949617                       # Percentage of idle cycles
+system.cpu0.Branches                         15683494                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass               100234      0.07%      0.07% # Class of executed instruction
+system.cpu0.op_class::IntAlu                133376064     90.27%     90.33% # Class of executed instruction
+system.cpu0.op_class::IntMult                   62929      0.04%     90.38% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    50413      0.03%     90.41% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.41% # Class of executed instruction
+system.cpu0.op_class::MemRead                10366088      7.02%     97.43% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3802878      2.57%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                 147758606                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           853193                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.838528                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          129757026                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           853705                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           151.992815                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     147468978000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   295.878537                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   138.959383                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    76.000608                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.577888                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.271405                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.148439                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997732                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           850385                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.795763                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          129494150                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           850897                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           152.185458                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle     147465545000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   306.120317                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   137.033154                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    67.642292                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.597891                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.267643                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.132114                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997648                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          183                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          228                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        131484548                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       131484548                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     88843413                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     38144708                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2768905                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      129757026                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     88843413                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     38144708                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2768905                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       129757026                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     88843413                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     38144708                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2768905                       # number of overall hits
-system.cpu0.icache.overall_hits::total      129757026                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       351339                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       141332                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       381133                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       873804                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       351339                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       141332                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       381133                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        873804                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       351339                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       141332                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       381133                       # number of overall misses
-system.cpu0.icache.overall_misses::total       873804                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1941508750                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5443063468                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   7384572218                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1941508750                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   5443063468                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   7384572218                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1941508750                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   5443063468                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   7384572218                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     89194752                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     38286040                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3150038                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    130630830                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     89194752                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     38286040                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3150038                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    130630830                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     89194752                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     38286040                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3150038                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    130630830                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003939                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.003691                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.120993                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.006689                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003939                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.003691                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.120993                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.006689                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003939                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.003691                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.120993                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.006689                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13737.219809                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14281.270496                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8451.062501                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13737.219809                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14281.270496                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8451.062501                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13737.219809                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14281.270496                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8451.062501                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4847                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        131214877                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       131214877                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     88330268                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     38415628                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2748254                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      129494150                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     88330268                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     38415628                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2748254                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       129494150                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     88330268                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     38415628                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2748254                       # number of overall hits
+system.cpu0.icache.overall_hits::total      129494150                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       347417                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       153575                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       368828                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       869820                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       347417                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       153575                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       368828                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        869820                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       347417                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       153575                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       368828                       # number of overall misses
+system.cpu0.icache.overall_misses::total       869820                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2140572500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5126974995                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7267547495                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2140572500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   5126974995                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7267547495                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2140572500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   5126974995                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7267547495                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     88677685                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     38569203                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3117082                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    130363970                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     88677685                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     38569203                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      3117082                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    130363970                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     88677685                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     38569203                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3117082                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    130363970                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003918                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.003982                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.118325                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.006672                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003918                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.003982                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.118325                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.006672                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003918                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.003982                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.118325                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.006672                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13938.287482                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13900.720648                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8355.231536                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13938.287482                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13900.720648                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8355.231536                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13938.287482                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13900.720648                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8355.231536                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         2303                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              200                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              142                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.235000                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.218310                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        20086                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        20086                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        20086                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        20086                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        20086                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        20086                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       141332                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       361047                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       502379                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       141332                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       361047                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       502379                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       141332                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       361047                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       502379                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1658307250                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4510414171                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6168721421                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1658307250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4510414171                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6168721421                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1658307250                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4510414171                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6168721421                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.003691                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.114617                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.003846                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.003691                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.114617                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.003846                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.003691                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.114617                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.003846                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11733.416707                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12492.595621                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12279.019268                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11733.416707                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12492.595621                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12279.019268                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11733.416707                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12492.595621                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12279.019268                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        18913                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        18913                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        18913                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        18913                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        18913                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        18913                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       153575                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       349915                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       503490                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       153575                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       349915                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       503490                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       153575                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       349915                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       503490                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1832623500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4249045164                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6081668664                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1832623500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4249045164                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6081668664                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1832623500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4249045164                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6081668664                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.003982                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.112257                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.003862                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.003982                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.112257                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.003862                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.003982                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.112257                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.003862                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11933.084812                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12143.078073                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12079.025728                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11933.084812                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12143.078073                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12079.025728                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11933.084812                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12143.078073                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12079.025728                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1636224                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999323                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19637131                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1636736                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            11.997739                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1632172                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999414                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19616448                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1632684                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            12.014847                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   276.200499                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   230.134495                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.664329                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.539454                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.449481                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.011063                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   243.807235                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   263.156885                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.035294                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.476186                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.513978                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.009835                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          259                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88232962                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88232962                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5302290                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2343807                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      3905907                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11552004                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3762855                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1548346                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2772193                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8083394                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9065145                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      3892153                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6678100                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19635398                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9065145                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      3892153                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6678100                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19635398                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       536567                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       225063                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       936224                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1697854                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       149749                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        58088                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       107958                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       315795                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       686316                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       283151                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1044182                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2013649                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       686316                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       283151                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1044182                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2013649                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3188254504                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  14965969569                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  18154224073                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2125358780                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3377412183                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   5502770963                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   5313613284                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  18343381752                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  23656995036                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   5313613284                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  18343381752                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  23656995036                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5838857                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2568870                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4842131                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13249858                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3912604                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1606434                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2880151                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8399189                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      9751461                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      4175304                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7722282                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21649047                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      9751461                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4175304                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7722282                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21649047                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.091896                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.087612                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.193350                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.128141                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038273                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.036160                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.037483                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.037598                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.070381                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.067816                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.135217                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.093013                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070381                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.067816                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.135217                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.093013                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14166.053523                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15985.458148                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10692.452987                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36588.603154                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31284.501223                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17425.136443                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18766.005714                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17567.226549                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 11748.321101                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18766.005714                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17567.226549                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11748.321101                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       168342                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88185531                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88185531                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5216887                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      2373281                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      3941483                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       11531651                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3654093                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      1632237                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      2796808                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       8083138                       # number of WriteReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      8870980                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      4005518                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      6738291                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        19614789                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      8870980                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      4005518                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      6738291                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       19614789                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       535895                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       223619                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       948939                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1708453                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       144501                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        62158                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       108308                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       314967                       # number of WriteReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       680396                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       285777                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1057247                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2023420                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       680396                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       285777                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1057247                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2023420                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3182430507                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  15408252283                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  18590682790                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2166727821                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3257890503                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   5424618324                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   5349158328                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  18666142786                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  24015301114                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   5349158328                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  18666142786                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  24015301114                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5752782                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      2596900                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4890422                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13240104                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3798594                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1694395                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2905116                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      8398105                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      9551376                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      4291295                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7795538                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     21638209                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      9551376                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      4291295                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7795538                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     21638209                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.093154                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.086110                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.194040                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.129036                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038041                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.036684                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.037282                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.037505                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.071235                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.066595                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.135622                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.093511                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.071235                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.066595                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.135622                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.093511                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14231.485281                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16237.347483                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10881.588659                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34858.390247                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30079.869474                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17222.814847                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18717.945559                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17655.422797                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 11868.668449                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18717.945559                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17655.422797                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 11868.668449                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       173678                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            11795                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            11797                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.272319                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.722218                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1545523                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1545523                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       357871                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       357871                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        17395                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        17395                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       375266                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       375266                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       375266                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       375266                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       225063                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       578353                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       803416                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        58088                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        90563                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       148651                       # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       283151                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       668916                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       952067                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       283151                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       668916                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       952067                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2737161496                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   8309689554                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  11046851050                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1998659220                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2996226317                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4994885537                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4735820716                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11305915871                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  16041736587                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4735820716                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11305915871                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16041736587                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30467694000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33225580500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63693274500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    404660000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    790542000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1195202000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  30872354000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34016122500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64888476500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.087612                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.119442                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.060636                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036160                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031444                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017698                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.067816                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.086622                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.043977                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.067816                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086622                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.043977                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12161.756913                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14367.850697                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13749.851945                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34407.437336                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33084.441958                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33601.425735                       # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16725.424653                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16901.846975                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16849.377814                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16725.424653                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16901.846975                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16849.377814                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      1542066                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1542066                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       371761                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       371761                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        17373                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        17373                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       389134                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       389134                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       389134                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       389134                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       223619                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       577178                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       800797                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        62158                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        90935                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       153093                       # number of WriteReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       285777                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       668113                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       953890                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       285777                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       668113                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       953890                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2734176493                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   8368429033                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  11102605526                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2032053179                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2876927496                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4908980675                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4766229672                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11245356529                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  16011586201                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4766229672                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11245356529                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16011586201                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30475246000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33186567000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63661813000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    395642000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    753351500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1148993500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  30870888000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33939918500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64810806500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.086110                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.118022                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.060483                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036684                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031302                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018229                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.066595                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.085705                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.044084                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.066595                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.085705                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.044084                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12226.941776                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14498.870423                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13864.444455                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32691.740066                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31637.185858                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32065.350310                       # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16678.143000                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16831.518813                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16785.568777                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16678.143000                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16831.518813                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16785.568777                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1365,307 +1373,377 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2608015730                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2606021866                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   34716890                       # Number of instructions committed
-system.cpu1.committedOps                     67541836                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             62669042                       # Number of integer alu accesses
+system.cpu1.committedInsts                   34914128                       # Number of instructions committed
+system.cpu1.committedOps                     67869824                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             62995293                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     430919                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6413966                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    62669042                       # number of integer instructions
+system.cpu1.num_func_calls                     438942                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6428622                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    62995293                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          115548964                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          54160900                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          116271698                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          54373004                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            35562537                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           26614034                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4364452                       # number of memory refs
-system.cpu1.num_load_insts                    2756893                       # Number of load instructions
-system.cpu1.num_store_insts                   1607559                       # Number of store instructions
-system.cpu1.num_idle_cycles              2483429860.768801                       # Number of idle cycles
-system.cpu1.num_busy_cycles              124585869.231199                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.047770                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.952230                       # Percentage of idle cycles
-system.cpu1.Branches                          7003911                       # Number of branches fetched
+system.cpu1.num_cc_register_reads            35773637                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           26686134                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4480510                       # number of memory refs
+system.cpu1.num_load_insts                    2784988                       # Number of load instructions
+system.cpu1.num_store_insts                   1695522                       # Number of store instructions
+system.cpu1.num_idle_cycles              2483027078.364504                       # Number of idle cycles
+system.cpu1.num_busy_cycles              122994787.635496                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.047196                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.952804                       # Percentage of idle cycles
+system.cpu1.Branches                          7029914                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                31008      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 63308001     93.28%     93.32% # Class of executed instruction
+system.cpu1.op_class::IntMult                   28040      0.04%     93.37% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    22580      0.03%     93.40% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.40% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2784988      4.10%     97.50% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1695522      2.50%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                  67870139                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               28782114                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         28782114                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           316524                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26348266                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               25752004                       # Number of BTB hits
+system.cpu2.branchPred.lookups               28758894                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         28758894                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           306803                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26351534                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               25737629                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.736997                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 537542                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             63717                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       155552038                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.670325                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 530881                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             61512                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       154845080                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9686701                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     141772190                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   28782114                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26289546                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     54340809                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                1470890                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     70055                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles              24627328                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles                4722                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             7901                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        23768                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.IcacheWaitRetryStallCycles          376                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3150040                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               144648                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2015                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          89899907                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             3.110146                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.408280                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9460785                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     141747704                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   28758894                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26268510                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     54302787                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                1434244                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     58972                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles              24471854                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles                4161                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             6545                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        20028                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.IcacheWaitRetryStallCycles          224                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3117082                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               139514                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   1749                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          89437217                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             3.124405                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.409858                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                35694732     39.70%     39.70% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  594255      0.66%     40.37% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23712499     26.38%     66.74% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  314699      0.35%     67.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  599600      0.67%     67.76% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  812421      0.90%     68.66% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  338881      0.38%     69.04% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  517837      0.58%     69.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27314983     30.38%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                35270123     39.44%     39.44% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  589507      0.66%     40.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23704151     26.50%     66.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  307246      0.34%     66.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  603965      0.68%     67.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  802586      0.90%     68.51% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  334965      0.37%     68.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  517417      0.58%     69.47% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27307257     30.53%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            89899907                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.185032                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.911413                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                11154829                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             23540580                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 30801007                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              1287318                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               1141583                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             278785410                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                   11                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               1141583                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                12143079                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               13933433                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4524497                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 30930733                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              5252059                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             277791777                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                 7238                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               2464468                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents              2117220                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands          331976691                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            604531856                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       371338716                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups               38                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            321781805                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                10194886                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            148461                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        149473                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 11392573                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6171654                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3395563                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           345995                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          292325                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 276091246                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             414813                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                274477250                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            60541                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        7173454                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     11041443                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         56132                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     89899907                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        3.053143                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.400877                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            89437217                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.185727                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.915416                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                10926187                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             23367960                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 31523393                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              1298286                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles               1115198                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             278635226                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                   49                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles               1115198                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                11921655                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               13834152                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4411879                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 31656208                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              5292001                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             277656292                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 6764                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               2483668                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents              2130930                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands          331880087                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            604361998                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       371268132                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups                6                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            321920244                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 9959841                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            147988                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        148926                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 11485411                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6218482                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3410117                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           341148                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          274139                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 276004640                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             412430                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                274449569                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            59781                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        7023554                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     10820295                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         55045                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     89437217                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        3.068628                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.396853                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           26563563     29.55%     29.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            6130901      6.82%     36.37% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3934206      4.38%     40.74% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            2710119      3.01%     43.76% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           25036419     27.85%     71.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            1342117      1.49%     73.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           23840310     26.52%     99.62% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             288717      0.32%     99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              53555      0.06%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           26098480     29.18%     29.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            6131096      6.86%     36.04% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3936751      4.40%     40.44% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            2730796      3.05%     43.49% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           25025448     27.98%     71.47% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            1337810      1.50%     72.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           23830586     26.65%     99.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             291775      0.33%     99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              54475      0.06%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       89899907                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       89437217                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                 122290     33.50%     33.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                   245      0.07%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     33.57% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                189949     52.03%     85.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                52573     14.40%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                 125312     33.75%     33.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                   120      0.03%     33.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                    109      0.03%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     33.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                191005     51.44%     85.24% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                54802     14.76%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            80536      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            264658650     96.42%     96.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               54855      0.02%     96.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                48402      0.02%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6455691      2.35%     98.84% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3179116      1.16%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            76601      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            264560846     96.40%     96.42% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               54414      0.02%     96.44% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                50942      0.02%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             6508971      2.37%     98.83% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3197795      1.17%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             274477250                       # Type of FU issued
-system.cpu2.iq.rate                          1.764537                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     365057                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001330                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         639321511                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        283683445                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    273115126                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                 61                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes                70                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses           18                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             274761742                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                     29                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          634301                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             274449569                       # Type of FU issued
+system.cpu2.iq.rate                          1.772414                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     371348                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001353                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         638809448                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        283444416                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    273102485                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                 12                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes                 6                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             274744310                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                      6                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          641561                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1002623                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         6718                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         4440                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       510444                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       993516                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         6753                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         4280                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       500329                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       656391                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        10280                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       656426                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        10045                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               1141583                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                9227965                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               815382                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          276506059                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            71664                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6171654                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3395563                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            234992                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                633068                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents                 3849                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          4440                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        176570                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       182317                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              358887                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            273973436                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6342946                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           503814                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles               1115198                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                9119918                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               823405                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          276417070                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            70631                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6218482                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3410117                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            233790                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                637954                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                 3900                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          4280                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        173413                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       173644                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              347057                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            273959168                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              6398525                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           490400                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     9455734                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                27867681                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3112788                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.761298                       # Inst execution rate
-system.cpu2.iew.wb_sent                     273823666                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    273115144                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                212986974                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                348231532                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                     9531292                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                27864904                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3132767                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.769247                       # Inst execution rate
+system.cpu2.iew.wb_sent                     273810478                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    273102491                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                212979431                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                348314367                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.755780                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.611625                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.763714                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.611457                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        7474898                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         358681                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           318992                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     88758324                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     3.031021                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.870805                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        7316358                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         357385                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           309115                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     88322018                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     3.046767                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.870309                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     31301057     35.27%     35.27% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4393147      4.95%     40.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1229186      1.38%     41.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24655081     27.78%     69.38% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       868070      0.98%     70.36% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       585819      0.66%     71.02% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       347474      0.39%     71.41% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23302544     26.25%     97.66% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2075946      2.34%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     30852434     34.93%     34.93% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4395307      4.98%     39.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1238857      1.40%     41.31% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24650858     27.91%     69.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       865215      0.98%     70.20% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       585749      0.66%     70.86% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       347954      0.39%     71.26% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23291491     26.37%     97.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      2094153      2.37%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     88758324                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           136214259                       # Number of instructions committed
-system.cpu2.commit.committedOps             269028357                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     88322018                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           136303075                       # Number of instructions committed
+system.cpu2.commit.committedOps             269096585                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8054150                       # Number of memory references committed
-system.cpu2.commit.loads                      5169031                       # Number of loads committed
-system.cpu2.commit.membars                     165004                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27530478                       # Number of branches committed
+system.cpu2.commit.refs                       8134753                       # Number of memory references committed
+system.cpu2.commit.loads                      5224965                       # Number of loads committed
+system.cpu2.commit.membars                     164376                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27532187                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                245624895                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              430032                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events              2075946                       # number cycles where commit BW limit reached
+system.cpu2.commit.int_insts                245708361                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              429087                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        43848      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       260815603     96.92%     96.94% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          52558      0.02%     96.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           49823      0.02%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.98% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5224965      1.94%     98.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2909788      1.08%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::total        269096585                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              2094153                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   363157720                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  554152180                       # The number of ROB writes
-system.cpu2.timesIdled                         477715                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       65652131                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4906975665                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  136214259                       # Number of Instructions Simulated
-system.cpu2.committedOps                    269028357                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total            136214259                       # Number of Instructions Simulated
-system.cpu2.cpi                              1.141966                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.141966                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.875683                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.875683                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               364409735                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              218808578                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    73042                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   73024                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                139320542                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               107246688                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               88724841                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                132896                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                   362613065                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  553944877                       # The number of ROB writes
+system.cpu2.timesIdled                         473034                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                       65407863                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4900873955                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  136303075                       # Number of Instructions Simulated
+system.cpu2.committedOps                    269096585                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total            136303075                       # Number of Instructions Simulated
+system.cpu2.cpi                              1.136035                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.136035                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.880254                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.880254                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               364552649                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              218803003                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    72918                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                139316304                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               107298284                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               88761943                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                132629                       # number of misc regfile writes
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 7e42f0dae..0e2c469d2 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.026923                       # Number of seconds simulated
-sim_ticks                                 26922512500                       # Number of ticks simulated
-final_tick                                26922512500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.026909                       # Number of seconds simulated
+sim_ticks                                 26909234500                       # Number of ticks simulated
+final_tick                                26909234500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 143955                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144989                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               42782119                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 446112                       # Number of bytes of host memory used
-host_seconds                                   629.29                       # Real time elapsed on the host
+host_inst_rate                                 142304                       # Simulator instruction rate (inst/s)
+host_op_rate                                   143325                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               42270537                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 446544                       # Number of bytes of host memory used
+host_seconds                                   636.60                       # Real time elapsed on the host
 sim_insts                                    90589798                       # Number of instructions simulated
 sim_ops                                      91240351                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             45248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             44992                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            947648                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               992896                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        45248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           45248                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                707                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               992640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        44992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           44992                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                703                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14807                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15514                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1680675                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             35199092                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36879767                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1680675                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1680675                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1680675                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            35199092                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               36879767                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         15514                       # Number of read requests accepted
+system.physmem.num_reads::total                 15510                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1671991                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             35216461                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                36888452                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1671991                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1671991                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1671991                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            35216461                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               36888452                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         15510                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       15514                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       15510                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   992896                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   992640                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    992896                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    992640                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              1                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 988                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 886                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs              3                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 987                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 885                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 942                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1050                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1049                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1105                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                1078                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                1078                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 956                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                938                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 957                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                935                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                904                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                905                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                865                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                877                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                896                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     26922312500                       # Total gap between requests
+system.physmem.totGap                     26909036500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15514                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   15510                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10767                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4517                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       211                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     10635                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4635                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       219                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -186,72 +186,74 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          880                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      935.927273                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     827.602742                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     262.440032                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             41      4.66%      4.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           26      2.95%      7.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           13      1.48%      9.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            4      0.45%      9.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            5      0.57%     10.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      0.23%     10.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      0.23%     10.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      0.11%     10.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          786     89.32%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            880                       # Bytes accessed per row activation
-system.physmem.totQLat                      108095000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 369557500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     77570000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                   183892500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6967.58                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    11853.33                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples         1363                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      726.491563                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     533.334896                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     387.223532                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            140     10.27%     10.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          158     11.59%     21.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           56      4.11%     25.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           68      4.99%     30.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           57      4.18%     35.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           39      2.86%     38.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           24      1.76%     39.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           39      2.86%     42.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          782     57.37%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1363                       # Bytes accessed per row activation
+system.physmem.totQLat                       83369750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 374182250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     77550000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5375.23                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23820.90                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          36.88                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24125.23                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          36.89                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       36.88                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       36.89                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.29                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.29                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14141                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14137                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   91.15                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1735355.97                       # Average gap between requests
+system.physmem.avgGap                      1734947.55                       # Average gap between requests
 system.physmem.pageHitRate                      91.15                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               1.09                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     36879767                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 976                       # Transaction distribution
-system.membus.trans_dist::ReadResp                976                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               1                       # Transaction distribution
+system.physmem.memoryStateTime::IDLE      24303660500                       # Time in different power states
+system.physmem.memoryStateTime::REF         898300000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1704463000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     36888452                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 972                       # Transaction distribution
+system.membus.trans_dist::ReadResp                972                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                3                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14538                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14538                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31030                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  31030                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       992896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              992896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 992896                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31026                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  31026                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       992640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              992640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 992640                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            19225500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            19094500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          144897999                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          145899997                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                26688187                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          22005801                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            842567                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11378681                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11285656                       # Number of BTB hits
+system.cpu.branchPred.lookups                26684247                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          22003797                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            841589                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11372801                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                11278925                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.182462                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   69960                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                176                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.174557                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   69990                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                184                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -337,239 +339,239 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                         53845026                       # number of cpu cycles simulated
+system.cpu.numCycles                         53818470                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           14173388                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      127901014                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    26688187                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11355616                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      24038968                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4766662                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               11320590                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles           14166768                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      127874482                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    26684247                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11348915                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      24030832                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4761225                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               11326508                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                  107                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles             8                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13845523                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                330018                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           53440501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.409803                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.214653                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  13838942                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                329737                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           53427318                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.409937                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.214887                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 29439765     55.09%     55.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3390250      6.34%     61.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2029247      3.80%     65.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1554755      2.91%     68.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1667292      3.12%     71.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2920236      5.46%     76.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1512043      2.83%     79.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1089860      2.04%     81.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9837053     18.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 29434889     55.09%     55.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3387974      6.34%     61.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2027945      3.80%     65.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1552978      2.91%     68.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1665988      3.12%     71.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2918810      5.46%     76.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1512193      2.83%     79.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1089826      2.04%     81.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9836715     18.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             53440501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.495648                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.375354                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16937222                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9166719                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  22408314                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1029433                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3898813                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4444354                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  8681                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              126084070                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 42675                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3898813                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18718559                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 3593311                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         188330                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  21554671                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5486817                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              123168222                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 424808                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4599857                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents             1460                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           143625263                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             536555031                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        500037832                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               718                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             53427318                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.495820                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.376033                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 16930628                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9172800                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  22402161                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1027234                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3894495                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4441775                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  8644                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              126055074                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 42561                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3894495                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 18710503                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 3595532                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         186271                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  21547494                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5493023                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              123139917                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 426575                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4604902                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents             1527                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           143588109                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             536432016                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        499923969                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               641                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107414186                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 36211077                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4609                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           4607                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12545622                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             29481569                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5520172                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2131780                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1278964                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  118183319                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                8477                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 105169429                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             79348                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        26754797                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     65616265                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            259                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      53440501                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.967972                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.909350                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 36173923                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4624                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           4622                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12547663                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29472846                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5519091                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2169224                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1269381                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  118159243                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                8489                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 105145248                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             78272                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        26728441                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     65602174                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            271                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      53427318                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.968005                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.908888                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            15384800     28.79%     28.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            11651642     21.80%     50.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             8259769     15.46%     66.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6813523     12.75%     78.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4933870      9.23%     88.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2968386      5.55%     93.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2461371      4.61%     98.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              525076      0.98%     99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              442064      0.83%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            15370604     28.77%     28.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            11662585     21.83%     50.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             8230563     15.41%     66.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6832993     12.79%     78.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4979120      9.32%     88.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2926966      5.48%     93.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2444206      4.57%     98.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              536236      1.00%     99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              444045      0.83%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        53440501                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        53427318                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   46222      6.98%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     26      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 339934     51.34%     58.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                275932     41.67%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   46059      6.94%      6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     26      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 341162     51.43%     58.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                276052     41.62%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              74431142     70.77%     70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                10980      0.01%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt             132      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            172      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25611933     24.35%     95.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5115067      4.86%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              74418244     70.78%     70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10973      0.01%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt             122      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            157      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25603497     24.35%     95.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5112252      4.86%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              105169429                       # Type of FU issued
-system.cpu.iq.rate                           1.953187                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      662114                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006296                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          264520145                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         144951370                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    102696867                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 676                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                925                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          287                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              105831206                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     337                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           441415                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              105145248                       # Type of FU issued
+system.cpu.iq.rate                           1.953702                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      663299                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006308                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          264458762                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         144900942                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    102674293                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 623                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                845                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          263                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              105808235                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     312                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           440410                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6907603                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6432                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         6446                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       775328                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6898880                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6071                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         6331                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       774247                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         31602                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked         31563                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3898813                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  959371                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                127029                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           118204490                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            309594                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              29481569                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5520172                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               4589                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  66074                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  6711                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           6446                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         446623                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       445838                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               892461                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             104194994                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25292197                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            974435                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3894495                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  960394                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                127228                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           118180427                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            309851                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29472846                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5519091                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               4601                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  65954                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  6808                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           6331                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         446096                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       445462                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               891558                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             104169534                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25284727                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            975714                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12694                       # number of nop insts executed
-system.cpu.iew.exec_refs                     30350924                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 21328461                       # Number of branches executed
-system.cpu.iew.exec_stores                    5058727                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.935090                       # Inst execution rate
-system.cpu.iew.wb_sent                      102975092                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     102697154                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  62242577                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 104291686                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         12695                       # number of nop insts executed
+system.cpu.iew.exec_refs                     30339844                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 21324580                       # Number of branches executed
+system.cpu.iew.exec_stores                    5055117                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.935572                       # Inst execution rate
+system.cpu.iew.wb_sent                      102952816                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     102674556                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  62244775                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 104288684                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.907273                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.596812                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.907794                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.596851                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        26954537                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        26930418                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            833969                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     49541688                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.841943                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.539958                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            833018                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     49532823                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.842273                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.541112                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     20036957     40.44%     40.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13159597     26.56%     67.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4169965      8.42%     75.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3431804      6.93%     82.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1536139      3.10%     85.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       734203      1.48%     86.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       944467      1.91%     88.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       252800      0.51%     89.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5275756     10.65%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     20056290     40.49%     40.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13134081     26.52%     67.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4165062      8.41%     75.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3431851      6.93%     82.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1531687      3.09%     85.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       719294      1.45%     86.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       966848      1.95%     88.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       252784      0.51%     89.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5274926     10.65%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     49541688                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     49532823                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             90602407                       # Number of instructions committed
 system.cpu.commit.committedOps               91252960                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -580,237 +582,274 @@ system.cpu.commit.branches                   18732304                       # Nu
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  72525674                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                56148                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5275756                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         63923653     70.05%     70.05% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           10474      0.01%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            6      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc           15      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            2      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.06% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        22573966     24.74%     94.80% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        4744844      5.20%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total          91252960                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5274926                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    162467695                       # The number of ROB reads
-system.cpu.rob.rob_writes                   240333520                       # The number of ROB writes
-system.cpu.timesIdled                           46195                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          404525                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    162435541                       # The number of ROB reads
+system.cpu.rob.rob_writes                   240280947                       # The number of ROB writes
+system.cpu.timesIdled                           46113                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          391152                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589798                       # Number of Instructions Simulated
 system.cpu.committedOps                      91240351                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              90589798                       # Number of Instructions Simulated
-system.cpu.cpi                               0.594383                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.594383                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.682417                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.682417                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                495621667                       # number of integer regfile reads
-system.cpu.int_regfile_writes               120557380                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       149                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      361                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                29211256                       # number of misc regfile reads
+system.cpu.cpi                               0.594090                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.594090                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.683247                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.683247                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                495503749                       # number of integer regfile reads
+system.cpu.int_regfile_writes               120538753                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       136                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      324                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                29202777                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              4495994050                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         904654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        904654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       942932                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        43718                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        43718                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1467                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2838210                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2839677                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        46912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120996480                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      121043392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         121043392                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus           64                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     1888584500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput              4498112646                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         904542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        904541                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       942913                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq            4                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            4                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        43808                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        43808                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1459                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2838157                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2839616                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        46528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120993984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      121040512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         121040512                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus          256                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     1888546500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          7.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1216499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1214249                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1423941741                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1424437743                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          5.3                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           632.458088                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13844537                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               733                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          18887.499318                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                 4                       # number of replacements
+system.cpu.icache.tags.tagsinuse           629.782020                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13837957                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               727                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          19034.328748                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   632.458088                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.308817                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.308817                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          730                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   629.782020                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.307511                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.307511                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          723                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           14                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          676                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.356445                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          27691778                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         27691778                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     13844537                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13844537                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13844537                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13844537                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13844537                       # number of overall hits
-system.cpu.icache.overall_hits::total        13844537                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          985                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           985                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          985                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            985                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          985                       # number of overall misses
-system.cpu.icache.overall_misses::total           985                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     65965748                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     65965748                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     65965748                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     65965748                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     65965748                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     65965748                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13845522                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13845522                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13845522                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13845522                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13845522                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13845522                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          671                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.353027                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          27678613                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27678613                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13837957                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13837957                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13837957                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13837957                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13837957                       # number of overall hits
+system.cpu.icache.overall_hits::total        13837957                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          984                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           984                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          984                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            984                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          984                       # number of overall misses
+system.cpu.icache.overall_misses::total           984                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     66510498                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     66510498                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     66510498                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     66510498                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     66510498                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     66510498                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13838941                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13838941                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13838941                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13838941                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13838941                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13838941                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000071                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000071                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000071                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000071                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000071                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000071                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66970.302538                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 66970.302538                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 66970.302538                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 66970.302538                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 66970.302538                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 66970.302538                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          596                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67591.969512                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67591.969512                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67591.969512                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67591.969512                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67591.969512                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67591.969512                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          649                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    49.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    54.083333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          251                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          251                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          251                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          251                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          251                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          251                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          734                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          734                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          734                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          734                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          734                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          734                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     51030750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     51030750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     51030750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     51030750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     51030750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     51030750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          252                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          252                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          252                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          252                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          252                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          252                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          732                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          732                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          732                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          732                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          732                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          732                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50737500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     50737500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50737500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     50737500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50737500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     50737500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69524.182561                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69524.182561                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69524.182561                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69524.182561                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69524.182561                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69524.182561                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69313.524590                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69313.524590                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69313.524590                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69313.524590                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69313.524590                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69313.524590                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10726.796939                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1831454                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15497                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           118.181196                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        10725.417134                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1831324                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            15493                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           118.203318                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9879.688406                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   618.475949                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   228.632584                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.301504                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.018874                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.006977                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.327356                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15497                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  9880.636903                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   615.219172                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   229.561060                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.301533                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.018775                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.007006                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.327314                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15493                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          514                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1300                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13616                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.472931                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15189647                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15189647                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           25                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       903641                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         903666                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       942932                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       942932                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        29180                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        29180                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           25                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       932821                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          932846                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           25                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       932821                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         932846                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          708                       # number of ReadReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1303                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13611                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.472809                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15189406                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15189406                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst           24                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       903531                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         903555                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       942913                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       942913                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        29270                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        29270                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           24                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       932801                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          932825                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           24                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       932801                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         932825                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          704                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data          279                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          987                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::total          983                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            3                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            3                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        14538                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        14538                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          708                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          704                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data        14817                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         15525                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          708                       # number of overall misses
+system.cpu.l2cache.demand_misses::total         15521                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          704                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14817                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        15525                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     50040500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     21343000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     71383500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    975716500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    975716500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     50040500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    997059500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1047100000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     50040500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    997059500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1047100000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          733                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       903920                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       904653                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       942932                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       942932                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        43718                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        43718                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          733                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       947638                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       948371                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          733                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       947638                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       948371                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.965894                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_misses::total        15521                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     49767750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     21366250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     71134000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    972292000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    972292000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     49767750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    993658250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1043426000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     49767750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    993658250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1043426000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          728                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       903810                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       904538                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       942913                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       942913                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            4                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            4                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        43808                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        43808                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          728                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       947618                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       948346                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          728                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       947618                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       948346                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.967033                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000309                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001091                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.332540                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.332540                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.965894                       # miss rate for demand accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001087                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.750000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.331857                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.331857                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.967033                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.015636                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.016370                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965894                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.016366                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967033                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015636                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.016370                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70678.672316                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76498.207885                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72323.708207                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67114.905764                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67114.905764                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70678.672316                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67291.590740                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67446.054750                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70678.672316                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67291.590740                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67446.054750                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.016366                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70692.826705                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76581.541219                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72364.191251                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66879.350667                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66879.350667                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70692.826705                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67062.040224                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67226.725082                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70692.826705                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67062.040224                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67226.725082                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -828,191 +867,191 @@ system.cpu.l2cache.demand_mshr_hits::total           11                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           11                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          707                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          703                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          269                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          976                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          972                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            3                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            3                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14538                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14538                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          707                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          703                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data        14807                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15514                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          707                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15510                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          703                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14807                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15514                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     41129750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     17372750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58502500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        10001                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        10001                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    793837000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    793837000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     41129750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    811209750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    852339500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     41129750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    811209750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    852339500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.964529                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total        15510                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     40904000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     17399000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58303000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        30003                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    788854000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    788854000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     40904000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    806253000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    847157000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     40904000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    806253000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    847157000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965659                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000298                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001079                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.332540                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.332540                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.964529                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001075                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.750000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.750000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.331857                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.331857                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965659                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015625                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.016359                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.964529                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016355                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965659                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015625                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.016359                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58175.035361                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64582.713755                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59941.086066                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016355                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58184.921764                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64680.297398                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59982.510288                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54604.278443                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54604.278443                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58175.035361                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54785.557507                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54940.021916                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58175.035361                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54785.557507                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54940.021916                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54261.521530                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54261.521530                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58184.921764                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54450.800297                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54620.051580                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58184.921764                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54450.800297                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54620.051580                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            943542                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3671.682953                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28143982                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            947638                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.699086                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        8008531250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3671.682953                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.896407                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.896407                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            943522                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3671.877894                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28137275                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            947618                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.692635                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        8001790250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3671.877894                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.896455                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.896455                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          464                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3129                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          503                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          461                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3114                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          521                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          59988388                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         59988388                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23603660                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23603660                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4532519                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4532519                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         3912                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         3912                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          59974850                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         59974850                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23597129                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23597129                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4532332                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4532332                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         3919                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         3919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      28136179                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28136179                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28136179                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28136179                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1173928                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1173928                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       202462                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       202462                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      28129461                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28129461                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28129461                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28129461                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1173693                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1173693                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       202649                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       202649                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            7                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            7                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1376390                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1376390                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1376390                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1376390                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  13893768230                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13893768230                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8571552365                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8571552365                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      1376342                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1376342                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1376342                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1376342                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  13892857479                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13892857479                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8552070346                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8552070346                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       251500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       251500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22465320595                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22465320595                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22465320595                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22465320595                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24777588                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24777588                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  22444927825                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22444927825                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22444927825                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22444927825                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24770822                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24770822                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         3919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3926                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         3926                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     29512569                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     29512569                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     29512569                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     29512569                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047379                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.047379                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.042759                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.042759                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001786                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001786                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.046637                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.046637                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.046637                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.046637                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.281406                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.281406                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42336.598300                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42336.598300                       # average WriteReq miss latency
+system.cpu.dcache.demand_accesses::cpu.data     29505803                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     29505803                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     29505803                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     29505803                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047382                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.047382                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.042798                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.042798                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001783                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001783                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.046646                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.046646                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.046646                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.046646                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.875127                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.875127                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42201.394263                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42201.394263                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16321.915006                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16321.915006                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16321.915006                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16321.915006                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       154484                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16307.667589                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16307.667589                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16307.667589                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16307.667589                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       154301                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             23933                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             23947                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.454853                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.443438                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       942932                       # number of writebacks
-system.cpu.dcache.writebacks::total            942932                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       269988                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       269988                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158763                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       158763                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       942913                       # number of writebacks
+system.cpu.dcache.writebacks::total            942913                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       269863                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       269863                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158857                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       158857                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            7                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            7                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       428751                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       428751                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       428751                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       428751                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903940                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       903940                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        43699                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        43699                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       947639                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       947639                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       947639                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       947639                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9994791010                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9994791010                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1332397702                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1332397702                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11327188712                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11327188712                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11327188712                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11327188712                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036482                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036482                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009229                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009229                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032110                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.032110                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032110                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032110                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.918612                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.918612                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30490.347651                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30490.347651                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11953.063046                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11953.063046                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11953.063046                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11953.063046                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data       428720                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       428720                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       428720                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       428720                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903830                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       903830                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        43792                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        43792                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       947622                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       947622                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       947622                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       947622                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9993578260                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9993578260                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1330001932                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1330001932                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11323580192                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11323580192                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11323580192                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11323580192                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036488                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036488                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009249                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009249                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032116                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.032116                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032116                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032116                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.922496                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.922496                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30370.888107                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30370.888107                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.469506                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.469506                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.469506                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.469506                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 0d20a5545..53bbc79f1 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.054241                       # Nu
 sim_ticks                                 54240661000                       # Number of ticks simulated
 final_tick                                54240661000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2151308                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2166754                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1287915883                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 391064                       # Number of bytes of host memory used
-host_seconds                                    42.12                       # Real time elapsed on the host
+host_inst_rate                                1753346                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1765935                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1049669772                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 433744                       # Number of bytes of host memory used
+host_seconds                                    51.67                       # Real time elapsed on the host
 sim_insts                                    90602407                       # Number of instructions simulated
 sim_ops                                      91252960                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,5 +147,40 @@ system.cpu.num_busy_cycles                  108481323                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          18732304                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  63924095     70.05%     70.05% # Class of executed instruction
+system.cpu.op_class::IntMult                    10474      0.01%     70.06% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::MemRead                 22573966     24.74%     94.80% # Class of executed instruction
+system.cpu.op_class::MemWrite                 4744844      5.20%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   91253402                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index c88119d29..a84dd1567 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.147136                       # Nu
 sim_ticks                                147135976000                       # Number of ticks simulated
 final_tick                               147135976000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1098833                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1106711                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1784978875                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 400800                       # Number of bytes of host memory used
-host_seconds                                    82.43                       # Real time elapsed on the host
+host_inst_rate                                 805246                       # Simulator instruction rate (inst/s)
+host_op_rate                                   811020                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1308067541                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 443480                       # Number of bytes of host memory used
+host_seconds                                   112.48                       # Real time elapsed on the host
 sim_insts                                    90576861                       # Number of instructions simulated
 sim_ops                                      91226312                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -153,6 +153,41 @@ system.cpu.num_busy_cycles                  294271952                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          18732304                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  63924095     70.05%     70.05% # Class of executed instruction
+system.cpu.op_class::IntMult                    10474      0.01%     70.06% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.06% # Class of executed instruction
+system.cpu.op_class::MemRead                 22573966     24.74%     94.80% # Class of executed instruction
+system.cpu.op_class::MemWrite                 4744844      5.20%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   91253402                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 2                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.071144                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           107830172                       # Total number of references to valid blocks.
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index 04e67f508..49ab3ae18 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.122216                       # Nu
 sim_ticks                                122215823500                       # Number of ticks simulated
 final_tick                               122215823500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3086610                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3086737                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1547143112                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 361240                       # Number of bytes of host memory used
-host_seconds                                    78.99                       # Real time elapsed on the host
+host_inst_rate                                2362566                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2362664                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1184221154                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 397240                       # Number of bytes of host memory used
+host_seconds                                   103.20                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -65,5 +65,40 @@ system.cpu.num_busy_cycles                  244431648                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          29302884                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              28877736     11.81%     11.81% # Class of executed instruction
+system.cpu.op_class::IntAlu                 109842388     44.94%     56.75% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatAdd                      42      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::MemRead                 82803527     33.88%     90.63% # Class of executed instruction
+system.cpu.op_class::MemWrite                22907920      9.37%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  244431613                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 5dcd0f89a..5300dcfdd 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.361489                       # Nu
 sim_ticks                                361488530000                       # Number of ticks simulated
 final_tick                               361488530000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1454320                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1454380                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2156135283                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 371132                       # Number of bytes of host memory used
-host_seconds                                   167.66                       # Real time elapsed on the host
+host_inst_rate                                1070091                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1070135                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1586487053                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 406976                       # Number of bytes of host memory used
+host_seconds                                   227.85                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -69,6 +69,41 @@ system.cpu.num_busy_cycles                  722977060                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          29302884                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              28877736     11.81%     11.81% # Class of executed instruction
+system.cpu.op_class::IntAlu                 109842388     44.94%     56.75% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatAdd                      42      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     56.75% # Class of executed instruction
+system.cpu.op_class::MemRead                 82803527     33.88%     90.63% # Class of executed instruction
+system.cpu.op_class::MemWrite                22907920      9.37%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  244431613                       # Class of executed instruction
 system.cpu.icache.tags.replacements                25                       # number of replacements
 system.cpu.icache.tags.tagsinuse           725.412977                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           244420617                       # Total number of references to valid blocks.
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 1b324ac26..53217cf02 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,79 +1,79 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.065578                       # Number of seconds simulated
-sim_ticks                                 65578127500                       # Number of ticks simulated
-final_tick                                65578127500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.065585                       # Number of seconds simulated
+sim_ticks                                 65585340000                       # Number of ticks simulated
+final_tick                                65585340000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  88175                       # Simulator instruction rate (inst/s)
-host_op_rate                                   155262                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               36599742                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 427692                       # Number of bytes of host memory used
-host_seconds                                  1791.76                       # Real time elapsed on the host
+host_inst_rate                                  87128                       # Simulator instruction rate (inst/s)
+host_op_rate                                   153419                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               36169402                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 428764                       # Number of bytes of host memory used
+host_seconds                                  1813.28                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             63744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1882880                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1946624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        63744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           63744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        10368                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             10368                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                996                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29420                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30416                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             162                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  162                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               972031                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             28712012                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                29684044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          972031                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             972031                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            158101                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 158101                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            158101                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              972031                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            28712012                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               29842145                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         30418                       # Number of read requests accepted
-system.physmem.writeReqs                          162                       # Number of write requests accepted
-system.physmem.readBursts                       30418                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        162                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1942912                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      3840                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                      8384                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1946752                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  10368                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       60                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             64064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1883456                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1947520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        64064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           64064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        11200                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             11200                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1001                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29429                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30430                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             175                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  175                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               976804                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             28717637                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                29694441                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          976804                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             976804                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            170770                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 170770                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            170770                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              976804                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            28717637                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               29865211                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         30432                       # Number of read requests accepted
+system.physmem.writeReqs                          175                       # Number of write requests accepted
+system.physmem.readBursts                       30432                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        175                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1942848                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      4800                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     10048                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1947648                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  11200                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       75                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1927                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                2065                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                2026                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1928                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                2026                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1922                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                2061                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                2029                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1929                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                2025                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1900                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1961                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1862                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1964                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1863                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1940                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                1933                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               1805                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                1934                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               1804                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               1796                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               1800                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               1818                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               1779                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                  10                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                  71                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   3                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                  17                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                  12                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1820                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               1778                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                   7                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                  84                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   9                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                  29                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                   7                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  10                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  12                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   5                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                   6                       # Per bank write bursts
 system.physmem.perBankWrBursts::10                  3                       # Per bank write bursts
 system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
@@ -82,26 +82,26 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     65578111000                       # Total gap between requests
+system.physmem.totGap                     65585323000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   30418                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   30432                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    162                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     29902                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       362                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        70                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        19                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    175                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     29908                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       357                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        72                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        17                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
@@ -193,179 +193,181 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1672                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      934.162679                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     823.717230                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     264.349754                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             77      4.61%      4.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           54      3.23%      7.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           19      1.14%      8.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           10      0.60%      9.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           11      0.66%     10.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            5      0.30%     10.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            6      0.36%     10.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            4      0.24%     11.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         1486     88.88%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1672                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples             7                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      4327.142857                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       47.742498                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    11404.448466                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023              6     85.71%     85.71% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719            1     14.29%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total               7                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples             7                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.714286                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.459831                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.545621                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  3     42.86%     42.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  3     42.86%     85.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1     14.29%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total               7                       # Writes before turning the bus around for reads
-system.physmem.totQLat                       98355750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 704267000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    151790000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                   454121250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        3239.86                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14958.87                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples         2701                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      722.766383                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     519.037520                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     387.855736                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            380     14.07%     14.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          203      7.52%     21.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          114      4.22%     25.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          105      3.89%     29.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          110      4.07%     33.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          132      4.89%     38.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           83      3.07%     41.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           80      2.96%     44.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1494     55.31%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           2701                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples             9                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      3366.777778                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       25.330646                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    10057.961719                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023              8     88.89%     88.89% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719            1     11.11%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total               9                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples             9                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.444444                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.423969                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.881917                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  2     22.22%     22.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  1     11.11%     33.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                  6     66.67%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total               9                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      122012500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 691206250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    151785000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4019.25                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23198.73                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          29.63                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.13                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       29.69                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.16                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  22769.25                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          29.62                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.15                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       29.70                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.17                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.23                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        15.72                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      27690                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                        93                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.21                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  57.41                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2144477.14                       # Average gap between requests
-system.physmem.pageHitRate                      91.03                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               1.03                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     29841169                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                1415                       # Transaction distribution
-system.membus.trans_dist::ReadResp               1412                       # Transaction distribution
-system.membus.trans_dist::Writeback               162                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             29003                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            29003                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        60995                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        60995                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  60995                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1956928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total      1956928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total             1956928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                1956928                       # Total data (bytes)
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        15.09                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      27699                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       110                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   91.24                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  62.86                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2142821.02                       # Average gap between requests
+system.physmem.pageHitRate                      91.08                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      59149173500                       # Time in different power states
+system.physmem.memoryStateTime::REF        2189980000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        4244704000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     29864235                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                1427                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1424                       # Transaction distribution
+system.membus.trans_dist::Writeback               175                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             29005                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            29005                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61036                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61036                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  61036                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1958656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total      1958656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total             1958656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                1958656                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            34882000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            35026000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          284250750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          284359000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                33848859                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          33848859                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            773675                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             19289255                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                19197917                       # Number of BTB hits
+system.cpu.branchPred.lookups                33857939                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          33857939                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            774699                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             19294742                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                19202488                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.526482                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 5013789                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               5382                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.521870                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 5017287                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               5447                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        131156258                       # number of cpu cycles simulated
+system.cpu.numCycles                        131170685                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           26124618                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      182201449                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    33848859                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24211706                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      55441130                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5339784                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               44953696                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   48                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           286                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           26133192                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      182246280                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    33857939                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24219775                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      55455334                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5351155                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               44937204                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   47                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           289                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles            1                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  25565447                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                166050                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          131050652                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.451103                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.313857                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  25572777                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                166462                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          131067108                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.451414                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.313936                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 78085477     59.58%     59.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1960121      1.50%     61.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2941365      2.24%     63.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3832581      2.92%     66.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7765611      5.93%     72.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4754905      3.63%     75.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2663892      2.03%     77.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1315906      1.00%     78.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 27730794     21.16%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 78089059     59.58%     59.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1960403      1.50%     61.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2941378      2.24%     63.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  3833422      2.92%     66.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7766051      5.93%     72.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4756858      3.63%     75.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2667148      2.03%     77.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1317375      1.01%     78.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 27735414     21.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            131050652                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.258080                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.389194                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 36811004                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              37176024                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  43889002                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               8643749                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4530873                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              318736109                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                4530873                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 42298555                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 9762867                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           7405                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  46737142                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              27713810                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              314904511                       # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total            131067108                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.258121                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.389383                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 36820362                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              37159698                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  43897766                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8648241                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4541041                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              318820485                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                4541041                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 42311218                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 9731436                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7378                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  46747775                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              27728260                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              314978384                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                   214                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  26056                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              25855633                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           317074927                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             836235433                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        514870937                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               492                       # Number of floating rename lookups
+system.cpu.rename.IQFullEvents                  26284                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              25867087                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           317148193                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             836430617                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        514996548                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               444                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 37862180                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                484                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            482                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  62586078                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            101522320                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            34765778                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          39602927                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5818030                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  311370743                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1646                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 300208382                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             88815                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        32598997                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     45935189                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1201                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     131050652                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.290781                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.700647                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 37935446                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                481                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            479                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  62636107                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            101548078                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            34773749                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          39632863                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5801803                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  311454794                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1640                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 300260019                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             90405                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        32683934                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     46065887                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1195                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     131067108                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.290888                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.699985                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            24364795     18.59%     18.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            23214690     17.71%     36.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25426307     19.40%     55.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            25814267     19.70%     75.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            18862103     14.39%     89.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             8277108      6.32%     96.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             3959654      3.02%     99.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              947423      0.72%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              184305      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            24336657     18.57%     18.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            23236619     17.73%     36.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25445511     19.41%     55.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            25817468     19.70%     75.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            18870400     14.40%     89.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8268823      6.31%     96.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3966909      3.03%     99.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              944963      0.72%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              179758      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       131050652                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       131067108                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   31474      1.53%      1.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   31509      1.53%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.53% # attempts to use FU when none available
@@ -394,14 +396,14 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.53% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1916835     93.04%     94.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                111878      5.43%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1916553     93.05%     94.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                111592      5.42%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             31277      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             169792966     56.56%     56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                11226      0.00%     56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                   332      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             31276      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             169826780     56.56%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11192      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   330      0.00%     56.57% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     56.57% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.57% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.57% # Type of FU issued
@@ -428,84 +430,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.57% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.57% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.57% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             97287204     32.41%     88.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            33085346     11.02%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             97302133     32.41%     88.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            33088277     11.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              300208382                       # Type of FU issued
-system.cpu.iq.rate                           2.288937                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2060187                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006863                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          733615929                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         344003056                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    297961989                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 489                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                706                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          149                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              302237064                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     228                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         54184589                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              300260019                       # Type of FU issued
+system.cpu.iq.rate                           2.289079                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2059654                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006860                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          733736743                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         344172361                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    298003080                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 462                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                638                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          138                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              302288185                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     212                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         54177955                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     10742935                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        32064                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        33208                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      3326026                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     10768693                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        31319                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        33463                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3333997                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3224                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          8575                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3215                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          8563                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4530873                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2837927                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                162034                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           311372389                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            196090                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             101522320                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             34765778                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                470                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   2524                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 73590                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          33208                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         392510                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       427924                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               820434                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             298810960                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              96874788                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1397422                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4541041                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2814889                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                161942                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           311456434                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            197084                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             101548078                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             34773749                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                466                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2528                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 73554                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          33463                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         393542                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       427902                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               821444                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             298855458                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              96888981                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1404561                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    129797042                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 30816203                       # Number of branches executed
-system.cpu.iew.exec_stores                   32922254                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.278282                       # Inst execution rate
-system.cpu.iew.wb_sent                      298329085                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     297962138                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 218205948                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 296684532                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    129814280                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 30819367                       # Number of branches executed
+system.cpu.iew.exec_stores                   32925299                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.278371                       # Inst execution rate
+system.cpu.iew.wb_sent                      298372320                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     298003218                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 218247752                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 296740863                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.271810                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.735481                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.271874                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.735483                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        33192838                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        33277101                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            773712                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    126519779                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.198806                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.971927                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            774736                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    126526067                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.198697                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.971805                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     58265880     46.05%     46.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     19155859     15.14%     61.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     11581370      9.15%     70.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9445264      7.47%     77.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1880302      1.49%     79.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2071430      1.64%     80.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1302334      1.03%     81.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       693009      0.55%     82.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22124331     17.49%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     58264985     46.05%     46.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     19162475     15.15%     61.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     11581155      9.15%     70.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9447794      7.47%     77.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1880712      1.49%     79.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2075089      1.64%     80.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1295892      1.02%     81.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       693068      0.55%     82.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22124897     17.49%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    126519779                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    126526067                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -516,231 +518,266 @@ system.cpu.commit.branches                   29309705                       # Nu
 system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 278169481                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              4237596                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              22124331                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass        16695      0.01%      0.01% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        155945353     56.06%     56.06% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           10938      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv              329      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd             12      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.07% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        90779385     32.63%     88.70% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       31439752     11.30%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              22124897                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    415780750                       # The number of ROB reads
-system.cpu.rob.rob_writes                   627305222                       # The number of ROB writes
-system.cpu.timesIdled                           13712                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          105606                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    415870735                       # The number of ROB reads
+system.cpu.rob.rob_writes                   627483927                       # The number of ROB writes
+system.cpu.timesIdled                           13678                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          103577                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             157988547                       # Number of Instructions Simulated
-system.cpu.cpi                               0.830163                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.830163                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.204583                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.204583                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                483659759                       # number of integer regfile reads
-system.cpu.int_regfile_writes               234542237                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       137                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       71                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 107049810                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 63997871                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               191792946                       # number of misc regfile reads
+system.cpu.cpi                               0.830254                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.830254                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.204450                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.204450                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                483721911                       # number of integer regfile reads
+system.cpu.int_regfile_writes               234579114                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       126                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       70                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 107055944                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 64002928                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               191820739                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              4044284064                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1995295                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1995292                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2066395                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        82322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        82322                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2024                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6219602                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6221626                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        64768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265151808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      265216576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         265216576                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              4043936892                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1995332                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1995329                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2066459                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        82321                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        82321                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2030                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6219732                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6221762                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        64960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265158016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      265222976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         265222976                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4138401000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy     4138515000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          6.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1688749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1696250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3121628749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3121723249                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          4.8                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                55                       # number of replacements
-system.cpu.icache.tags.tagsinuse           821.703802                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25564150                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1012                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          25261.017787                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           822.073751                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25571467                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1015                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          25193.563547                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   821.703802                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.401223                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.401223                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          957                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   822.073751                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.401403                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.401403                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          960                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          870                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.467285                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51131906                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51131906                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25564150                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25564150                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25564150                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25564150                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25564150                       # number of overall hits
-system.cpu.icache.overall_hits::total        25564150                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1297                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1297                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1297                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1297                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1297                       # number of overall misses
-system.cpu.icache.overall_misses::total          1297                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     90379749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     90379749                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     90379749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     90379749                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     90379749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     90379749                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25565447                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25565447                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25565447                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25565447                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25565447                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25565447                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          874                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.468750                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          51146569                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51146569                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     25571467                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25571467                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25571467                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25571467                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25571467                       # number of overall hits
+system.cpu.icache.overall_hits::total        25571467                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1310                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1310                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1310                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1310                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1310                       # number of overall misses
+system.cpu.icache.overall_misses::total          1310                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     88805250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     88805250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     88805250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     88805250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     88805250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     88805250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25572777                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25572777                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25572777                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25572777                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25572777                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25572777                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000051                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000051                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000051                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000051                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000051                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000051                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69683.692367                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69683.692367                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69683.692367                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69683.692367                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69683.692367                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69683.692367                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          114                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67790.267176                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67790.267176                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67790.267176                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67790.267176                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67790.267176                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67790.267176                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          116                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           38                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    38.666667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          285                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          285                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          285                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          285                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          285                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          285                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1012                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1012                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1012                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1012                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1012                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1012                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     70911751                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     70911751                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     70911751                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     70911751                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     70911751                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     70911751                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          295                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          295                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          295                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          295                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          295                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          295                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1015                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1015                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1015                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1015                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1015                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1015                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     69941750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     69941750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     69941750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     69941750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     69941750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     69941750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70070.900198                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70070.900198                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70070.900198                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70070.900198                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70070.900198                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70070.900198                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68908.128079                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68908.128079                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68908.128079                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68908.128079                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68908.128079                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68908.128079                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements              479                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20808.807905                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4029125                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            30398                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           132.545727                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements              490                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        20815.284491                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4029213                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            30412                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           132.487604                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19891.385936                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   670.059760                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   247.362209                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.607037                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020449                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.007549                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.635034                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29919                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 19896.837490                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   671.064611                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   247.382390                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.607203                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020479                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.007550                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.635232                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29922                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          763                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1379                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27657                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913055                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         33264816                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        33264816                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           16                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1993864                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1993880                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2066395                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2066395                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        53319                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        53319                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           16                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2047183                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2047199                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           16                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2047183                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2047199                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          996                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          419                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1415                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        29003                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        29003                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          996                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29422                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30418                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          996                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29422                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30418                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     69735750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     30889250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    100625000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1899321750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1899321750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     69735750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1930211000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1999946750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     69735750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1930211000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1999946750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         1012                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1994283                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1995295                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2066395                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2066395                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        82322                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        82322                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1012                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2076605                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2077617                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1012                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2076605                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2077617                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.984190                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000210                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000709                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352312                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.352312                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.984190                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.014168                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.014641                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.984190                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014168                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014641                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70015.813253                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73721.360382                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71113.074205                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65487.078923                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65487.078923                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70015.813253                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65604.343688                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 65748.791834                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70015.813253                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65604.343688                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 65748.791834                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          771                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1381                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27649                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913147                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33265629                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33265629                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst           14                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1993891                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1993905                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2066459                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2066459                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        53316                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        53316                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           14                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2047207                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2047221                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           14                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2047207                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2047221                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1001                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          426                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1427                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        29005                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        29005                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1001                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        29431                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         30432                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1001                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        29431                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        30432                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     68781250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     30133000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     98914250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1888274750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1888274750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     68781250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1918407750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1987189000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     68781250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1918407750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1987189000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1015                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1994317                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1995332                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2066459                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2066459                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        82321                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        82321                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1015                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2076638                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2077653                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1015                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2076638                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2077653                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.986207                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000214                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000715                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352340                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.352340                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.986207                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.014172                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.014647                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.986207                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.014172                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.014647                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68712.537463                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70734.741784                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69316.222845                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65101.697983                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65101.697983                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68712.537463                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65183.233665                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 65299.323081                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68712.537463                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65183.233665                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 65299.323081                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -749,167 +786,167 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          162                       # number of writebacks
-system.cpu.l2cache.writebacks::total              162                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          996                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          419                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1415                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29003                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        29003                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          996                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29422                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30418                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          996                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29422                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30418                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     57248250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     25743750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     82992000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1534558750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1534558750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     57248250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1560302500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1617550750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     57248250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1560302500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1617550750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.984190                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000210                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000709                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352312                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352312                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.984190                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014168                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014641                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.984190                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014168                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.014641                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57478.162651                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61440.930788                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58651.590106                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52910.345482                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52910.345482                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57478.162651                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53031.829923                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53177.419620                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57478.162651                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53031.829923                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53177.419620                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks          175                       # number of writebacks
+system.cpu.l2cache.writebacks::total              175                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1001                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          426                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1427                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29005                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        29005                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1001                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        29431                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        30432                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1001                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        29431                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        30432                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     56223750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     24897500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     81121250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1523473250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1523473250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     56223750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1548370750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1604594500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     56223750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1548370750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1604594500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.986207                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000214                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000715                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352340                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352340                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.986207                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014172                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014647                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.986207                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014172                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.014647                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56167.582418                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58444.835681                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56847.407148                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52524.504396                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52524.504396                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56167.582418                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52610.198430                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52727.211488                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56167.582418                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52610.198430                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52727.211488                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2072506                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4069.429006                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            71361494                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2076602                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             34.364550                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20660759250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4069.429006                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993513                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993513                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2072539                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4069.510002                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            71382775                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2076635                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             34.374252                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20654566000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4069.510002                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993533                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993533                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          573                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3367                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          156                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          584                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3362                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         150248380                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        150248380                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     40019790                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        40019790                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31341704                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31341704                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      71361494                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         71361494                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     71361494                       # number of overall hits
-system.cpu.dcache.overall_hits::total        71361494                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2626347                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2626347                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        98048                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        98048                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2724395                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2724395                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2724395                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2724395                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  31407355250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31407355250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2801736997                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2801736997                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34209092247                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34209092247                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34209092247                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34209092247                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     42646137                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     42646137                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         150290167                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        150290167                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     40041040                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        40041040                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31341735                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31341735                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      71382775                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         71382775                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     71382775                       # number of overall hits
+system.cpu.dcache.overall_hits::total        71382775                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2625974                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2625974                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        98017                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        98017                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2723991                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2723991                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2723991                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2723991                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31399512249                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31399512249                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2790424746                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2790424746                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34189936995                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34189936995                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34189936995                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34189936995                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     42667014                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     42667014                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     74085889                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     74085889                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     74085889                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     74085889                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061585                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.061585                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003119                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.003119                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036773                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036773                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036773                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036773                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.570307                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.570307                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28575.157035                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28575.157035                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12556.583112                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12556.583112                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12556.583112                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12556.583112                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        32689                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     74106766                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     74106766                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     74106766                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     74106766                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061546                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.061546                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003118                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.003118                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036758                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036758                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036758                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036758                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11957.282231                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11957.282231                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28468.783436                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28468.783436                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12551.413347                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12551.413347                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12551.413347                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12551.413347                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32593                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              9492                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              9513                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     3.443847                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     3.426154                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2066395                       # number of writebacks
-system.cpu.dcache.writebacks::total           2066395                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       631958                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       631958                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        15832                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        15832                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       647790                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       647790                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       647790                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       647790                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994389                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994389                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82216                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82216                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076605                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076605                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076605                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076605                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21997400000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  21997400000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2514181749                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2514181749                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24511581749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  24511581749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24511581749                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  24511581749                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046766                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046766                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks      2066459                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066459                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       631537                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       631537                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        15816                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        15816                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       647353                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       647353                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       647353                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       647353                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994437                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994437                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82201                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82201                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076638                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076638                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076638                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076638                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21996919001                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21996919001                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2502949746                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2502949746                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24499868747                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  24499868747                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24499868747                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  24499868747                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046744                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046744                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002615                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002615                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028030                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028030                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028030                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028030                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.643665                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.643665                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30580.200314                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30580.200314                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11803.680406                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11803.680406                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11803.680406                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11803.680406                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028022                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028022                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028022                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028022                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.137045                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.137045                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30449.139864                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30449.139864                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.852465                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.852465                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.852465                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.852465                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 2af726aad..d0541f8a9 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.168950                       # Nu
 sim_ticks                                168950040000                       # Number of ticks simulated
 final_tick                               168950040000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1603557                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2823605                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1714813271                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379092                       # Number of bytes of host memory used
-host_seconds                                    98.52                       # Real time elapsed on the host
+host_inst_rate                                1054637                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1857047                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1127809594                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 414920                       # Number of bytes of host memory used
+host_seconds                                   149.80                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -66,5 +66,40 @@ system.cpu.num_busy_cycles                  337900081                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          29309705                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                 16695      0.01%      0.01% # Class of executed instruction
+system.cpu.op_class::IntAlu                 155945354     56.06%     56.06% # Class of executed instruction
+system.cpu.op_class::IntMult                    10938      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::IntDiv                       329      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatAdd                      12      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::MemRead                 90779385     32.63%     88.70% # Class of executed instruction
+system.cpu.op_class::MemWrite                31439752     11.30%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  278192465                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 9f0a8c755..917c42379 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.365989                       # Nu
 sim_ticks                                365989065000                       # Number of ticks simulated
 final_tick                               365989065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 696180                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1225861                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1612738645                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 388852                       # Number of bytes of host memory used
-host_seconds                                   226.94                       # Real time elapsed on the host
+host_inst_rate                                 596728                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1050742                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1382352440                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 424660                       # Number of bytes of host memory used
+host_seconds                                   264.76                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -82,6 +82,41 @@ system.cpu.num_busy_cycles                  731978130                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          29309705                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                 16695      0.01%      0.01% # Class of executed instruction
+system.cpu.op_class::IntAlu                 155945354     56.06%     56.06% # Class of executed instruction
+system.cpu.op_class::IntMult                    10938      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::IntDiv                       329      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatAdd                      12      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     56.07% # Class of executed instruction
+system.cpu.op_class::MemRead                 90779385     32.63%     88.70% # Class of executed instruction
+system.cpu.op_class::MemWrite                31439752     11.30%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  278192465                       # Class of executed instruction
 system.cpu.icache.tags.replacements                24                       # number of replacements
 system.cpu.icache.tags.tagsinuse           665.632508                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           217695357                       # Total number of references to valid blocks.
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 50a810bbd..8b3ef27a1 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.202387                       # Number of seconds simulated
-sim_ticks                                202386636500                       # Number of ticks simulated
-final_tick                               202386636500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.202425                       # Number of seconds simulated
+sim_ticks                                202425052500                       # Number of ticks simulated
+final_tick                               202425052500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 118405                       # Simulator instruction rate (inst/s)
-host_op_rate                                   133495                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               47430504                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317288                       # Number of bytes of host memory used
-host_seconds                                  4267.01                       # Real time elapsed on the host
+host_inst_rate                                 117924                       # Simulator instruction rate (inst/s)
+host_op_rate                                   132952                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47246555                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317744                       # Number of bytes of host memory used
+host_seconds                                  4284.44                       # Real time elapsed on the host
 sim_insts                                   505237723                       # Number of instructions simulated
 sim_ops                                     569624283                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            215296                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9261568                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9476864                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       215296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          215296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6245824                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6245824                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3364                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             144712                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                148076                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97591                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97591                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1063786                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             45761757                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                46825542                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1063786                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1063786                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          30860852                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               30860852                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          30860852                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1063786                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            45761757                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               77686394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        148077                       # Number of read requests accepted
-system.physmem.writeReqs                        97591                       # Number of write requests accepted
-system.physmem.readBursts                      148077                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97591                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9467712                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9216                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6243712                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9476928                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6245824                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      144                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            216128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9265920                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9482048                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       216128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          216128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6248320                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6248320                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3377                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             144780                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                148157                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97630                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97630                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1067694                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             45774571                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                46842265                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1067694                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1067694                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          30867326                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               30867326                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          30867326                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1067694                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            45774571                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               77709591                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        148159                       # Number of read requests accepted
+system.physmem.writeReqs                        97630                       # Number of write requests accepted
+system.physmem.readBursts                      148159                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97630                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9473600                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8576                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6247040                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9482176                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6248320                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      134                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              9                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9595                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9241                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9230                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8948                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9774                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9652                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9107                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8317                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8793                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8911                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8931                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9713                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9649                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9746                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8931                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9395                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6267                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6152                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6088                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5869                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6257                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6287                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6043                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5545                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5805                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5895                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5984                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6504                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6370                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6330                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6044                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6118                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs              5                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9589                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9250                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9271                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8997                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9766                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9623                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9103                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8296                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8815                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8915                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8926                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9755                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9632                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9741                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8922                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9424                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6257                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6164                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6102                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5898                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6263                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6268                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6040                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5542                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5815                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5905                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5986                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6523                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6368                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6315                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6035                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6129                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    202386616500                       # Total gap between requests
+system.physmem.totGap                    202425037000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  148077                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  148159                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97591                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    138091                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      9280                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       494                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        59                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97630                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    138435                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      9034                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       497                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        50                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,48 +144,48 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1942                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2625                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4944                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5396                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5496                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5554                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5554                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6518                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5951                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5565                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5335                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5757                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5818                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5824                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5835                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5866                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5860                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5863                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5973                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5919                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5829                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5845                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5807                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5734                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
@@ -193,112 +193,103 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39628                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      257.573029                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     159.018208                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     287.256707                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15558     39.26%     39.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11171     28.19%     67.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4346     10.97%     78.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2186      5.52%     83.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1365      3.44%     87.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          780      1.97%     89.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          563      1.42%     90.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          515      1.30%     92.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3144      7.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39628                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5484                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.971554                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      384.653172                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5482     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        65421                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      240.288837                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     153.819388                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     255.394880                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          26636     40.71%     40.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17331     26.49%     67.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6016      9.20%     76.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         6235      9.53%     85.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3111      4.76%     90.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1372      2.10%     92.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          907      1.39%     94.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          656      1.00%     95.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3157      4.83%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65421                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5723                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.864057                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      376.771836                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5718     99.91%     99.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            4      0.07%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5484                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5484                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.789570                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.450739                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        4.762634                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            3346     61.01%     61.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            1810     33.01%     94.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21             182      3.32%     97.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              11      0.20%     97.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25               3      0.05%     97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27               4      0.07%     97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29               3      0.05%     97.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               1      0.02%     97.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               3      0.05%     97.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               1      0.02%     97.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               1      0.02%     97.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39              12      0.22%     98.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41              29      0.53%     98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43              19      0.35%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45               8      0.15%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47               7      0.13%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               7      0.13%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               8      0.15%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               9      0.16%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               6      0.11%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               4      0.07%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59               3      0.05%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63               1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-65               2      0.04%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::66-67               1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-73               1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-77               1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::90-91               1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5484                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1351646500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4559189000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    739665000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  2467877500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        9136.88                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16682.40                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            5723                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5723                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.055740                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.965515                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.130372                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            3465     60.55%     60.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            2071     36.19%     96.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              82      1.43%     98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              27      0.47%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              23      0.40%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              19      0.33%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              13      0.23%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               7      0.12%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               3      0.05%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               3      0.05%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               1      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43               3      0.05%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47               2      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-69               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5723                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1821123750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4596592500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    740125000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12302.81                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30819.28                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          46.78                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          30.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       46.83                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       30.86                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31052.81                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          46.80                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          30.86                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       46.84                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       30.87                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.61                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.37                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.24                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.36                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     116029                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64903                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   78.43                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.51                       # Row buffer hit rate for writes
-system.physmem.avgGap                       823821.65                       # Average gap between requests
-system.physmem.pageHitRate                      73.69                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.51                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     77686394                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               46784                       # Transaction distribution
-system.membus.trans_dist::ReadResp              46783                       # Transaction distribution
-system.membus.trans_dist::Writeback             97591                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                9                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               9                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            101293                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           101293                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393762                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 393762                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15722688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            15722688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               15722688                       # Total data (bytes)
+system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        19.22                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     115945                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64262                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   78.33                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  65.82                       # Row buffer hit rate for writes
+system.physmem.avgGap                       823572.40                       # Average gap between requests
+system.physmem.pageHitRate                      73.36                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     121085417750                       # Time in different power states
+system.physmem.memoryStateTime::REF        6759220000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       74577349250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     77709591                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               46864                       # Transaction distribution
+system.membus.trans_dist::ReadResp              46862                       # Transaction distribution
+system.membus.trans_dist::Writeback             97630                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                5                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               5                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            101295                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           101295                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393956                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 393956                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15730368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            15730368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               15730368                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1083423500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1082435500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1396187241                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1397409745                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               182802497                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         143128799                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7265604                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             92710665                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                87222146                       # Number of BTB hits
+system.cpu.branchPred.lookups               182802818                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         143112021                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7267941                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             93011295                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                87213055                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.079949                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12678300                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             93.766090                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                12678218                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect             116271                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -385,134 +376,134 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        404773274                       # number of cpu cycles simulated
+system.cpu.numCycles                        404850106                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          119371431                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      761670050                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   182802497                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           99900446                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     170159805                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                35695191                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               77489066                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   40                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           409                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           15                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 114520254                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2435167                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          394646362                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.164609                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.986746                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          119389916                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      761628718                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   182802818                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           99891273                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     170150143                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                35691365                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               77449263                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   42                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           486                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           26                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 114538694                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2440341                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          394609388                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.164838                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.986971                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                224499175     56.89%     56.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 14180048      3.59%     60.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 22900330      5.80%     66.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 22746018      5.76%     72.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 20904181      5.30%     77.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 11597078      2.94%     80.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 13062660      3.31%     83.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 11996924      3.04%     86.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 52759948     13.37%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                224471880     56.88%     56.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 14182431      3.59%     60.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 22892997      5.80%     66.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 22746730      5.76%     72.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 20891038      5.29%     77.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 11596009      2.94%     80.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 13056866      3.31%     83.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 12000205      3.04%     86.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 52771232     13.37%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            394646362                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.451617                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.881720                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                129065441                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              72977589                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 158843318                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               6208520                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               27551494                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             26113840                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 76933                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              825615862                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                295408                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               27551494                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                135663599                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10124037                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       47858907                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 158270703                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              15177622                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              800676203                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1362                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                3041401                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               8927839                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              380                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           954380743                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3518821037                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3237543722                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               408                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            394609388                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.451532                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.881261                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                129090145                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              72932890                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 158811519                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6229483                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               27545351                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             26129524                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 76858                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              825625828                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                295316                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               27545351                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                135687065                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10105791                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       47805401                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 158260364                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              15205416                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              800656323                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1334                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                3053839                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               8954907                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              385                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           954272169                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3518760229                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3237464445                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               416                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             666252291                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                288128452                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2293069                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2293066                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  41767697                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            170285712                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            73492930                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          28608200                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         15804502                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  755130380                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             3775454                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 665331830                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1375167                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       187454297                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    480174835                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         797822                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     394646362                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.685894                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.735410                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                288019878                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2292922                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2292918                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  41836509                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            170268509                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            73501316                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          28634884                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         15888043                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  755077640                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3775313                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 665327015                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1386285                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       187386746                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    479953007                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         797681                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     394609388                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.686039                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.735073                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           139160941     35.26%     35.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            69972049     17.73%     52.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            71433490     18.10%     71.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            53381143     13.53%     84.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            31203736      7.91%     92.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            16006372      4.06%     96.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             8742132      2.22%     98.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             2922216      0.74%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1824283      0.46%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           139096453     35.25%     35.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            69938770     17.72%     52.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            71532009     18.13%     71.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            53395901     13.53%     84.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            31139583      7.89%     92.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15999118      4.05%     96.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8786717      2.23%     98.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2904396      0.74%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1816441      0.46%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       394646362                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       394609388                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  481604      5.01%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                6543314     68.07%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2587932     26.92%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  479561      5.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                6536466     68.14%     73.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2577260     26.87%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             447808389     67.31%     67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               383403      0.06%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             447787138     67.30%     67.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               383414      0.06%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  94      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.36% # Type of FU issued
@@ -540,84 +531,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.36% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            153377795     23.05%     90.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            63762146      9.58%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            153368040     23.05%     90.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            63788326      9.59%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              665331830                       # Type of FU issued
-system.cpu.iq.rate                           1.643715                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     9612850                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014448                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1736297816                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         947166381                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    646062448                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              665327015                       # Type of FU issued
+system.cpu.iq.rate                           1.643391                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     9593287                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014419                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1736242767                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         947046337                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    646056325                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 223                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                298                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              674944567                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              674920189                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     113                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          8567764                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads          8551877                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     44256157                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        42344                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       810357                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     16632453                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     44238954                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        41472                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       810610                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     16640839                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        19504                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          8568                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        19493                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          7969                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               27551494                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5275843                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                386509                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           760464256                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1125230                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             170285712                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             73492930                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            2286912                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 220350                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 11309                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         810357                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4338774                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4002387                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8341161                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             655913475                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             150097155                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           9418355                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               27545351                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5256121                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                385567                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           760412013                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1120947                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             170268509                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             73501316                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2286771                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 219704                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 12090                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         810610                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4341838                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4001214                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8343052                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             655907838                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             150084771                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           9419177                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1558422                       # number of nop insts executed
-system.cpu.iew.exec_refs                    212571042                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                138499517                       # Number of branches executed
-system.cpu.iew.exec_stores                   62473887                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.620447                       # Inst execution rate
-system.cpu.iew.wb_sent                      651035258                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     646062464                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 374747617                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 646369396                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       1559060                       # number of nop insts executed
+system.cpu.iew.exec_refs                    212583673                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                138498504                       # Number of branches executed
+system.cpu.iew.exec_stores                   62498902                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.620125                       # Inst execution rate
+system.cpu.iew.wb_sent                      651026464                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     646056341                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 374698942                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 646299992                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.596109                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.579773                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.595791                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.579760                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       189524475                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       189472037                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           7191502                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    367094868                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.555370                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.229648                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           7193780                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    367064037                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.555500                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.230573                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    159372239     43.41%     43.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     98509322     26.83%     70.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     33822268      9.21%     79.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     18793314      5.12%     84.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     16194287      4.41%     88.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7448885      2.03%     91.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7004810      1.91%     92.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3214010      0.88%     93.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22735733      6.19%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    159337830     43.41%     43.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     98602437     26.86%     70.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     33803348      9.21%     79.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     18720540      5.10%     84.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     16173781      4.41%     88.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7454535      2.03%     91.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      6985415      1.90%     92.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3172083      0.86%     93.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22814068      6.22%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    367094868                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    367064037                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            506581607                       # Number of instructions committed
 system.cpu.commit.committedOps              570968167                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -628,243 +619,273 @@ system.cpu.commit.branches                  121548301                       # Nu
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 470727693                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              22735733                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        387738913     67.91%     67.91% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          339219      0.06%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.97% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       126029555     22.07%     90.04% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       56860477      9.96%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total         570968167                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              22814068                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1104844639                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1548657613                       # The number of ROB writes
-system.cpu.timesIdled                          329536                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        10126912                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   1104683035                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1548546574                       # The number of ROB writes
+system.cpu.timesIdled                          329089                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        10240718                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505237723                       # Number of Instructions Simulated
 system.cpu.committedOps                     569624283                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             505237723                       # Number of Instructions Simulated
-system.cpu.cpi                               0.801154                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.801154                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.248199                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.248199                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3058738251                       # number of integer regfile reads
-system.cpu.int_regfile_writes               752038270                       # number of integer regfile writes
+system.cpu.cpi                               0.801306                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.801306                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.247962                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.247962                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3058680468                       # number of integer regfile reads
+system.cpu.int_regfile_writes               751974394                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               237846973                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               237852228                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               735012008                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         864661                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        864660                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1110883                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           79                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           79                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       348779                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       348779                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        33728                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3504101                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3537829                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1076352                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    147674432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148750784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148750784                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus         5824                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2273084998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               734945552                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         864760                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        864758                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1110914                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           63                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           63                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       348881                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       348881                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        33826                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3504415                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3538241                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1079872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    147686464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      148766336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         148766336                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus         5056                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2273224996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      25918735                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      26000486                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1823048732                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1824563475                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             14973                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1095.994633                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           114499162                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             16828                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           6804.086166                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             15031                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1100.518238                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           114517542                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             16885                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           6782.205626                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1095.994633                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.535154                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.535154                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1855                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          300                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1379                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.905762                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         229057415                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        229057415                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    114499162                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       114499162                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     114499162                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        114499162                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    114499162                       # number of overall hits
-system.cpu.icache.overall_hits::total       114499162                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        21091                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         21091                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        21091                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          21091                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        21091                       # number of overall misses
-system.cpu.icache.overall_misses::total         21091                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    555853234                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    555853234                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    555853234                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    555853234                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    555853234                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    555853234                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    114520253                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    114520253                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    114520253                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    114520253                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    114520253                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    114520253                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000184                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000184                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000184                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000184                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000184                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000184                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26354.996634                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 26354.996634                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 26354.996634                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 26354.996634                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 26354.996634                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 26354.996634                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          663                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1100.518238                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.537362                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.537362                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1854                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          292                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.905273                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         229094338                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        229094338                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    114517542                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       114517542                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     114517542                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        114517542                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    114517542                       # number of overall hits
+system.cpu.icache.overall_hits::total       114517542                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        21151                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         21151                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        21151                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          21151                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        21151                       # number of overall misses
+system.cpu.icache.overall_misses::total         21151                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    554005735                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    554005735                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    554005735                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    554005735                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    554005735                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    554005735                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    114538693                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    114538693                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    114538693                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    114538693                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    114538693                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    114538693                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000185                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000185                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000185                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000185                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000185                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000185                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26192.886152                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 26192.886152                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26192.886152                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 26192.886152                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26192.886152                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 26192.886152                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          775                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    60.272727                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    51.666667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4181                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4181                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4181                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4181                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4181                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4181                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16910                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        16910                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        16910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        16910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        16910                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        16910                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    402050014                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    402050014                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    402050014                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    402050014                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    402050014                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    402050014                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4198                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4198                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4198                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4198                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4198                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4198                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16953                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        16953                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        16953                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        16953                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        16953                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        16953                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    401201263                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    401201263                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    401201263                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    401201263                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    401201263                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    401201263                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000148                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000148                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000148                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23775.873093                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23775.873093                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23775.873093                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 23775.873093                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23775.873093                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 23775.873093                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23665.502448                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23665.502448                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23665.502448                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 23665.502448                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23665.502448                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 23665.502448                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           115331                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27082.895535                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1781400                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           146592                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.152096                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     102338963500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23017.339474                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   360.906574                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3704.649487                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.702433                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011014                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.113057                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.826504                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31261                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2190                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7667                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21324                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954010                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         19089931                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        19089931                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        13449                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       804311                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         817760                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1110883                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1110883                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           71                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           71                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       247485                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       247485                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        13449                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1051796                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1065245                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        13449                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1051796                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1065245                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3370                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        43440                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        46810                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            8                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            8                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       101294                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       101294                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3370                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       144734                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        148104                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3370                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       144734                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       148104                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    250298750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3365658750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3615957500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23499                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total        23499                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7297338249                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7297338249                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    250298750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10662996999                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10913295749                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    250298750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10662996999                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10913295749                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        16819                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       847751                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       864570                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1110883                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1110883                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           79                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           79                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       348779                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       348779                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        16819                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1196530                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1213349                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        16819                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1196530                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1213349                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.200369                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051241                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.054143                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.101266                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.101266                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290425                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.290425                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200369                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.120961                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.122062                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200369                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.120961                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.122062                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74272.626113                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77478.332182                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 77247.543260                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  2937.375000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  2937.375000                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72041.169753                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72041.169753                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74272.626113                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73673.062300                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73686.704944                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74272.626113                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73673.062300                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73686.704944                       # average overall miss latency
+system.cpu.l2cache.tags.replacements           115416                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        27085.834103                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1781268                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           146665                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.145147                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      89916309500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23017.620858                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   361.438946                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3706.774299                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.702442                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011030                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.113122                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.826594                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31249                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7681                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21304                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.953644                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         19091917                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        19091917                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        13492                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       804297                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         817789                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1110914                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1110914                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           59                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           59                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       247585                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       247585                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        13492                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1051882                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1065374                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        13492                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1051882                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1065374                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3382                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        43510                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        46892                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            4                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            4                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       101296                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       101296                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3382                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       144806                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        148188                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3382                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       144806                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       148188                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    248983750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3325064500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   3574048250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7369870249                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7369870249                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    248983750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10694934749                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10943918499                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    248983750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10694934749                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10943918499                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        16874                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       847807                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       864681                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1110914                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1110914                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           63                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           63                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       348881                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       348881                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        16874                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1196688                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1213562                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        16874                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1196688                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1213562                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.200427                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051321                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.054230                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.063492                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.063492                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290345                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.290345                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200427                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.121006                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.122110                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200427                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.121006                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.122110                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73620.269072                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76420.696392                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 76218.720677                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72755.787484                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72755.787484                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73620.269072                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73856.986237                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73851.583792                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73620.269072                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73856.986237                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73851.583792                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -873,203 +894,203 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97591                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97591                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           26                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           26                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           26                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3365                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43419                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        46784                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            8                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            8                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101294                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       101294                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3365                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       144713                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       148078                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3365                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       144713                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       148078                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    207676000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2821069500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3028745500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        80008                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        80008                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6013621251                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6013621251                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    207676000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8834690751                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9042366751                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    207676000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8834690751                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9042366751                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.200071                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051217                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054112                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.101266                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.101266                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290425                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290425                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200071                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.120944                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.122041                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200071                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.120944                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.122041                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61716.493314                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64973.156913                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64738.917151                       # average ReadReq mshr miss latency
+system.cpu.l2cache.writebacks::writebacks        97630                       # number of writebacks
+system.cpu.l2cache.writebacks::total            97630                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           24                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           28                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           24                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           28                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           24                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           28                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3378                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43486                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        46864                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            4                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            4                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101296                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       101296                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3378                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       144782                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       148160                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3378                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       144782                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       148160                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    206192500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2779400500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2985593000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        40004                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        40004                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6084575751                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6084575751                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    206192500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8863976251                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9070168751                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    206192500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8863976251                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9070168751                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.200190                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051292                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054198                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.063492                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.063492                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290345                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290345                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200190                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.120986                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.122087                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200190                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.120986                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.122087                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61039.816459                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63914.834659                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.600717                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59367.990710                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59367.990710                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61716.493314                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61049.738109                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61064.889795                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61716.493314                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61049.738109                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61064.889795                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60067.285490                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60067.285490                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61039.816459                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61222.916184                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61218.741570                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61039.816459                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61222.916184                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61218.741570                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1192434                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4057.447359                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           190168921                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1196530                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            158.933684                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        4256684250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4057.447359                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.990588                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.990588                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1192591                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4057.481628                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           190175522                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1196687                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            158.918349                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4252802250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4057.481628                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.990596                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.990596                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2348                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1681                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2354                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1688                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         391443552                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        391443552                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    136203085                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       136203085                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     50988219                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       50988219                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488837                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488837                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         391451119                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        391451119                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    136209146                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       136209146                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     50988846                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       50988846                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488796                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488796                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     187191304                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        187191304                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    187191304                       # number of overall hits
-system.cpu.dcache.overall_hits::total       187191304                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1703703                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1703703                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3251087                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3251087                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           39                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           39                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      4954790                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4954790                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4954790                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4954790                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  29263316713                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  29263316713                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  70545580472                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  70545580472                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       635500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       635500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  99808897185                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  99808897185                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  99808897185                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  99808897185                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    137906788                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    137906788                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     187197992                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        187197992                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    187197992                       # number of overall hits
+system.cpu.dcache.overall_hits::total       187197992                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1701390                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1701390                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3250460                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3250460                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           37                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           37                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      4951850                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4951850                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4951850                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4951850                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  29115477457                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  29115477457                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  71211038449                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  71211038449                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       609500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       609500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 100326515906                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 100326515906                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 100326515906                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 100326515906                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    137910536                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    137910536                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488876                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488876                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488833                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488833                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    192146094                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    192146094                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    192146094                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    192146094                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012354                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012354                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059940                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.059940                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000026                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000026                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025787                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025787                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025787                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025787                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17176.301687                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17176.301687                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21699.074947                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21699.074947                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16294.871795                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16294.871795                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20143.920769                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20143.920769                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20143.920769                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20143.920769                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        17635                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        54424                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1686                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             666                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.459668                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    81.717718                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    192149842                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    192149842                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    192149842                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    192149842                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012337                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012337                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059928                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.059928                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000025                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000025                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.025771                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.025771                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.025771                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.025771                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17112.759248                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17112.759248                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21907.987931                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21907.987931                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20260.410939                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20260.410939                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20260.410939                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20260.410939                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        17276                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        49920                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1691                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             664                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.216440                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    75.180723                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1110883                       # number of writebacks
-system.cpu.dcache.writebacks::total           1110883                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       855409                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       855409                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2902772                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2902772                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           39                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           39                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3758181                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3758181                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3758181                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3758181                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848294                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       848294                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348315                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       348315                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1196609                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1196609                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1196609                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1196609                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12295329526                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12295329526                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10170217738                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10170217738                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22465547264                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  22465547264                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22465547264                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  22465547264                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      1110914                       # number of writebacks
+system.cpu.dcache.writebacks::total           1110914                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       853047                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       853047                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2902052                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2902052                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           37                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           37                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3755099                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3755099                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3755099                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3755099                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848343                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       848343                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348408                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       348408                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1196751                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1196751                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1196751                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1196751                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12254549779                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12254549779                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10243730741                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10243730741                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22498280520                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  22498280520                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22498280520                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  22498280520                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006151                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006151                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006422                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006422                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006424                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006424                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006228                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006228                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14494.184240                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14494.184240                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29198.334088                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29198.334088                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18774.342550                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18774.342550                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18774.342550                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18774.342550                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14445.277180                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14445.277180                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29401.537109                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29401.537109                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18799.466656                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18799.466656                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18799.466656                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18799.466656                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index d5ef40d1a..2e9e4306a 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.290499                       # Nu
 sim_ticks                                290498967000                       # Number of ticks simulated
 final_tick                               290498967000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2103217                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2370536                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1206088561                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262216                       # Number of bytes of host memory used
-host_seconds                                   240.86                       # Real time elapsed on the host
+host_inst_rate                                1775828                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2001536                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1018347697                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304924                       # Number of bytes of host memory used
+host_seconds                                   285.27                       # Real time elapsed on the host
 sim_insts                                   506581607                       # Number of instructions simulated
 sim_ops                                     570968167                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,5 +147,40 @@ system.cpu.num_busy_cycles                  580997935                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         121548301                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 387739461     67.91%     67.91% # Class of executed instruction
+system.cpu.op_class::IntMult                   339219      0.06%     67.97% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::MemRead                126029555     22.07%     90.04% # Class of executed instruction
+system.cpu.op_class::MemWrite                56860479      9.96%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  570968717                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index d77119b6a..ef3fc2a0f 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.717366                       # Nu
 sim_ticks                                717366012000                       # Number of ticks simulated
 final_tick                               717366012000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1131056                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1274509                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1606737202                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 271980                       # Number of bytes of host memory used
-host_seconds                                   446.47                       # Real time elapsed on the host
+host_inst_rate                                 879063                       # Simulator instruction rate (inst/s)
+host_op_rate                                   990556                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1248765490                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313636                       # Number of bytes of host memory used
+host_seconds                                   574.46                       # Real time elapsed on the host
 sim_insts                                   504986853                       # Number of instructions simulated
 sim_ops                                     569034839                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -161,6 +161,41 @@ system.cpu.num_busy_cycles                 1434732024                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         121548301                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 387739461     67.91%     67.91% # Class of executed instruction
+system.cpu.op_class::IntMult                   339219      0.06%     67.97% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.97% # Class of executed instruction
+system.cpu.op_class::MemRead                126029555     22.07%     90.04% # Class of executed instruction
+system.cpu.op_class::MemWrite                56860479      9.96%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  570968717                       # Class of executed instruction
 system.cpu.icache.tags.replacements              9788                       # number of replacements
 system.cpu.icache.tags.tagsinuse           982.663229                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           516599855                       # Total number of references to valid blocks.
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index a5895db0e..333a1495e 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.458346                       # Number of seconds simulated
-sim_ticks                                458345683000                       # Number of ticks simulated
-final_tick                               458345683000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.458513                       # Number of seconds simulated
+sim_ticks                                458512999500                       # Number of ticks simulated
+final_tick                               458512999500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  77949                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144137                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43207948                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 382980                       # Number of bytes of host memory used
-host_seconds                                 10607.90                       # Real time elapsed on the host
+host_inst_rate                                  75448                       # Simulator instruction rate (inst/s)
+host_op_rate                                   139512                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               41836736                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 384056                       # Number of bytes of host memory used
+host_seconds                                 10959.58                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            201344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24476224                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24677568                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       201344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          201344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18790080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18790080                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3146                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             382441                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                385587                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293595                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293595                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               439284                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             53401232                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                53840516                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          439284                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             439284                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          40995434                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               40995434                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          40995434                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              439284                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            53401232                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               94835949                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        385587                       # Number of read requests accepted
-system.physmem.writeReqs                       293595                       # Number of write requests accepted
-system.physmem.readBursts                      385587                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293595                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24655680                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     21888                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18787904                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24677568                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18790080                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      342                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            201856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24474368                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24676224                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       201856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          201856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18792384                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18792384                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3154                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             382412                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                385566                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293631                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293631                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               440241                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             53377697                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                53817938                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          440241                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             440241                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          40985499                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               40985499                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          40985499                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              440241                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            53377697                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               94803436                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        385568                       # Number of read requests accepted
+system.physmem.writeReqs                       293631                       # Number of write requests accepted
+system.physmem.readBursts                      385568                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     293631                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24654400                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21952                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18790528                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24676352                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18792384                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      343                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         137451                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               23999                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26321                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24635                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24488                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23208                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23662                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24431                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24245                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23683                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23822                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24823                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24044                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23228                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22920                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23793                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              23943                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18539                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         136756                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               24002                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26346                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24809                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24514                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23427                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23679                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24437                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24240                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23642                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23833                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24803                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              23968                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23115                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22838                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23649                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              23923                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18533                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               19811                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18919                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18907                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18016                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18404                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18977                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18938                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18573                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18106                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18839                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17716                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17343                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16932                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17725                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17816                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18961                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18917                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18087                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18414                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               18972                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18944                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18562                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18116                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18832                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17714                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17339                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16924                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17682                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17794                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    458345657000                       # Total gap between requests
+system.physmem.totGap                    458512983000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  385587                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  385568                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293595                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    380584                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       291                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 293631                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    380696                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       287                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,288 +144,286 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     8122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    15790                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    16374                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    16588                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    16668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    16965                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    16912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    16903                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    21550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    22491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17603                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17344                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    16827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      517                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      374                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      344                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      272                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6409                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6808                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17378                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17556                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17556                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17561                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17726                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17619                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17431                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        96485                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      354.073856                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     206.339683                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     360.153261                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          30862     31.99%     31.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        25245     26.16%     58.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9104      9.44%     67.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4981      5.16%     72.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3508      3.64%     76.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2549      2.64%     79.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1904      1.97%     81.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1721      1.78%     82.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16611     17.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          96485                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         16638                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.153564                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      214.001392                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          16625     99.92%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            8      0.05%     99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       146743                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      296.052173                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.726027                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.657452                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          54056     36.84%     36.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        40668     27.71%     64.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13398      9.13%     73.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7234      4.93%     78.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5377      3.66%     82.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3862      2.63%     84.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3026      2.06%     86.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2779      1.89%     88.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16343     11.14%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         146743                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17400                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.138621                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      209.351810                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17386     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            9      0.05%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            3      0.02%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           16638                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         16638                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.644008                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.412925                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.984420                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           15809     95.02%     95.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             568      3.41%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              13      0.08%     98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               7      0.04%     98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               5      0.03%     98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              61      0.37%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             106      0.64%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              27      0.16%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              20      0.12%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               3      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.04%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           16638                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2817376000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11128592250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1926225000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  6384991250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        7313.21                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16573.85                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total           17400                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17400                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.873678                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.805032                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.403017                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17211     98.91%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             144      0.83%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              22      0.13%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               3      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               3      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               2      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               2      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17400                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4188887000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11411855750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1926125000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10873.87                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28887.05                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          53.79                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          40.99                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       53.84                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       41.00                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29623.87                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          53.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          40.98                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       53.82                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       40.99                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.74                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.28                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     317177                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    216322                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.33                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.68                       # Row buffer hit rate for writes
-system.physmem.avgGap                       674849.54                       # Average gap between requests
-system.physmem.pageHitRate                      78.59                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               5.94                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     94835949                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              178789                       # Transaction distribution
-system.membus.trans_dist::ReadResp             178789                       # Transaction distribution
-system.membus.trans_dist::Writeback            293595                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           137451                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          137451                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206798                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206798                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1339671                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1339671                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1339671                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43467648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43467648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            43467648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               43467648                       # Total data (bytes)
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.82                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     316892                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215180                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.26                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.28                       # Row buffer hit rate for writes
+system.physmem.avgGap                       675079.00                       # Average gap between requests
+system.physmem.pageHitRate                      78.38                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     318092069500                       # Time in different power states
+system.physmem.memoryStateTime::REF       15310620000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      125106520750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     94803436                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              178732                       # Transaction distribution
+system.membus.trans_dist::ReadResp             178730                       # Transaction distribution
+system.membus.trans_dist::Writeback            293631                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           136756                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          136756                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206836                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206836                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1338277                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1338277                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1338277                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43468608                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43468608                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            43468608                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               43468608                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          3393086500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          3392871500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3901807065                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3899245261                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               205603387                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         205603387                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           9902113                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            117080162                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               114702381                       # Number of BTB hits
+system.cpu.branchPred.lookups               205578466                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         205578466                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           9901534                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            117029392                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               114680074                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.969100                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25060949                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1802781                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.992540                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                25067972                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1805738                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        916852867                       # number of cpu cycles simulated
+system.cpu.numCycles                        917184655                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          167425421                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1131697501                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   205603387                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          139763330                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     352285469                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                71105811                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              304521969                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                48109                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        252946                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           61                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 162022121                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2522560                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          885484431                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.378017                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.324314                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          167397549                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1131555944                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   205578466                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          139748046                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     352223186                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                71069558                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              304555909                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                47998                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        253720                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           58                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 161997167                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2518791                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          885395126                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.377906                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.324319                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                537271116     60.68%     60.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 23397088      2.64%     63.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 25262126      2.85%     66.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 27864383      3.15%     69.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 17763945      2.01%     71.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 22926561      2.59%     73.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 29429676      3.32%     77.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 26640012      3.01%     80.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                174929524     19.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                537236750     60.68%     60.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 23398648      2.64%     63.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 25254202      2.85%     66.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 27875613      3.15%     69.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 17735392      2.00%     71.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 22920767      2.59%     73.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 29423422      3.32%     77.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 26636426      3.01%     80.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                174913906     19.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            885484431                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.224249                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.234328                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                222585266                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             259638923                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 295357907                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              46951879                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               60950456                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2071410922                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                     1                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               60950456                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                256114538                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               114960463                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          17780                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 306643544                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             146797650                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2035254884                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 19108                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               24985336                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             106570240                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2138126742                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5150804980                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3273565222                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             40421                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            885395126                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.224141                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.233728                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                222654978                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             259567656                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 295344640                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              46911146                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               60916706                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2071122559                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                     3                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               60916706                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                256101136                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               115302026                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          17668                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 306678759                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             146378831                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2034998452                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 20313                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               24722090                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             106340501                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2137925960                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5150186774                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3273147321                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             41991                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                524085888                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1238                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1169                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 346813798                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            495843290                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           194454992                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         195400842                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         54863800                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1975546158                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               13200                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1772179882                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            484148                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       441719386                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    735183548                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          12648                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     885484431                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.001368                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.882860                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                523885106                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1288                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1219                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 345625652                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            495840221                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           194409464                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         195351813                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         54649414                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1975275020                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               13975                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1772033700                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            489443                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       441377933                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    734704744                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          13423                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     885395126                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.001404                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.883479                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           268514596     30.32%     30.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           152316057     17.20%     47.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           137257157     15.50%     63.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           131678995     14.87%     77.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            91673992     10.35%     88.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            56016548      6.33%     94.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            34412328      3.89%     98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            11858214      1.34%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1756544      0.20%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           268930520     30.37%     30.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           151513258     17.11%     47.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           137639902     15.55%     63.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           131544541     14.86%     77.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            91741507     10.36%     88.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            55934371      6.32%     94.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            34425935      3.89%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            11907214      1.34%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1757878      0.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       885484431                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       885395126                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 4914226     32.32%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                7684512     50.55%     82.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2604414     17.13%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 4908226     32.44%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7617033     50.35%     82.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2603803     17.21%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2627261      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1165804408     65.78%     65.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               352994      0.02%     65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               3880826      0.22%     66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  67      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2622809      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1165654727     65.78%     65.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               353604      0.02%     65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3880790      0.22%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  51      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.17% # Type of FU issued
@@ -451,84 +449,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.17% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            429279214     24.22%     90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           170235112      9.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            429257765     24.22%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170263954      9.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1772179882                       # Type of FU issued
-system.cpu.iq.rate                           1.932895                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    15203152                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008579                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4445517936                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2417485915                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1744947174                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               13559                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              50440                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         3261                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1784749273                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    6500                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        172700004                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1772033700                       # Type of FU issued
+system.cpu.iq.rate                           1.932036                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    15129062                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008538                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4445065609                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2416869316                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1744809668                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               15422                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              52952                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         3677                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1784532643                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    7310                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        172476568                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    111742246                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       386565                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       329489                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     45294806                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    111739174                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       389536                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       327115                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     45249278                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        14850                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           595                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        14923                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           606                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               60950456                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                66921774                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               7152270                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1975559358                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            792714                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             495844403                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            194454992                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               3102                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                4466928                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 83631                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         329489                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        5907148                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4425214                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10332362                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1753055321                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             424140880                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          19124561                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               60916706                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                67511680                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               7160873                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1975288995                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            782662                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             495841331                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            194409464                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               3475                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                4447984                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 83109                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         327115                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5905027                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4421064                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10326091                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1752917365                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             424127416                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          19116335                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    590933103                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                167483673                       # Number of branches executed
-system.cpu.iew.exec_stores                  166792223                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.912036                       # Inst execution rate
-system.cpu.iew.wb_sent                     1749807321                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1744950435                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1324909698                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1945755632                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    590948442                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                167460417                       # Number of branches executed
+system.cpu.iew.exec_stores                  166821026                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.911194                       # Inst execution rate
+system.cpu.iew.wb_sent                     1749660983                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1744813345                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1324821434                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1945562364                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.903196                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.680923                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.902358                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.680945                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       446599399                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       446329306                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9930890                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    824533975                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.854367                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.435928                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           9930052                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    824478420                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.854492                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.436428                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    332362619     40.31%     40.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    193345604     23.45%     63.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     63386723      7.69%     71.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     92493757     11.22%     82.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     24926721      3.02%     85.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27481357      3.33%     89.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9323499      1.13%     90.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11375843      1.38%     91.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     69837852      8.47%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    332514113     40.33%     40.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    193200456     23.43%     63.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     63249703      7.67%     71.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     92516022     11.22%     82.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     24944995      3.03%     85.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27441019      3.33%     89.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9353308      1.13%     90.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11434582      1.39%     91.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     69824222      8.47%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    824533975                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    824478420                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -539,245 +537,280 @@ system.cpu.commit.branches                  149758583                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              69837852                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass      1819099      0.12%      0.12% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        989721889     64.73%     64.85% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          306834      0.02%     64.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv          3878536      0.25%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       384102157     25.12%     90.24% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              69824222                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2730284223                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4012285085                       # The number of ROB writes
-system.cpu.timesIdled                         3361589                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        31368436                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2729972205                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4011712950                       # The number of ROB writes
+system.cpu.timesIdled                         3360559                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        31789529                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             826877109                       # Number of Instructions Simulated
-system.cpu.cpi                               1.108814                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.108814                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.901865                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.901865                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2716343034                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1420512883                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      3304                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       92                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 597249207                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                405429285                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               964722506                       # number of misc regfile reads
+system.cpu.cpi                               1.109215                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.109215                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.901538                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.901538                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2716307472                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1420359444                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      3689                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       68                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 597203936                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                405421760                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               964666021                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               699635153                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1908088                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1908087                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2330726                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       138856                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       138856                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       771730                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       771730                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       152619                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7676496                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7829115                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       437120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311344320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      311781440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         311781440                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus      8893312                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4908984370                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               699262879                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1907311                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1907308                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2330645                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq       138184                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp       138184                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       771752                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       771752                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       151977                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7674879                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7826856                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       438272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311332928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      311771200                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         311771200                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      8849920                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     4908820525                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     219136241                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     218162491                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3952027365                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3952575691                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              5320                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1037.745275                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           161872406                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6896                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          23473.376740                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              5306                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1035.768369                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           161848074                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6885                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          23507.345534                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1037.745275                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.506712                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.506712                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1576                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          238                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1228                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.769531                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         324190030                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        324190030                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    161874355                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       161874355                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     161874355                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        161874355                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    161874355                       # number of overall hits
-system.cpu.icache.overall_hits::total       161874355                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       147766                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        147766                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       147766                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         147766                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       147766                       # number of overall misses
-system.cpu.icache.overall_misses::total        147766                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    941588486                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    941588486                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    941588486                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    941588486                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    941588486                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    941588486                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    162022121                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    162022121                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    162022121                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    162022121                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    162022121                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    162022121                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000912                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000912                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000912                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000912                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000912                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000912                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6372.159265                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6372.159265                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6372.159265                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6372.159265                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6372.159265                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6372.159265                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          953                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1035.768369                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.505746                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.505746                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1579                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          250                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1221                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.770996                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         324139462                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        324139462                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    161850058                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       161850058                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     161850058                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        161850058                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    161850058                       # number of overall hits
+system.cpu.icache.overall_hits::total       161850058                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       147109                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        147109                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       147109                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         147109                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       147109                       # number of overall misses
+system.cpu.icache.overall_misses::total        147109                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    933905482                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    933905482                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    933905482                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    933905482                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    933905482                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    933905482                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    161997167                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    161997167                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    161997167                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    161997167                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    161997167                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    161997167                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000908                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000908                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000908                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000908                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000908                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000908                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6348.391207                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6348.391207                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6348.391207                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6348.391207                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6348.391207                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6348.391207                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          500                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 9                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs   119.125000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    55.555556                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1977                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1977                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1977                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1977                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1977                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1977                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       145789                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       145789                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       145789                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       145789                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       145789                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       145789                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    560897259                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    560897259                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    560897259                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    560897259                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    560897259                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    560897259                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000900                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000900                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000900                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000900                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000900                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000900                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3847.322219                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3847.322219                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3847.322219                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  3847.322219                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3847.322219                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  3847.322219                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1980                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1980                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1980                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1980                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1980                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1980                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       145129                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       145129                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       145129                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       145129                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       145129                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       145129                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    558373758                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    558373758                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    558373758                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    558373758                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    558373758                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    558373758                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000896                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000896                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000896                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000896                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000896                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000896                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3847.430617                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3847.430617                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3847.430617                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  3847.430617                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3847.430617                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  3847.430617                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           352905                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29664.192610                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3697555                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           385281                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.597034                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     198720708500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21111.841089                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   223.120798                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8329.230723                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.644282                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006809                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.254188                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.905279                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32376                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           352885                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29666.734110                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3697072                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           385254                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             9.596453                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     198759422000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21121.357308                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   222.494139                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8322.882663                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.644573                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006790                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.253994                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.905357                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32369                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          246                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11697                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20354                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.988037                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41242263                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41242263                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3684                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1586656                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1590340                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2330726                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2330726                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1427                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1427                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       564910                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       564910                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3684                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2151566                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2155250                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3684                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2151566                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2155250                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3147                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       175643                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       178790                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       137429                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       137429                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206820                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206820                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3147                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       382463                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        385610                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3147                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       382463                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       385610                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    236007500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  12735446955                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  12971454455                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      6722711                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      6722711                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14644727978                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14644727978                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    236007500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  27380174933                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  27616182433                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    236007500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  27380174933                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  27616182433                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         6831                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1762299                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1769130                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2330726                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2330726                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       138856                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       138856                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       771730                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       771730                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6831                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2534029                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2540860                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6831                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2534029                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2540860                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.460694                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099667                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.101061                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989723                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989723                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.267995                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.267995                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.460694                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.150931                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151764                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.460694                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.150931                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151764                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74994.439148                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72507.569075                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72551.342105                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    48.917703                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    48.917703                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70809.051243                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70809.051243                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74994.439148                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71589.081644                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71616.873092                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74994.439148                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71589.081644                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71616.873092                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          244                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11715                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20331                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987823                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         41235634                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41235634                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         3694                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1586604                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1590298                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2330645                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2330645                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1450                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1450                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       564894                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       564894                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3694                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2151498                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2155192                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3694                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2151498                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2155192                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3155                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       175578                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       178733                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       136734                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       136734                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206858                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206858                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3155                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       382436                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        385591                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3155                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       382436                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       385591                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    234254750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  12845252206                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  13079506956                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      6557218                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total      6557218                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14818754478                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14818754478                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    234254750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  27664006684                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  27898261434                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    234254750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  27664006684                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  27898261434                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         6849                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1762182                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1769031                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2330645                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2330645                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       138184                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       138184                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       771752                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       771752                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6849                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2533934                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2540783                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6849                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2533934                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2540783                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.460651                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099637                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.101034                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989507                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989507                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268037                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.268037                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.460651                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.150926                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151761                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.460651                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.150926                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151761                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74248.732171                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73159.804793                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73179.026570                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    47.956017                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    47.956017                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71637.328399                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71637.328399                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74248.732171                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72336.303810                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72351.951768                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74248.732171                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72336.303810                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72351.951768                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -786,176 +819,176 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       293595                       # number of writebacks
-system.cpu.l2cache.writebacks::total           293595                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3147                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175643                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       178790                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       137429                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       137429                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206820                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206820                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3147                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       382463                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       385610                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3147                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       382463                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       385610                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    196679500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10498248955                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10694928455                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1378003511                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1378003511                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12022304022                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12022304022                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    196679500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22520552977                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  22717232477                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    196679500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22520552977                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  22717232477                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.460694                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099667                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101061                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989723                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989723                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.267995                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.267995                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.460694                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150931                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151764                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.460694                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150931                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151764                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62497.457896                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59770.380573                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59818.381649                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.021306                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.021306                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58129.310618                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58129.310618                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62497.457896                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58882.958553                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58912.456827                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62497.457896                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58882.958553                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.456827                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       293631                       # number of writebacks
+system.cpu.l2cache.writebacks::total           293631                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3155                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175578                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       178733                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       136734                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       136734                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206858                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206858                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3155                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       382436                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       385591                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3155                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       382436                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       385591                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    194803750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10608113206                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10802916956                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1371755972                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1371755972                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12195917522                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12195917522                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    194803750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22804030728                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  22998834478                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    194803750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22804030728                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  22998834478                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.460651                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099637                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101034                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989507                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989507                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268037                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268037                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.460651                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150926                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151761                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.460651                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150926                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151761                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61744.453249                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60418.236943                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60441.647351                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.296079                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.296079                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58957.920516                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58957.920516                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61744.453249                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59628.358021                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59645.672430                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61744.453249                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59628.358021                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59645.672430                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2529933                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4088.224261                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           395924693                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2534029                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            156.243158                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1796857250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4088.224261                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998102                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998102                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2529836                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.247019                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           396128893                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2533932                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            156.329725                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1791176250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.247019                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998107                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998107                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          753                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3301                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          741                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3311                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         800965525                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        800965525                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    247184750                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       247184750                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148232864                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148232864                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     395417614                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        395417614                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    395417614                       # number of overall hits
-system.cpu.dcache.overall_hits::total       395417614                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2870796                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2870796                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       927338                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       927338                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3798134                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3798134                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3798134                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3798134                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  57044971459                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  57044971459                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  26405527365                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  26405527365                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  83450498824                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  83450498824                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  83450498824                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  83450498824                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250055546                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250055546                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         801380064                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        801380064                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    247376910                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       247376910                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148233547                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148233547                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     395610457                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        395610457                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    395610457                       # number of overall hits
+system.cpu.dcache.overall_hits::total       395610457                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2885954                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2885954                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       926655                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       926655                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3812609                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3812609                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3812609                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3812609                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57615846746                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  57615846746                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  26561972442                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  26561972442                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  84177819188                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  84177819188                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  84177819188                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  84177819188                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250262864                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250262864                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    399215748                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    399215748                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    399215748                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    399215748                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011481                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011481                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006217                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006217                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009514                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009514                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009514                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009514                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19870.785475                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19870.785475                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28474.544734                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28474.544734                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 21971.446722                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21971.446722                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21971.446722                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21971.446722                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         6569                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    399423066                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    399423066                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    399423066                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    399423066                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011532                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011532                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006212                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006212                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009545                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009545                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009545                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009545                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19964.229072                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19964.229072                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28664.359920                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28664.359920                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22078.796747                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22078.796747                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22078.796747                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22078.796747                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         6778                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               666                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               684                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.863363                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.909357                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2330726                       # number of writebacks
-system.cpu.dcache.writebacks::total           2330726                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1108238                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1108238                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17013                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        17013                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1125251                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1125251                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1125251                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1125251                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762558                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1762558                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       910325                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       910325                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2672883                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2672883                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2672883                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2672883                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30399879250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30399879250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24280652885                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  24280652885                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  54680532135                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  54680532135                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  54680532135                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  54680532135                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007049                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007049                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006103                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006103                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006695                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006695                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006695                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006695                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17247.590859                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17247.590859                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26672.510241                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26672.510241                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20457.510536                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20457.510536                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20457.510536                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20457.510536                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2330645                       # number of writebacks
+system.cpu.dcache.writebacks::total           2330645                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1123517                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1123517                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16974                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16974                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1140491                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1140491                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1140491                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1140491                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762437                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1762437                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       909681                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       909681                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2672118                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2672118                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2672118                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2672118                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30508505001                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30508505001                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24438286308                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  24438286308                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  54946791309                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  54946791309                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  54946791309                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  54946791309                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007042                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007042                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006099                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006099                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006690                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006690                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006690                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006690                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17310.408827                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17310.408827                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26864.677077                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26864.677077                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20563.010806                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20563.010806                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20563.010806                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20563.010806                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 4b881d03d..745f93407 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.885229                       # Nu
 sim_ticks                                885229328000                       # Number of ticks simulated
 final_tick                               885229328000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1633857                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3021184                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1749156833                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252248                       # Number of bytes of host memory used
-host_seconds                                   506.09                       # Real time elapsed on the host
+host_inst_rate                                1112999                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2058060                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1191542406                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 288080                       # Number of bytes of host memory used
+host_seconds                                   742.93                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -66,5 +66,40 @@ system.cpu.num_busy_cycles                 1770458657                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         149758583                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               1819099      0.12%      0.12% # Class of executed instruction
+system.cpu.op_class::IntAlu                 989721890     64.73%     64.85% # Class of executed instruction
+system.cpu.op_class::IntMult                   306834      0.02%     64.87% # Class of executed instruction
+system.cpu.op_class::IntDiv                   3878536      0.25%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::MemRead                384102157     25.12%     90.24% # Class of executed instruction
+system.cpu.op_class::MemWrite               149160186      9.76%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 1528988702                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index 0e5529ee3..2b67425b8 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.647873                       # Nu
 sim_ticks                                1647872849000                       # Number of ticks simulated
 final_tick                               1647872849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 782951                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1447764                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1560332529                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260992                       # Number of bytes of host memory used
-host_seconds                                  1056.10                       # Real time elapsed on the host
+host_inst_rate                                 654522                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1210285                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1304389188                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 297832                       # Number of bytes of host memory used
+host_seconds                                  1263.33                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -82,6 +82,41 @@ system.cpu.num_busy_cycles                 3295745698                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         149758583                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               1819099      0.12%      0.12% # Class of executed instruction
+system.cpu.op_class::IntAlu                 989721890     64.73%     64.85% # Class of executed instruction
+system.cpu.op_class::IntMult                   306834      0.02%     64.87% # Class of executed instruction
+system.cpu.op_class::IntDiv                   3878536      0.25%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.12% # Class of executed instruction
+system.cpu.op_class::MemRead                384102157     25.12%     90.24% # Class of executed instruction
+system.cpu.op_class::MemWrite               149160186      9.76%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 1528988702                       # Class of executed instruction
 system.cpu.icache.tags.replacements              1253                       # number of replacements
 system.cpu.icache.tags.tagsinuse           881.356491                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1068344252                       # Total number of references to valid blocks.
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 4b6099b52..16a9ab312 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.139926                       # Number of seconds simulated
-sim_ticks                                139926186500                       # Number of ticks simulated
-final_tick                               139926186500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.139925                       # Number of seconds simulated
+sim_ticks                                139925460500                       # Number of ticks simulated
+final_tick                               139925460500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 124689                       # Simulator instruction rate (inst/s)
-host_op_rate                                   124689                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43764124                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 271420                       # Number of bytes of host memory used
-host_seconds                                  3197.28                       # Real time elapsed on the host
+host_inst_rate                                 120046                       # Simulator instruction rate (inst/s)
+host_op_rate                                   120046                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               42134532                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271408                       # Number of bytes of host memory used
+host_seconds                                  3320.92                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          214976                       # Nu
 system.physmem.num_reads::cpu.inst               3359                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3969                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7328                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1536353                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1815357                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3351710                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1536353                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1536353                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1536353                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1815357                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3351710                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1536361                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1815367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3351727                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1536361                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1536361                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1536361                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1815367                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3351727                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7328                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7328                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    139926113000                       # Total gap between requests
+system.physmem.totGap                    139925387000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4589                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1831                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       611                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       237                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4503                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1916                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       608                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       242                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        58                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,28 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          558                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      480.917563                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     280.270360                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     415.877438                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            147     26.34%     26.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          107     19.18%     45.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           50      8.96%     54.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           28      5.02%     59.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           15      2.69%     62.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           15      2.69%     64.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            7      1.25%     66.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            5      0.90%     67.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          184     32.97%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            558                       # Bytes accessed per row activation
-system.physmem.totQLat                       59527000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 199924500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1345                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      345.790335                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     209.990258                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     340.082178                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            408     30.33%     30.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          331     24.61%     54.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          167     12.42%     67.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           84      6.25%     73.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           65      4.83%     78.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           45      3.35%     81.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           30      2.23%     84.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           29      2.16%     86.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          186     13.83%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1345                       # Bytes accessed per row activation
+system.physmem.totQLat                       64590750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 201990750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     36640000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                   103757500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8123.23                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14159.05                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        8814.24                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27282.27                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27564.24                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.35                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.35                       # Average system read bandwidth in MiByte/s
@@ -218,14 +216,18 @@ system.physmem.busUtilRead                       0.03                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5962                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5972                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.36                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.50                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19094720.66                       # Average gap between requests
-system.physmem.pageHitRate                      81.36                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.43                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      3351710                       # Throughput (bytes/s)
+system.physmem.avgGap                     19094621.59                       # Average gap between requests
+system.physmem.pageHitRate                      81.50                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     133853003250                       # Time in different power states
+system.physmem.memoryStateTime::REF        4672200000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1393983000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      3351727                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                4183                       # Transaction distribution
 system.membus.trans_dist::ReadResp               4183                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              3145                       # Transaction distribution
@@ -236,40 +238,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              468992                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 468992                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             8743500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             8819000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           68133000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           68224500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                53489673                       # Number of BP lookups
+system.cpu.branchPred.lookups                53489674                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          30685396                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          15149659                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             32882350                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups             32882351                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                15212538                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             46.263537                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             46.263535                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 8007516                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 20                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     94754639                       # DTB read hits
+system.cpu.dtb.read_hits                     94754638                       # DTB read hits
 system.cpu.dtb.read_misses                         21                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 94754660                       # DTB read accesses
-system.cpu.dtb.write_hits                    73521131                       # DTB write hits
+system.cpu.dtb.read_accesses                 94754659                       # DTB read accesses
+system.cpu.dtb.write_hits                    73521127                       # DTB write hits
 system.cpu.dtb.write_misses                        35                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73521166                       # DTB write accesses
-system.cpu.dtb.data_hits                    168275770                       # DTB hits
+system.cpu.dtb.write_accesses                73521162                       # DTB write accesses
+system.cpu.dtb.data_hits                    168275765                       # DTB hits
 system.cpu.dtb.data_misses                         56                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                168275826                       # DTB accesses
-system.cpu.itb.fetch_hits                    48611322                       # ITB hits
+system.cpu.dtb.data_accesses                168275821                       # DTB accesses
+system.cpu.itb.fetch_hits                    48611320                       # ITB hits
 system.cpu.itb.fetch_misses                     44520                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                48655842                       # ITB accesses
+system.cpu.itb.fetch_accesses                48655840                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -283,18 +285,18 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        279852374                       # number of cpu cycles simulated
+system.cpu.numCycles                        279850922                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken     29230505                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken     24259168                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads    280386572                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedNotTaken     24259169                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads    280386575                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites    159335859                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses    439722431                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses    439722434                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads    119631955                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites    100196481                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses    219828436                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards      100484576                       # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards      100484573                       # Number of Registers Read Through Forwarding Logic
 system.cpu.agen_unit.agens                  168485322                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect     14315634                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.execution_unit.predictedNotTakenIncorrect       833366                       # Number of Branches Incorrectly Predicted As Not Taken).
@@ -305,12 +307,12 @@ system.cpu.execution_unit.executions        205475782                       # Nu
 system.cpu.mult_div_unit.multiplies           2124323                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                     279400810                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                     279400656                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                            7266                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        13545705                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                        266306669                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         95.159696                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                            7212                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        13544259                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                        266306663                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         95.160188                       # Percentage of cycles cpu is active
 system.cpu.comLoads                          94754489                       # Number of Load instructions committed
 system.cpu.comStores                         73520729                       # Number of Store instructions committed
 system.cpu.comBranches                       44587532                       # Number of Branches instructions committed
@@ -322,81 +324,81 @@ system.cpu.committedInsts                   398664595                       # Nu
 system.cpu.committedOps                     398664595                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total             398664595                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.701974                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               0.701971                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.701974                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.424553                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         0.701971                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.424561                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.424553                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                 78104700                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                 201747674                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               72.090750                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                107200637                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                 172651737                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               61.693862                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                102637143                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                 177215231                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               63.324541                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                181107747                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                  98744627                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               35.284541                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                 90384400                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                 189467974                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               67.702829                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         1.424561                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                 78103252                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                 201747670                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               72.091122                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                107199191                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 172651731                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               61.694180                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                102635700                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 177215222                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               63.324866                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                181106302                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  98744620                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               35.284722                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 90382943                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                 189467979                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               67.703182                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements              1975                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1830.934233                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            48606787                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1830.939956                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            48606789                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              3903                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12453.698950                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          12453.699462                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1830.934233                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.894011                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.894011                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1830.939956                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.894014                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.894014                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          322                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1366                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          97226547                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         97226547                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     48606787                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        48606787                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      48606787                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         48606787                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     48606787                       # number of overall hits
-system.cpu.icache.overall_hits::total        48606787                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4535                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4535                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4535                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4535                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4535                       # number of overall misses
-system.cpu.icache.overall_misses::total          4535                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    279787250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    279787250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    279787250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    279787250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    279787250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    279787250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     48611322                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     48611322                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     48611322                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     48611322                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     48611322                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     48611322                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          97226543                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         97226543                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     48606789                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        48606789                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      48606789                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         48606789                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     48606789                       # number of overall hits
+system.cpu.icache.overall_hits::total        48606789                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4531                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4531                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4531                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4531                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4531                       # number of overall misses
+system.cpu.icache.overall_misses::total          4531                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    279235250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    279235250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    279235250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    279235250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    279235250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    279235250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     48611320                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     48611320                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     48611320                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     48611320                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     48611320                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     48611320                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000093                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000093                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000093                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000093                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000093                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000093                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61695.093716                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61695.093716                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61695.093716                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61695.093716                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61695.093716                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61695.093716                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61627.731185                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61627.731185                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61627.731185                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61627.731185                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61627.731185                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61627.731185                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          330                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
@@ -405,38 +407,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          110
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          632                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          632                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          632                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          632                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          632                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          632                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          628                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          628                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          628                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          628                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          628                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          628                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3903                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         3903                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         3903                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total         3903                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         3903                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         3903                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    243875500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    243875500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    243875500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    243875500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    243875500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    243875500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    243851250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    243851250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    243851250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    243851250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    243851250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    243851250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000080                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000080                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000080                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62484.114783                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62484.114783                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62484.114783                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 62484.114783                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62484.114783                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 62484.114783                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62477.901614                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62477.901614                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62477.901614                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 62477.901614                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62477.901614                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 62477.901614                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                 3981070                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput                 3981091                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq           4850                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          4850                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          649                       # Transaction distribution
@@ -452,26 +454,26 @@ system.cpu.toL2Bus.data_through_bus            557056                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy        5001000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6445500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6455750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6649999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6676249                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3906.832917                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         3906.848534                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                753                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4717                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.159635                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   370.533355                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2908.730052                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   627.569510                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   370.535307                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2908.741321                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   627.571906                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.011308                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088767                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088768                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.019152                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.119227                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.119228                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         4717                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          127                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          564                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3928                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.143951                       # Percentage of cache occupancy per task id
@@ -501,17 +503,17 @@ system.cpu.l2cache.demand_misses::total          7328                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3359                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3969                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7328                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    234486500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     61133000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    295619500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    230289500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    230289500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    234486500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    291422500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    525909000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    234486500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    291422500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    525909000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    234462250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     60397500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    294859750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    231906750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    231906750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    234462250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    292304250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    526766500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    234462250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    292304250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    526766500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         3903                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          947                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         4850                       # number of ReadReq accesses(hits+misses)
@@ -536,17 +538,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.909745                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.860620                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.955925                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.909745                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69808.425127                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74190.533981                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70671.647143                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73224.006359                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73224.006359                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69808.425127                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73424.666163                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71767.057860                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69808.425127                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73424.666163                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71767.057860                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69801.205716                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73297.936893                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70490.019125                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73738.235294                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73738.235294                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69801.205716                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73646.825397                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71884.074782                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69801.205716                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73646.825397                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71884.074782                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -566,17 +568,17 @@ system.cpu.l2cache.demand_mshr_misses::total         7328
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3359                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3969                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7328                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    192420000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     50867000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    243287000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    191492500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    191492500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    192420000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    242359500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    434779500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    192420000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    242359500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    434779500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    192372250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     50131500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    242503750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    193005250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    193005250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    192372250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    243136750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    435509000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    192372250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    243136750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    435509000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.860620                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.870116                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.862474                       # mshr miss rate for ReadReq accesses
@@ -588,27 +590,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.909745
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.860620                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955925                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.909745                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57284.906222                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61731.796117                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58160.889314                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60887.917329                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60887.917329                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57284.906222                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61063.114135                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.263646                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57284.906222                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61063.114135                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.263646                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57270.690682                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60839.199029                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57973.643318                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61368.918919                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61368.918919                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57270.690682                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61258.944318                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59430.813319                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57270.690682                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61258.944318                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59430.813319                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements               764                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3284.879976                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3284.892778                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168254239                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4152                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          40523.660645                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3284.879976                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.801973                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.801973                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3284.892778                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.801976                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.801976                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3388                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
@@ -618,30 +620,30 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4         3109
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.827148                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         336554588                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        336554588                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     94753181                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94753181                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73501058                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73501058                       # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     94753183                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94753183                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73501056                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73501056                       # number of WriteReq hits
 system.cpu.dcache.demand_hits::cpu.data     168254239                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total        168254239                       # number of demand (read+write) hits
 system.cpu.dcache.overall_hits::cpu.data    168254239                       # number of overall hits
 system.cpu.dcache.overall_hits::total       168254239                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1308                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1308                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19671                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19671                       # number of WriteReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data         1306                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1306                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19673                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19673                       # number of WriteReq misses
 system.cpu.dcache.demand_misses::cpu.data        20979                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total          20979                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data        20979                       # number of overall misses
 system.cpu.dcache.overall_misses::total         20979                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     87087749                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     87087749                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1166784250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1166784250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1253871999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1253871999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1253871999                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1253871999                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     86414249                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     86414249                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1153377000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1153377000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1239791249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1239791249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1239791249                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1239791249                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     94754489                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     94754489                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
@@ -658,28 +660,28 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000125
 system.cpu.dcache.demand_miss_rate::total     0.000125                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000125                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000125                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66580.847859                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66580.847859                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59314.943318                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59314.943318                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59767.958387                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59767.958387                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59767.958387                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59767.958387                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        33117                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66167.112557                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66167.112557                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58627.408123                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 58627.408123                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59096.775299                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59096.775299                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59096.775299                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59096.775299                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        33700                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               591                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               588                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    56.035533                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    57.312925                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          649                       # number of writebacks
 system.cpu.dcache.writebacks::total               649                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          358                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          358                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16469                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16469                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          356                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          356                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16471                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16471                       # number of WriteReq MSHR hits
 system.cpu.dcache.demand_mshr_hits::cpu.data        16827                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total        16827                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.overall_mshr_hits::cpu.data        16827                       # number of overall MSHR hits
@@ -692,14 +694,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4152
 system.cpu.dcache.demand_mshr_misses::total         4152                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4152                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4152                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     63587751                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     63587751                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    234030250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    234030250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    297618001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    297618001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    297618001                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    297618001                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     62852251                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     62852251                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    235649500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    235649500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    298501751                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    298501751                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    298501751                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    298501751                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
@@ -708,14 +710,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66934.474737                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66934.474737                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73088.772642                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73088.772642                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71680.636079                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71680.636079                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71680.636079                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71680.636079                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66160.264211                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66160.264211                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73594.472205                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73594.472205                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71893.485308                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71893.485308                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71893.485308                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71893.485308                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 8d6cbc006..1b726b2c6 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.077418                       # Number of seconds simulated
-sim_ticks                                 77417500000                       # Number of ticks simulated
-final_tick                                77417500000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.077558                       # Number of seconds simulated
+sim_ticks                                 77558022000                       # Number of ticks simulated
+final_tick                                77558022000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 187521                       # Simulator instruction rate (inst/s)
-host_op_rate                                   187521                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               38653802                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273448                       # Number of bytes of host memory used
-host_seconds                                  2002.84                       # Real time elapsed on the host
+host_inst_rate                                 184821                       # Simulator instruction rate (inst/s)
+host_op_rate                                   184821                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               38166348                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 274476                       # Number of bytes of host memory used
+host_seconds                                  2032.10                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            220992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            255488                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               476480                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       220992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          220992                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3453                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3992                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7445                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2854548                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3300132                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6154681                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2854548                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2854548                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2854548                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3300132                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6154681                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7445                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            221184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            255360                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               476544                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       221184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          221184                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3456                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3990                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7446                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2851852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3292503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6144355                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2851852                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2851852                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2851852                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3292503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6144355                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7446                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7445                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7446                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   476480                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   476544                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    476480                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    476544                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 524                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 654                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 449                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 526                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 653                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 448                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 600                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 447                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 455                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 518                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 516                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 524                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 436                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 439                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 405                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                339                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                306                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                414                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                541                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                454                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                543                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                452                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                379                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     77417410500                       # Total gap between requests
+system.physmem.totGap                     77557932500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7445                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7446                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4367                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2023                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       735                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       258                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4325                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2039                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       758                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       260                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,90 +186,92 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          629                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      457.157393                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     257.861215                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     416.549348                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            187     29.73%     29.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          122     19.40%     49.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           53      8.43%     57.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           24      3.82%     61.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           18      2.86%     64.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           15      2.38%     66.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            7      1.11%     67.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            3      0.48%     68.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          200     31.80%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            629                       # Bytes accessed per row activation
-system.physmem.totQLat                       62316500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 205595250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37225000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                   106053750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8370.25                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14244.96                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples         1343                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      351.356664                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     209.733129                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.313012                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            424     31.57%     31.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          321     23.90%     55.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          148     11.02%     66.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           81      6.03%     72.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           60      4.47%     76.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           47      3.50%     80.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           36      2.68%     83.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           32      2.38%     85.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          194     14.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1343                       # Bytes accessed per row activation
+system.physmem.totQLat                       64732500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 204345000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37230000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8693.59                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27615.21                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           6.15                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27443.59                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           6.14                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        6.15                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        6.14                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6071                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6090                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.54                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.79                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     10398577.64                       # Average gap between requests
-system.physmem.pageHitRate                      81.54                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.52                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      6154681                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                4313                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4313                       # Transaction distribution
+system.physmem.avgGap                     10416053.25                       # Average gap between requests
+system.physmem.pageHitRate                      81.79                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      73756071000                       # Time in different power states
+system.physmem.memoryStateTime::REF        2589600000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1205652750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      6144355                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                4314                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4314                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              3132                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             3132                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14890                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14890                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       476480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              476480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 476480                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14892                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14892                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       476544                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              476544                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 476544                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             9329500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9331000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           69519750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           69621500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                50246060                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          29233966                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1199560                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             25853120                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23225371                       # Number of BTB hits
+system.cpu.branchPred.lookups                50345417                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          29291104                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1215969                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             26826828                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                23310375                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             89.835853                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9012456                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1102                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             86.892028                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9011574                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1048                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    101798719                       # DTB read hits
-system.cpu.dtb.read_misses                      78049                       # DTB read misses
-system.cpu.dtb.read_acv                         48607                       # DTB read access violations
-system.cpu.dtb.read_accesses                101876768                       # DTB read accesses
-system.cpu.dtb.write_hits                    78433341                       # DTB write hits
-system.cpu.dtb.write_misses                      1499                       # DTB write misses
-system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_accesses                78434840                       # DTB write accesses
-system.cpu.dtb.data_hits                    180232060                       # DTB hits
-system.cpu.dtb.data_misses                      79548                       # DTB misses
-system.cpu.dtb.data_acv                         48609                       # DTB access violations
-system.cpu.dtb.data_accesses                180311608                       # DTB accesses
-system.cpu.itb.fetch_hits                    50221171                       # ITB hits
-system.cpu.itb.fetch_misses                       373                       # ITB misses
+system.cpu.dtb.read_hits                    101817662                       # DTB read hits
+system.cpu.dtb.read_misses                      78218                       # DTB read misses
+system.cpu.dtb.read_acv                         48604                       # DTB read access violations
+system.cpu.dtb.read_accesses                101895880                       # DTB read accesses
+system.cpu.dtb.write_hits                    78432784                       # DTB write hits
+system.cpu.dtb.write_misses                      1485                       # DTB write misses
+system.cpu.dtb.write_acv                            3                       # DTB write access violations
+system.cpu.dtb.write_accesses                78434269                       # DTB write accesses
+system.cpu.dtb.data_hits                    180250446                       # DTB hits
+system.cpu.dtb.data_misses                      79703                       # DTB misses
+system.cpu.dtb.data_acv                         48607                       # DTB access violations
+system.cpu.dtb.data_accesses                180330149                       # DTB accesses
+system.cpu.itb.fetch_hits                    50303452                       # ITB hits
+system.cpu.itb.fetch_misses                       374                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                50221544                       # ITB accesses
+system.cpu.itb.fetch_accesses                50303826                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -283,105 +285,105 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        154835002                       # number of cpu cycles simulated
+system.cpu.numCycles                        155116046                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           51111974                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      448661331                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    50246060                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           32237827                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      78769244                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6113875                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               19767092                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  184                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         10735                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  50221171                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                406319                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          154534598                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.903307                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.325117                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           51199541                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      449368258                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    50345417                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           32321949                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      78906536                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6198249                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               19757533                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  186                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         10530                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           40                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  50303452                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                417357                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          154817464                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.902568                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.324801                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 75765354     49.03%     49.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4278797      2.77%     51.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  6878880      4.45%     56.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5365294      3.47%     59.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11742013      7.60%     67.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  7808130      5.05%     72.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5610858      3.63%     76.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1827134      1.18%     77.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35258138     22.82%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 75910928     49.03%     49.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4292900      2.77%     51.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6887952      4.45%     56.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5378426      3.47%     59.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 11777021      7.61%     67.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  7819850      5.05%     72.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5605225      3.62%     76.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1835804      1.19%     77.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 35309358     22.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            154534598                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.324514                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.897674                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 56469798                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              15107857                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  74141890                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3943911                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4871142                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              9469846                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4291                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              444777840                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 12202                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4871142                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 59608441                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4896661                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         418311                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  75037002                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               9703041                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              440308504                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   162                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  18256                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               8013879                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           287257669                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             578877349                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        413693152                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         165184196                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            154817464                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.324566                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.896981                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 56574106                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              15095997                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  74265148                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3943304                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4938909                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              9501741                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4271                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              445384778                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 12171                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4938909                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 59715078                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4876409                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         419715                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  75168099                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               9699254                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              440873304                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   165                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  26337                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               8019570                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           287561386                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             579637001                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        414043720                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         165593280                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27725340                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              36879                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            302                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  27905569                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            104673865                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            80579462                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           8919028                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          6395315                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  408114726                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 290                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 401714158                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            971094                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        32406044                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     15222181                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             75                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     154534598                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.599510                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.995704                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 28029057                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              36796                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            273                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  27775978                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            104708247                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            80640808                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           8927201                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          6403621                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  408496151                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 259                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 401987429                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            970780                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        32786458                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     15509808                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             44                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     154817464                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.596525                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.995719                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            28287072     18.30%     18.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            25862273     16.74%     35.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25616970     16.58%     51.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            24199972     15.66%     67.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            21258651     13.76%     81.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15520360     10.04%     91.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             8472156      5.48%     96.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3988463      2.58%     99.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1328681      0.86%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            28475792     18.39%     18.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            25868593     16.71%     35.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25622739     16.55%     51.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            24250418     15.66%     67.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            21294797     13.75%     81.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15492171     10.01%     91.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8526240      5.51%     96.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3969091      2.56%     99.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1317623      0.85%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       154534598                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       154817464                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   33844      0.29%      0.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   33961      0.29%      0.29% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      0.29% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                 57389      0.49%      0.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                  4757      0.04%      0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  5293      0.04%      0.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              1937864     16.39%     17.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1755771     14.85%     32.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                 60734      0.51%      0.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                  4893      0.04%      0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  5332      0.05%      0.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              1940982     16.38%     17.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1755182     14.82%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.09% # attempts to use FU when none available
@@ -403,118 +405,118 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.09% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5068587     42.87%     74.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2960872     25.04%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5081532     42.89%     74.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2964138     25.02%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             155710180     38.76%     38.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2126250      0.53%     39.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             155819959     38.76%     38.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2126233      0.53%     39.30% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            32800446      8.17%     47.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7495713      1.87%     49.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2793863      0.70%     50.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16555604      4.12%     54.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1576822      0.39%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            103379318     25.73%     80.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            79242381     19.73%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            32858833      8.17%     47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7513495      1.87%     49.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2793143      0.69%     50.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16555819      4.12%     54.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1584570      0.39%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            103403919     25.72%     80.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            79297877     19.73%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              401714158                       # Type of FU issued
-system.cpu.iq.rate                           2.594466                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    11824377                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.029435                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          633974130                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         260128925                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    234699525                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           336784255                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          180440959                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    161353653                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              241409796                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               172095158                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         15058802                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              401987429                       # Type of FU issued
+system.cpu.iq.rate                           2.591527                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    11846754                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.029470                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          634443309                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         260407475                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    234772020                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           337166547                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          180924376                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    161447715                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              241509351                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               172291251                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         15019191                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      9919378                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       112340                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        48844                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      7058733                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      9953760                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       111699                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        48994                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7120079                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       260875                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3830                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       260856                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3918                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4871142                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2518143                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                371002                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           432897365                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            126094                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             104673865                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             80579462                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                290                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     87                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    80                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          48844                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         943634                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       406077                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1349711                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             398212292                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             101925424                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3501866                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4938909                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2515248                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                368703                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           433326930                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            121866                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             104708247                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             80640808                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                259                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     84                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    84                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          48994                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         963874                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       408153                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1372027                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             398387733                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             101944518                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3599696                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      24782349                       # number of nop insts executed
-system.cpu.iew.exec_refs                    180360292                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 46546611                       # Number of branches executed
-system.cpu.iew.exec_stores                   78434868                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.571849                       # Inst execution rate
-system.cpu.iew.wb_sent                      396683492                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     396053178                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 193508627                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 271030051                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      24830520                       # number of nop insts executed
+system.cpu.iew.exec_refs                    180378816                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 46578472                       # Number of branches executed
+system.cpu.iew.exec_stores                   78434298                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.568321                       # Inst execution rate
+system.cpu.iew.wb_sent                      396855480                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     396219735                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 193571599                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 271152784                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.557905                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.713975                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.554344                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.713884                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        34263124                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        34693909                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1195351                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    149663456                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.663740                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.995900                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1211780                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    149878555                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.659917                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.995453                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     55327244     36.97%     36.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     22535122     15.06%     52.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13022576      8.70%     60.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11475094      7.67%     68.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8197799      5.48%     73.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      5452875      3.64%     77.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      5172237      3.46%     80.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3274038      2.19%     83.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     25206471     16.84%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     55522565     37.05%     37.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     22544256     15.04%     52.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13057076      8.71%     60.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11473348      7.66%     68.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8182798      5.46%     73.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      5442795      3.63%     77.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      5157024      3.44%     80.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3290724      2.20%     83.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     25207969     16.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    149663456                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    149878555                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
 system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -525,228 +527,263 @@ system.cpu.commit.branches                   44587533                       # Nu
 system.cpu.commit.fp_insts                  155295106                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 316365839                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              25206471                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass     23123356      5.80%      5.80% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        145805186     36.57%     42.37% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2124322      0.53%     42.91% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     42.91% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd       31467419      7.89%     50.80% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp        7072549      1.77%     52.57% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt        2735231      0.69%     53.26% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult      16498021      4.14%     57.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv        1563283      0.39%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     57.79% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        94754487     23.77%     81.56% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       73520729     18.44%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total         398664583                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              25207969                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    557381715                       # The number of ROB reads
-system.cpu.rob.rob_writes                   870735186                       # The number of ROB writes
-system.cpu.timesIdled                            3600                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          300404                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    558026101                       # The number of ROB reads
+system.cpu.rob.rob_writes                   871664409                       # The number of ROB writes
+system.cpu.timesIdled                            3592                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          298582                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
 system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             375574808                       # Number of Instructions Simulated
-system.cpu.cpi                               0.412261                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.412261                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.425645                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.425645                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                398046268                       # number of integer regfile reads
-system.cpu.int_regfile_writes               170097469                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 156518592                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                104028166                       # number of floating regfile writes
+system.cpu.cpi                               0.413010                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.413010                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.421251                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.421251                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                398150942                       # number of integer regfile reads
+system.cpu.int_regfile_writes               170167166                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 156627293                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                104100522                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                 7364950                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq           5055                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          5055                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          661                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3193                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3193                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8124                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9033                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             17157                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       259968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       310208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         570176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            570176                       # Total data (bytes)
+system.cpu.toL2Bus.throughput                 7339228                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           5048                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5048                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          655                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3191                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3191                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8126                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9007                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             17133                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       260032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         569216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            569216                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        5115500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy        5102000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6740250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6747750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6663250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6703500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              2135                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1832.551439                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            50215552                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4062                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12362.272772                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2136                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1830.591331                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            50297811                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4063                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          12379.476003                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1832.551439                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.894801                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.894801                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1830.591331                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.893843                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.893843                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1927                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1346                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          331                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1340                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.940918                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         100446404                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        100446404                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     50215552                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        50215552                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      50215552                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         50215552                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     50215552                       # number of overall hits
-system.cpu.icache.overall_hits::total        50215552                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5619                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5619                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5619                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5619                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5619                       # number of overall misses
-system.cpu.icache.overall_misses::total          5619                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    332785750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    332785750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    332785750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    332785750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    332785750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    332785750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     50221171                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     50221171                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     50221171                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     50221171                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     50221171                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     50221171                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         100610967                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        100610967                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     50297811                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        50297811                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      50297811                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         50297811                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     50297811                       # number of overall hits
+system.cpu.icache.overall_hits::total        50297811                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5641                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5641                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5641                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5641                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5641                       # number of overall misses
+system.cpu.icache.overall_misses::total          5641                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    335074000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    335074000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    335074000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    335074000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    335074000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    335074000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     50303452                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     50303452                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     50303452                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     50303452                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     50303452                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     50303452                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000112                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000112                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000112                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000112                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000112                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000112                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59225.084535                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 59225.084535                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 59225.084535                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 59225.084535                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 59225.084535                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 59225.084535                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          251                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59399.751817                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 59399.751817                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 59399.751817                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 59399.751817                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 59399.751817                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 59399.751817                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          446                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 9                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    83.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    49.555556                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1557                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1557                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1557                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1557                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1557                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1557                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4062                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4062                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4062                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4062                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4062                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4062                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    250275250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    250275250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    250275250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    250275250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    250275250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    250275250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1578                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1578                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1578                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1578                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1578                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1578                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4063                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4063                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4063                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4063                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4063                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4063                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    249433250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    249433250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    249433250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    249433250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    249433250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    249433250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000081                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000081                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000081                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61613.798621                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61613.798621                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61613.798621                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61613.798621                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61613.798621                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61613.798621                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61391.397982                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61391.397982                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61391.397982                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61391.397982                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61391.397982                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61391.397982                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4014.912123                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                831                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4004.954677                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                821                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4850                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.171340                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.169278                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   372.322070                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2981.516963                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   661.073090                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011362                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090989                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.020174                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.122525                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   371.321858                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2975.631846                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   658.000972                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011332                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090809                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.020081                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.122222                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         4850                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          114                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          550                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4037                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          147                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          573                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4031                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148010                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            79315                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           79315                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst          609                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          133                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total            742                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks          661                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          661                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           61                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          609                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          194                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total             803                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          609                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          194                       # number of overall hits
-system.cpu.l2cache.overall_hits::total            803                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3453                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          860                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4313                       # number of ReadReq misses
+system.cpu.l2cache.tags.tag_accesses            79193                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           79193                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst          607                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          127                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total            734                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          655                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          655                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           59                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           59                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          607                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          186                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total             793                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          607                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          186                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            793                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3456                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          858                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4314                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         3132                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         3132                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3453                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         3992                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7445                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3453                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         3992                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7445                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    240112000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     66837250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    306949250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    229848000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    229848000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    240112000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    296685250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    536797250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    240112000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    296685250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    536797250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         4062                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          993                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5055                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks          661                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          661                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3193                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         3193                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4062                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4186                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8248                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4062                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4186                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8248                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.850074                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.866062                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.853215                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.980896                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.980896                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.850074                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.953655                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.902643                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.850074                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.953655                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.902643                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69537.214017                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77717.732558                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71168.386274                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73386.973180                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73386.973180                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69537.214017                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74319.952405                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72101.712559                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69537.214017                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74319.952405                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72101.712559                       # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst         3456                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3990                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7446                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3456                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3990                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7446                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    239290500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     65195250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    304485750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    229768250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    229768250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    239290500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    294963500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    534254000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    239290500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    294963500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    534254000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4063                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          985                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         5048                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          655                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          655                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3191                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3191                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4063                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4176                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8239                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4063                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4176                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8239                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.850603                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.871066                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.854596                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981510                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.981510                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.850603                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.955460                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.903750                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.850603                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.955460                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.903750                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69239.149306                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75985.139860                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70580.841446                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73361.510217                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73361.510217                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69239.149306                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73925.689223                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71750.470051                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69239.149306                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73925.689223                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71750.470051                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -755,155 +792,155 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3453                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          860                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4313                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3456                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          858                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4314                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3132                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         3132                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3453                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3992                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7445                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3453                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3992                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7445                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    196358500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     56239750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    252598250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    191312000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    191312000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    196358500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    247551750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    443910250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    196358500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    247551750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    443910250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.850074                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.866062                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.853215                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.980896                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980896                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.850074                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.953655                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.902643                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.850074                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.953655                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.902643                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56866.058500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65395.058140                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58566.716902                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61083.014049                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61083.014049                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56866.058500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62011.961423                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59625.285426                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56866.058500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62011.961423                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59625.285426                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3456                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3990                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7446                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3456                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3990                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7446                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    195490000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     54612750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    250102750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    191098750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    191098750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    195490000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    245711500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    441201500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    195490000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    245711500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    441201500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.850603                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.871066                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.854596                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981510                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981510                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.850603                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955460                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.903750                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.850603                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955460                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.903750                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56565.393519                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63651.223776                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57974.675475                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61014.926564                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61014.926564                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56565.393519                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61581.829574                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59253.491808                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56565.393519                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61581.829574                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59253.491808                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements               784                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3296.614513                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           159974752                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4186                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          38216.615385                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements               774                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3296.550770                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           160033276                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4176                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          38322.144636                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3296.614513                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.804838                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.804838                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3296.550770                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.804822                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.804822                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3402                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3118                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3119                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.830566                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         319997054                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        319997054                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     86473896                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86473896                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73500850                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73500850                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            6                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            6                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     159974746                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        159974746                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    159974746                       # number of overall hits
-system.cpu.dcache.overall_hits::total       159974746                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1803                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1803                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19879                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19879                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21682                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21682                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21682                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21682                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    116178750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    116178750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1100405079                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1100405079                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1216583829                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1216583829                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1216583829                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1216583829                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     86475699                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86475699                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         320114012                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        320114012                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     86532394                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86532394                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73500878                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73500878                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            4                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            4                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     160033272                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        160033272                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    160033272                       # number of overall hits
+system.cpu.dcache.overall_hits::total       160033272                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1791                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1791                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19851                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19851                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21642                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21642                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21642                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21642                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    112278750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    112278750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1112532070                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1112532070                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1224810820                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1224810820                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1224810820                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1224810820                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86534185                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86534185                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    159996428                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    159996428                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    159996428                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    159996428                       # number of overall (read+write) accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    160054914                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    160054914                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    160054914                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    160054914                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000021                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000021                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000270                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000270                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000136                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000136                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000136                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000136                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64436.356073                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 64436.356073                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55355.152623                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55355.152623                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56110.314039                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56110.314039                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 56110.314039                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 56110.314039                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        40445                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000135                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000135                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000135                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000135                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62690.536013                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62690.536013                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56044.132286                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 56044.132286                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56594.160429                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56594.160429                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 56594.160429                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 56594.160429                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        40644                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               670                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               681                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    60.365672                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    59.682819                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          661                       # number of writebacks
-system.cpu.dcache.writebacks::total               661                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          810                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          810                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16686                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16686                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        17496                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        17496                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        17496                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        17496                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          993                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          993                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3193                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3193                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4186                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4186                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4186                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4186                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     69211250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     69211250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    233753500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    233753500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    302964750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    302964750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    302964750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    302964750                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks          655                       # number of writebacks
+system.cpu.dcache.writebacks::total               655                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          806                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          806                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16660                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16660                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        17466                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        17466                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        17466                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        17466                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          985                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          985                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3191                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3191                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4176                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4176                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4176                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4176                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     67500250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     67500250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    233649750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    233649750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    301150000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    301150000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    301150000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    301150000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -912,14 +949,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000026
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69699.144008                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69699.144008                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73208.111494                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73208.111494                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72375.716675                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72375.716675                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72375.716675                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72375.716675                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68528.172589                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68528.172589                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73221.482294                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73221.482294                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72114.463602                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72114.463602                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72114.463602                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72114.463602                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 1fcce529e..4cd29aa5b 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.199332                       # Nu
 sim_ticks                                199332411500                       # Number of ticks simulated
 final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3310187                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3310187                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1655094150                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226700                       # Number of bytes of host memory used
-host_seconds                                   120.44                       # Real time elapsed on the host
+host_inst_rate                                2589605                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2589605                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1294803220                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262692                       # Number of bytes of host memory used
+host_seconds                                   153.95                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -95,5 +95,40 @@ system.cpu.num_busy_cycles                  398664824                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          44587532                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              23123356      5.80%      5.80% # Class of executed instruction
+system.cpu.op_class::IntAlu                 145805196     36.57%     42.37% # Class of executed instruction
+system.cpu.op_class::IntMult                  2124322      0.53%     42.91% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     42.91% # Class of executed instruction
+system.cpu.op_class::FloatAdd                31467419      7.89%     50.80% # Class of executed instruction
+system.cpu.op_class::FloatCmp                 7072549      1.77%     52.57% # Class of executed instruction
+system.cpu.op_class::FloatCvt                 2735231      0.69%     53.26% # Class of executed instruction
+system.cpu.op_class::FloatMult               16498021      4.14%     57.40% # Class of executed instruction
+system.cpu.op_class::FloatDiv                 1563283      0.39%     57.79% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::MemRead                 94754510     23.77%     81.56% # Class of executed instruction
+system.cpu.op_class::MemWrite                73520764     18.44%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  398664651                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 504ea284e..c52832ea0 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.567335                       # Nu
 sim_ticks                                567335093000                       # Number of ticks simulated
 final_tick                               567335093000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1478735                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1478735                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2104370306                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235572                       # Number of bytes of host memory used
-host_seconds                                   269.60                       # Real time elapsed on the host
+host_inst_rate                                1080224                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1080224                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1537254294                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271408                       # Number of bytes of host memory used
+host_seconds                                   369.06                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -101,6 +101,41 @@ system.cpu.num_busy_cycles                 1134670186                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          44587535                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              23123356      5.80%      5.80% # Class of executed instruction
+system.cpu.op_class::IntAlu                 145805208     36.57%     42.37% # Class of executed instruction
+system.cpu.op_class::IntMult                  2124322      0.53%     42.91% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     42.91% # Class of executed instruction
+system.cpu.op_class::FloatAdd                31467419      7.89%     50.80% # Class of executed instruction
+system.cpu.op_class::FloatCmp                 7072549      1.77%     52.57% # Class of executed instruction
+system.cpu.op_class::FloatCvt                 2735231      0.69%     53.26% # Class of executed instruction
+system.cpu.op_class::FloatMult               16498021      4.14%     57.40% # Class of executed instruction
+system.cpu.op_class::FloatDiv                 1563283      0.39%     57.79% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.79% # Class of executed instruction
+system.cpu.op_class::MemRead                 94754511     23.77%     81.56% # Class of executed instruction
+system.cpu.op_class::MemWrite                73520765     18.44%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  398664665                       # Class of executed instruction
 system.cpu.icache.tags.replacements              1769                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1795.138964                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           398660993                       # Total number of references to valid blocks.
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 648c5ea6f..9ff03dde6 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.068245                       # Number of seconds simulated
-sim_ticks                                 68245472000                       # Number of ticks simulated
-final_tick                                68245472000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.068540                       # Number of seconds simulated
+sim_ticks                                 68540241500                       # Number of ticks simulated
+final_tick                                68540241500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 123424                       # Simulator instruction rate (inst/s)
-host_op_rate                                   157791                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               30849723                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 321440                       # Number of bytes of host memory used
-host_seconds                                  2212.19                       # Real time elapsed on the host
+host_inst_rate                                 122061                       # Simulator instruction rate (inst/s)
+host_op_rate                                   156050                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               30641006                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321880                       # Number of bytes of host memory used
+host_seconds                                  2236.88                       # Real time elapsed on the host
 sim_insts                                   273036725                       # Number of instructions simulated
 sim_ops                                     349064449                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            193792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            272576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            193920                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            272448                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               466368                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       193792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          193792                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3028                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               4259                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst       193920                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          193920                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3030                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               4257                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7287                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2839632                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3994053                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6833684                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2839632                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2839632                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2839632                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3994053                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6833684                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7288                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst              2829287                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3975008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6804295                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2829287                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2829287                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2829287                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3975008                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6804295                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7287                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7288                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7287                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   466432                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   466368                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    466432                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    466368                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 606                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs              2                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 604                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 802                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 608                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 526                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 441                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 356                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 162                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 220                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 205                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 290                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 607                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 525                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 444                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 161                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 221                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 206                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 292                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                324                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                417                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                531                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                687                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                611                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                502                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                416                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                533                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                685                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                612                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                506                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     68245446000                       # Total gap between requests
+system.physmem.totGap                     68540041000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7288                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7287                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4342                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       590                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       174                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4301                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2168                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       588                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       170                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        60                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,70 +186,74 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          580                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      479.779310                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     274.986956                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     421.744260                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            159     27.41%     27.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          117     20.17%     47.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           45      7.76%     55.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           23      3.97%     59.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           14      2.41%     61.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           13      2.24%     63.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            6      1.03%     65.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      0.34%     65.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          201     34.66%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            580                       # Bytes accessed per row activation
-system.physmem.totQLat                       57907000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 195684500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     36440000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                   101337500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        7945.53                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13904.71                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples         1441                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      322.087439                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     187.561369                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     340.705535                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            517     35.88%     35.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          362     25.12%     61.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          132      9.16%     70.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           71      4.93%     75.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           61      4.23%     79.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           42      2.91%     82.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           35      2.43%     84.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           26      1.80%     86.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          195     13.53%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1441                       # Bytes accessed per row activation
+system.physmem.totQLat                       60227500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 196858750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     36435000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8265.06                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26850.23                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           6.83                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27015.06                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           6.80                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        6.83                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        6.80                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.16                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5839                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5834                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.12                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.06                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9364084.25                       # Average gap between requests
-system.physmem.pageHitRate                      80.12                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               1.16                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      6833684                       # Throughput (bytes/s)
+system.physmem.avgGap                      9405796.76                       # Average gap between requests
+system.physmem.pageHitRate                      80.06                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      64419207500                       # Time in different power states
+system.physmem.memoryStateTime::REF        2288520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1827118750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      6804295                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                4468                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4467                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              2820                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             2820                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14575                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14575                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               4468                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              2819                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             2819                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14578                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14578                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       466368                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size::total              466368                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 466368                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             8915000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             8924000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           67732500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           67911998                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                35342667                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          21189046                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1621967                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18355176                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                16729462                       # Number of BTB hits
+system.cpu.branchPred.lookups                35427097                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          21222481                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1662305                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             19504890                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                16830620                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             91.143021                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6774978                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               8404                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             86.289233                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6785276                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               8391                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -335,239 +339,239 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        136490945                       # number of cpu cycles simulated
+system.cpu.numCycles                        137080484                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           38825213                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      317051968                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    35342667                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           23504440                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      70679896                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6716000                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               21545367                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  106                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1322                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           66                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  37451719                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                502899                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          136134435                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.985255                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.454681                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           39013094                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      318011666                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    35427097                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           23615896                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      70957700                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6891338                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               21536315                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  110                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1697                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           56                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  37608451                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                511125                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          136726497                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.983044                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.454276                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 66077496     48.54%     48.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  6747770      4.96%     53.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  5691244      4.18%     57.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  6070617      4.46%     62.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4899295      3.60%     65.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4080163      3.00%     68.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3177720      2.33%     71.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4131471      3.03%     74.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35258659     25.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 66399200     48.56%     48.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  6788638      4.97%     53.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  5707530      4.17%     57.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6111990      4.47%     62.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4922665      3.60%     65.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4080012      2.98%     68.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3180881      2.33%     71.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4139139      3.03%     74.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 35396442     25.89%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            136134435                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.258938                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.322879                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 45319095                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              16701200                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  66547822                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2552537                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5013781                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              7320658                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 69067                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              400437341                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                211449                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5013781                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 50843684                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 1928767                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         335631                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  63516277                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14496295                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              392925979                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    32                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1658279                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              10203172                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            22306                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           431444746                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2730832248                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1570013245                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         200164445                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            136726497                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.258440                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.319890                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 45526376                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              16684464                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  66829825                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2537018                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                5148814                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              7346336                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 69128                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              401912579                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                214046                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                5148814                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 51079671                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 1913308                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         333807                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  63753347                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14497550                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              394307650                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    25                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1657315                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              10195595                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            22429                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           432708181                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2738145852                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1575813049                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         200323476                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             384566193                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 46878553                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              11940                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          11939                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  36493417                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            103352368                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            91160183                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           4261604                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5303451                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  383671023                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               22900                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 373754233                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1199031                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        33881433                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     97712598                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            780                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     136134435                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.745479                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.022556                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 48141988                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              11963                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          11962                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  36553940                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            103619662                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            91398989                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           4293575                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5309451                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  384641768                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               22898                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 374271543                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1203075                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        34859337                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    100548351                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            778                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     136726497                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.737374                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.024550                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            24740289     18.17%     18.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19905513     14.62%     32.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            20515084     15.07%     47.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18158642     13.34%     61.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            24030824     17.65%     78.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15691878     11.53%     90.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             8802431      6.47%     96.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3372838      2.48%     99.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              916936      0.67%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            25150398     18.39%     18.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19938048     14.58%     32.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            20598425     15.07%     48.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18168946     13.29%     61.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            24025170     17.57%     78.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15741501     11.51%     90.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8821837      6.45%     96.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3366776      2.46%     99.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              915396      0.67%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       136134435                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       136726497                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                    8938      0.05%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   4692      0.03%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd             46049      0.26%      0.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp              3482      0.02%      0.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               434      0.00%      0.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 2      0.00%      0.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           186470      1.05%      1.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult             3938      0.02%      1.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        241178      1.36%      2.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    8454      0.05%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   4686      0.03%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd             46141      0.26%      0.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp              3549      0.02%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               438      0.00%      0.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 3      0.00%      0.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           186673      1.05%      1.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult             3981      0.02%      1.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        241129      1.36%      2.80% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9277159     52.37%     55.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               7942822     44.84%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9262679     52.30%     55.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               7952866     44.90%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             126226981     33.77%     33.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2175715      0.58%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    4      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6775957      1.81%     36.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8464752      2.26%     38.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3426733      0.92%     39.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1595441      0.43%     39.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       20845390      5.58%     45.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7170609      1.92%     47.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7125607      1.91%     49.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt         175287      0.05%     49.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            101514689     27.16%     76.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            88257068     23.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             126495771     33.80%     33.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2175574      0.58%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    1      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6778108      1.81%     36.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8473024      2.26%     38.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3429632      0.92%     39.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1595745      0.43%     39.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20862309      5.57%     45.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7172511      1.92%     47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7129172      1.90%     49.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            101679299     27.17%     76.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            88305111     23.59%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              373754233                       # Type of FU issued
-system.cpu.iq.rate                           2.738308                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    17715164                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.047398                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          653197592                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         287339977                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    249810515                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           249359504                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          130249499                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    118015221                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              262881293                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               128588104                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         11104968                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              374271543                       # Type of FU issued
+system.cpu.iq.rate                           2.730305                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    17710599                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.047320                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          654796096                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         289211293                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    250149926                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           249387161                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          130326745                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    118060008                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              263377407                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               128604735                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         11093990                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      8703620                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       109542                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14223                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      8784600                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      8970914                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       108859                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14127                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      9023406                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       184473                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1790                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       175522                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1863                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5013781                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  291002                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 36408                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           383695470                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            852736                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             103352368                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             91160183                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              11866                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    327                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   282                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14223                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1256888                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       362770                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1619658                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             369836414                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             100211998                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3917819                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                5148814                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  279698                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 35585                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           384666248                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            872586                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             103619662                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             91398989                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              11864                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    344                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   288                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14127                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1301679                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       370144                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1671823                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             370317109                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             100386827                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3954434                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1547                       # number of nop insts executed
-system.cpu.iew.exec_refs                    187429987                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31988466                       # Number of branches executed
-system.cpu.iew.exec_stores                   87217989                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.709604                       # Inst execution rate
-system.cpu.iew.wb_sent                      368475660                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     367825736                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 182824140                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 363330392                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1582                       # number of nop insts executed
+system.cpu.iew.exec_refs                    187618668                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 32015275                       # Number of branches executed
+system.cpu.iew.exec_stores                   87231841                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.701458                       # Inst execution rate
+system.cpu.iew.wb_sent                      368883883                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     368209934                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 183051685                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 363776414                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.694873                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.503190                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.686086                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.503198                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        34630475                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        35601258                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1553283                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    131120654                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.662167                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.659302                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1593594                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    131577683                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.652920                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.658674                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     34358811     26.20%     26.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     28410916     21.67%     47.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13299289     10.14%     58.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11469684      8.75%     66.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     13783827     10.51%     77.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7406623      5.65%     82.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3875247      2.96%     85.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3903446      2.98%     88.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     14612811     11.14%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     34743119     26.41%     26.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     28469178     21.64%     48.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13363377     10.16%     58.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11438386      8.69%     66.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     13773451     10.47%     77.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7412867      5.63%     82.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3865563      2.94%     85.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3891482      2.96%     88.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     14620260     11.11%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    131120654                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    131577683                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            273037337                       # Number of instructions committed
 system.cpu.commit.committedOps              349065061                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -578,230 +582,273 @@ system.cpu.commit.branches                   30563497                       # Nu
 system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 279584611                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              6225112                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              14612811                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        116648967     33.42%     33.42% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2145845      0.61%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     34.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd      6594343      1.89%     35.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     35.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp      7943502      2.28%     38.20% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt      3118180      0.89%     39.09% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv      1563217      0.45%     39.54% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc     19652356      5.63%     45.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult      7136937      2.04%     47.21% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc      7062098      2.02%     49.24% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt       175285      0.05%     49.29% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        94648748     27.11%     76.40% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       82375583     23.60%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total         349065061                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              14620260                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    500200856                       # The number of ROB reads
-system.cpu.rob.rob_writes                   772408679                       # The number of ROB writes
-system.cpu.timesIdled                            6691                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          356510                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    501621219                       # The number of ROB reads
+system.cpu.rob.rob_writes                   774485510                       # The number of ROB writes
+system.cpu.timesIdled                            6746                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          353987                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273036725                       # Number of Instructions Simulated
 system.cpu.committedOps                     349064449                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             273036725                       # Number of Instructions Simulated
-system.cpu.cpi                               0.499900                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.499900                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.000402                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.000402                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1768035388                       # number of integer regfile reads
-system.cpu.int_regfile_writes               232615737                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 188041949                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                132439422                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1200568638                       # number of misc regfile reads
+system.cpu.cpi                               0.502059                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.502059                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.991799                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.991799                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1770130874                       # number of integer regfile reads
+system.cpu.int_regfile_writes               233038396                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 188133896                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                132498519                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1201060026                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                20175639                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          17638                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         17637                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback         1039                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         2838                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         2838                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31713                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10277                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             41990                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1014784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       362112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total        1376896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus           1376896                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy       11796500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                20063659                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          17609                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         17609                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback         1041                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         2837                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         2837                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31648                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10285                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             41933                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1012608                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       362304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total        1374912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus           1374912                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus          256                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy       11785500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      24305488                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      24279239                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       7381711                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       7466709                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             13966                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1849.581585                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            37434387                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             15856                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           2360.897263                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             13936                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1847.607729                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            37591137                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15825                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           2375.427299                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1849.581585                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.903116                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.903116                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1890                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          206                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1847.607729                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.902152                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.902152                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1889                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1531                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.922852                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          74919290                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         74919290                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     37434387                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        37434387                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      37434387                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         37434387                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     37434387                       # number of overall hits
-system.cpu.icache.overall_hits::total        37434387                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        17330                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         17330                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        17330                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          17330                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        17330                       # number of overall misses
-system.cpu.icache.overall_misses::total         17330                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    451723484                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    451723484                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    451723484                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    451723484                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    451723484                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    451723484                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     37451717                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     37451717                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     37451717                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     37451717                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     37451717                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     37451717                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000463                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000463                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000463                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000463                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000463                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000463                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26065.982920                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 26065.982920                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 26065.982920                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 26065.982920                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 26065.982920                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 26065.982920                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1035                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1525                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.922363                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          75232724                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         75232724                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     37591137                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        37591137                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      37591137                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         37591137                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     37591137                       # number of overall hits
+system.cpu.icache.overall_hits::total        37591137                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        17312                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         17312                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        17312                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          17312                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        17312                       # number of overall misses
+system.cpu.icache.overall_misses::total         17312                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    452091985                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    452091985                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    452091985                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    452091985                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    452091985                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    452091985                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     37608449                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     37608449                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     37608449                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     37608449                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     37608449                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     37608449                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000460                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000460                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000460                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000460                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000460                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000460                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26114.370668                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 26114.370668                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26114.370668                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 26114.370668                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26114.370668                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 26114.370668                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          970                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                19                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    39.807692                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    51.052632                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1473                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1473                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1473                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1473                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1473                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1473                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15857                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15857                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15857                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15857                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15857                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15857                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    359348009                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    359348009                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    359348009                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    359348009                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    359348009                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    359348009                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000423                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000423                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000423                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000423                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000423                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000423                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22661.790313                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22661.790313                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22661.790313                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22661.790313                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22661.790313                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22661.790313                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1486                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1486                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1486                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1486                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1486                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1486                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15826                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15826                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15826                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15826                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15826                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15826                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    356931509                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    356931509                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    356931509                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    356931509                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    356931509                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    356931509                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000421                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000421                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000421                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22553.488500                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22553.488500                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22553.488500                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22553.488500                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22553.488500                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22553.488500                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3939.930856                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              13213                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5393                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.450028                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         3938.278477                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              13178                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5394                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.443085                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   375.867414                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2777.143346                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   786.920096                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011471                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084752                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.024015                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.120237                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5393                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1243                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4011                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.164581                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           180351                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          180351                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        12816                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          303                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          13119                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks         1039                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total         1039                       # number of Writeback hits
+system.cpu.l2cache.tags.occ_blocks::writebacks   377.930800                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2772.496816                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   787.850861                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011534                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084610                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.024043                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.120187                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5394                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1247                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4004                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.164612                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           180111                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          180111                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        12781                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          302                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          13083                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks         1041                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total         1041                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           18                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           18                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        12816                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          321                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           13137                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        12816                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          321                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          13137                       # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst        12781                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          320                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           13101                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        12781                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          320                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          13101                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst         3041                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         1478                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4519                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         2820                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2820                       # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         1481                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4522                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         2819                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2819                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         3041                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         4298                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7339                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         4300                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7341                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         3041                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         4298                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7339                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    215304250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    106779500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    322083750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    200114250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    200114250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    215304250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    306893750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    522198000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    215304250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    306893750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    522198000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        15857                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data         1781                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        17638                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks         1039                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total         1039                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         2838                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         2838                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        15857                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4619                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        20476                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        15857                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4619                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        20476                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.191777                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.829871                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.256208                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993658                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.993658                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.191777                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.930504                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.358420                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.191777                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.930504                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.358420                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70800.476817                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72245.940460                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71273.235229                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70962.500000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70962.500000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70800.476817                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71403.850628                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71153.835672                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70800.476817                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71403.850628                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71153.835672                       # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.data         4300                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7341                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    213267000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    109185750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    322452750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    198902000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    198902000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    213267000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    308087750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    521354750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    213267000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    308087750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    521354750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        15822                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data         1783                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        17605                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks         1041                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total         1041                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            2                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            2                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         2837                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         2837                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        15822                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4620                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        20442                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        15822                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4620                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        20442                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.192201                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.830623                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.256859                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993655                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.993655                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192201                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.930736                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.359114                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192201                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.930736                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.359114                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70130.549161                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73724.341661                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71307.551968                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70557.644555                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70557.644555                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70130.549161                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71648.313953                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71019.581801                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70130.549161                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71648.313953                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71019.581801                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -810,178 +857,186 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           39                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           51                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           39                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           51                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           39                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           51                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3029                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1439                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           43                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           54                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           43                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           54                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           43                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           54                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3030                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1438                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total         4468                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2820                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         2820                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3029                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         4259                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7288                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3029                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         4259                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7288                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    176626500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     86490250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    263116750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    165285750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    165285750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    176626500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    251776000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    428402500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    176626500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    251776000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    428402500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191020                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.807973                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253317                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993658                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993658                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191020                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922061                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.355929                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191020                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922061                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.355929                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58311.819082                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60104.412787                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58889.156222                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58611.968085                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58611.968085                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58311.819082                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59116.224466                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58781.901756                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58311.819082                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59116.224466                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58781.901756                       # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2819                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         2819                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3030                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         4257                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7287                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3030                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         4257                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7287                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    174561000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     88459500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    263020500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        20002                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        20002                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    163883500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    163883500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    174561000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    252343000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    426904000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    174561000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    252343000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    426904000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191505                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.806506                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253792                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993655                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993655                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191505                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.921429                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.356472                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191505                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.921429                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.356472                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57610.891089                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61515.646732                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58867.614145                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58135.331678                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58135.331678                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57610.891089                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59277.190510                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58584.328256                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57610.891089                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59277.190510                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58584.328256                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements              1416                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3111.494128                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           170791722                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4619                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          36975.908638                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements              1423                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3106.690369                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           170987022                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4620                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37010.177922                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3111.494128                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.759642                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.759642                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3203                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          686                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2450                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.781982                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         341638239                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        341638239                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     88738255                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        88738255                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82031563                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82031563                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        11009                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        11009                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.occ_blocks::cpu.data  3106.690369                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.758469                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.758469                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3197                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          683                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2448                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.780518                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         342028974                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        342028974                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     88933648                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        88933648                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82031473                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82031473                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        10994                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        10994                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     170769818                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        170769818                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    170769818                       # number of overall hits
-system.cpu.dcache.overall_hits::total       170769818                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         3984                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          3984                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        21102                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        21102                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     170965121                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        170965121                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    170965121                       # number of overall hits
+system.cpu.dcache.overall_hits::total       170965121                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         3973                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          3973                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        21192                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        21192                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data        25086                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          25086                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        25086                       # number of overall misses
-system.cpu.dcache.overall_misses::total         25086                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    232475203                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    232475203                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1255700879                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1255700879                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data        25165                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          25165                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        25165                       # number of overall misses
+system.cpu.dcache.overall_misses::total         25165                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    236002703                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    236002703                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1249306876                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1249306876                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       170250                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       170250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1488176082                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1488176082                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1488176082                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1488176082                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     88742239                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     88742239                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data   1485309579                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1485309579                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1485309579                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1485309579                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     88937621                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     88937621                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11011                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        11011                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10996                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        10996                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    170794904                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    170794904                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    170794904                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    170794904                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    170990286                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    170990286                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    170990286                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    170990286                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000045                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000257                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000257                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000258                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000258                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000182                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000182                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000147                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000147                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000147                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000147                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58352.209588                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 58352.209588                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59506.249597                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59506.249597                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59401.636798                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 59401.636798                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58951.815591                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 58951.815591                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85125                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85125                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59322.972255                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59322.972255                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59322.972255                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59322.972255                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        26768                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1267                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               424                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59022.832466                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59022.832466                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59022.832466                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59022.832466                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        25911                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1248                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               444                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              13                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    63.132075                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    97.461538                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    58.358108                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           96                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks         1039                       # number of writebacks
-system.cpu.dcache.writebacks::total              1039                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2202                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         2202                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18265                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        18265                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks         1041                       # number of writebacks
+system.cpu.dcache.writebacks::total              1041                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2189                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         2189                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18354                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        18354                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        20467                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        20467                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        20467                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        20467                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1782                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1782                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2837                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         2837                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4619                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4619                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    111706789                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    111706789                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    203137000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    203137000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    314843789                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    314843789                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    314843789                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    314843789                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data        20543                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        20543                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        20543                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        20543                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1784                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1784                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2838                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2838                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4622                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4622                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4622                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4622                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    114103043                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    114103043                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    201967248                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    201967248                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    316070291                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    316070291                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    316070291                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    316070291                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -990,14 +1045,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62686.189113                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62686.189113                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71602.749383                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71602.749383                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68162.760121                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68162.760121                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68162.760121                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68162.760121                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63959.104821                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63959.104821                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71165.344609                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71165.344609                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68383.879489                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68383.879489                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68383.879489                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68383.879489                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 74fdba7cd..edb370512 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.212344                       # Nu
 sim_ticks                                212344043000                       # Number of ticks simulated
 final_tick                               212344043000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1312619                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1678120                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1020836459                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 266392                       # Number of bytes of host memory used
-host_seconds                                   208.01                       # Real time elapsed on the host
+host_inst_rate                                1152169                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1472992                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              896053064                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309060                       # Number of bytes of host memory used
+host_seconds                                   236.98                       # Real time elapsed on the host
 sim_insts                                   273037663                       # Number of instructions simulated
 sim_ops                                     349065399                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,5 +147,40 @@ system.cpu.num_busy_cycles                  424688087                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          30563502                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 116649415     33.42%     33.42% # Class of executed instruction
+system.cpu.op_class::IntMult                  2145905      0.61%     34.03% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd             6594343      1.89%     35.92% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     35.92% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp             7943502      2.28%     38.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt             3118180      0.89%     39.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv             1563217      0.45%     39.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc           19652356      5.63%     45.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult            7136937      2.04%     47.21% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc         7062098      2.02%     49.24% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt             175285      0.05%     49.29% # Class of executed instruction
+system.cpu.op_class::MemRead                 94648757     27.11%     76.40% # Class of executed instruction
+system.cpu.op_class::MemWrite                82375599     23.60%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  349065594                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 6cac10996..23ba68f1d 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.525834                       # Nu
 sim_ticks                                525834342000                       # Number of ticks simulated
 final_tick                               525834342000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 485432                       # Simulator instruction rate (inst/s)
-host_op_rate                                   620607                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              935900071                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 332908                       # Number of bytes of host memory used
-host_seconds                                   561.85                       # Real time elapsed on the host
+host_inst_rate                                 605985                       # Simulator instruction rate (inst/s)
+host_op_rate                                   774729                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1168322503                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318808                       # Number of bytes of host memory used
+host_seconds                                   450.08                       # Real time elapsed on the host
 sim_insts                                   272739283                       # Number of instructions simulated
 sim_ops                                     348687122                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -153,6 +153,41 @@ system.cpu.num_busy_cycles                 1051668684                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          30563501                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 116649413     33.42%     33.42% # Class of executed instruction
+system.cpu.op_class::IntMult                  2145905      0.61%     34.03% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     34.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd             6594343      1.89%     35.92% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     35.92% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp             7943502      2.28%     38.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt             3118180      0.89%     39.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv             1563217      0.45%     39.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc           19652356      5.63%     45.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult            7136937      2.04%     47.21% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc         7062098      2.02%     49.24% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt             175285      0.05%     49.29% # Class of executed instruction
+system.cpu.op_class::MemRead                 94648757     27.11%     76.40% # Class of executed instruction
+system.cpu.op_class::MemWrite                82375599     23.60%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  349065592                       # Class of executed instruction
 system.cpu.icache.tags.replacements             13796                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1765.993223                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           348644747                       # Total number of references to valid blocks.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 55140cd28..139fd1f12 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.629599                       # Number of seconds simulated
-sim_ticks                                629599373500                       # Number of ticks simulated
-final_tick                               629599373500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.629061                       # Number of seconds simulated
+sim_ticks                                629060517500                       # Number of ticks simulated
+final_tick                               629060517500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 142688                       # Simulator instruction rate (inst/s)
-host_op_rate                                   142688                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               49278187                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277460                       # Number of bytes of host memory used
-host_seconds                                 12776.43                       # Real time elapsed on the host
+host_inst_rate                                 141618                       # Simulator instruction rate (inst/s)
+host_op_rate                                   141618                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48866772                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278492                       # Number of bytes of host memory used
+host_seconds                                 12872.97                       # Real time elapsed on the host
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            176768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          30295936                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30472704                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       176768                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          176768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            177024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          30295744                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             30472768                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       177024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          177024                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4282112                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4282112                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2762                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             473374                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                476136                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2766                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             473371                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                476137                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66908                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66908                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               280763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             48119387                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                48400150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          280763                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             280763                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           6801328                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6801328                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           6801328                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              280763                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            48119387                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               55201478                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        476136                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               281410                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             48160301                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                48441711                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          281410                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             281410                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           6807154                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                6807154                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           6807154                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              281410                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            48160301                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               55248866                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        476137                       # Number of read requests accepted
 system.physmem.writeReqs                        66908                       # Number of write requests accepted
-system.physmem.readBursts                      476136                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      476137                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66908                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 30452800                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19904                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4280256                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  30472704                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 30454016                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     18752                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4280576                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  30472768                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4282112                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      311                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      293                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               29443                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               29448                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               29785                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29834                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29781                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               29679                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29744                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               29853                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               29847                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               29759                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29871                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              29836                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29910                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              29783                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              29571                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              29499                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              29630                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               29839                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               29775                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               29682                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               29757                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               29851                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               29843                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               29760                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               29872                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              29842                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              29921                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              29772                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              29569                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              29495                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              29633                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::6                4262                       # Pe
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4334                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4219                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4224                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    629599315500                       # Total gap between requests
+system.physmem.totGap                    629060434500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  476136                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  476137                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,11 +97,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66908                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    405282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     66881                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      3493                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       148                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        19                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    408337                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     66853                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       494                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       143                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      959                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4042                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4086                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      986                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4093                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4047                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
@@ -193,111 +193,111 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        21634                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      530.927244                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     283.070424                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     451.227629                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7470     34.53%     34.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         2793     12.91%     47.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          292      1.35%     48.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          662      3.06%     51.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          618      2.86%     54.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          184      0.85%     55.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          105      0.49%     56.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           67      0.31%     56.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9443     43.65%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          21634                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4040                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       114.953218                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.941709                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     1121.982719                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           4021     99.53%     99.53% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-12287            1      0.02%     99.55% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335            6      0.15%     99.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383           11      0.27%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       186678                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      186.061046                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.793811                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     215.276022                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          65820     35.26%     35.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        88170     47.23%     82.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        20719     11.10%     93.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          470      0.25%     93.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          393      0.21%     94.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          522      0.28%     94.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          523      0.28%     94.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          573      0.31%     94.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9488      5.08%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         186678                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4045                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       115.896168                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.909110                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     1130.293958                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           4026     99.53%     99.53% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335            6      0.15%     99.68% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383           12      0.30%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4040                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4040                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.554208                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.524474                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.020237                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3080     76.24%     76.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                645     15.97%     92.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                312      7.72%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  2      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4040                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3865744500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15098494500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2379125000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  8853625000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8124.30                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    18606.89                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            4045                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4045                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.534981                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.512135                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.885131                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2961     73.20%     73.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  5      0.12%     73.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1078     26.65%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4045                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5368112500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               14290187500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2379220000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11281.24                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31731.19                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          48.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30031.24                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          48.41                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           6.80                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       48.40                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        6.80                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       48.44                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        6.81                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.48                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     304858                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50638                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   64.07                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.68                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1159389.14                       # Average gap between requests
-system.physmem.pageHitRate                      65.50                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              25.10                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     55201376                       # Throughput (bytes/s)
+system.physmem.avgWrQLen                        24.35                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     305539                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50504                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   64.21                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.48                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1158394.67                       # Average gap between requests
+system.physmem.pageHitRate                      65.60                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     166526885000                       # Time in different power states
+system.physmem.memoryStateTime::REF       21005660000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      441526652500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     55248866                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq              409283                       # Transaction distribution
-system.membus.trans_dist::ReadResp             409282                       # Transaction distribution
+system.membus.trans_dist::ReadResp             409283                       # Transaction distribution
 system.membus.trans_dist::Writeback             66908                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66853                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66853                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019179                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1019179                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34754752                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34754752                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               34754752                       # Total data (bytes)
+system.membus.trans_dist::ReadExReq             66854                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66854                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019182                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1019182                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34754880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            34754880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               34754880                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1216217500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1216375500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4476344750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4475214250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               388794194                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         256437181                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          25515612                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            316966671                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               257889505                       # Number of BTB hits
+system.cpu.branchPred.lookups               388838415                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         256496026                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          25500542                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            313163608                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               257889708                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             81.361710                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                56977055                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               6765                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             82.349833                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                56962894                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               6655                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    520530320                       # DTB read hits
-system.cpu.dtb.read_misses                     596868                       # DTB read misses
+system.cpu.dtb.read_hits                    520477201                       # DTB read hits
+system.cpu.dtb.read_misses                     601468                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                521127188                       # DTB read accesses
-system.cpu.dtb.write_hits                   282735636                       # DTB write hits
-system.cpu.dtb.write_misses                     50248                       # DTB write misses
+system.cpu.dtb.read_accesses                521078669                       # DTB read accesses
+system.cpu.dtb.write_hits                   282725842                       # DTB write hits
+system.cpu.dtb.write_misses                     50160                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               282785884                       # DTB write accesses
-system.cpu.dtb.data_hits                    803265956                       # DTB hits
-system.cpu.dtb.data_misses                     647116                       # DTB misses
+system.cpu.dtb.write_accesses               282776002                       # DTB write accesses
+system.cpu.dtb.data_hits                    803203043                       # DTB hits
+system.cpu.dtb.data_misses                     651628                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                803913072                       # DTB accesses
-system.cpu.itb.fetch_hits                   392575649                       # ITB hits
-system.cpu.itb.fetch_misses                       637                       # ITB misses
+system.cpu.dtb.data_accesses                803854671                       # DTB accesses
+system.cpu.itb.fetch_hits                   392472204                       # ITB hits
+system.cpu.itb.fetch_misses                       553                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               392576286                       # ITB accesses
+system.cpu.itb.fetch_accesses               392472757                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -311,98 +311,98 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       1259198748                       # number of cpu cycles simulated
+system.cpu.numCycles                       1258121036                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          407695740                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3264617465                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   388794194                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          314866560                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     628012855                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               156754099                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               76226521                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  146                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          6801                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           25                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 392575649                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes              11023705                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1242691149                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.627055                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.139887                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          407549546                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3264335293                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   388838415                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          314852602                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     627934120                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               156719825                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               76880186                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  142                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          6672                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           36                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 392472204                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              11052250                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1243100397                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.625963                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.139695                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                614678294     49.46%     49.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 57194010      4.60%     54.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 43037577      3.46%     57.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 71548664      5.76%     63.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                128942698     10.38%     73.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 45555972      3.67%     77.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 41222741      3.32%     80.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  8274333      0.67%     81.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                232236860     18.69%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                615166277     49.49%     49.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 57172656      4.60%     54.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 43000211      3.46%     57.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 71551989      5.76%     63.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                128968214     10.37%     73.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 45505183      3.66%     77.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 41223100      3.32%     80.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  8333259      0.67%     81.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                232179508     18.68%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1242691149                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.308763                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.592615                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                436055809                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              62292865                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 604244409                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9361042                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              130737024                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             31725769                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12419                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3186787270                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 46304                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              130737024                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                465340122                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                27154826                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          26997                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 583972819                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              35459361                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3088232608                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   174                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  15483                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              29158265                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2049406757                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3572462908                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3487065334                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          85397573                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1243100397                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.309063                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.594611                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                435930978                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              62933874                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 604150213                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9367719                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              130717613                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             31718395                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12462                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3186570357                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 46425                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              130717613                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                465229496                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                27790939                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          27122                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 583871323                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              35463904                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3087907389                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   154                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  15123                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              29163905                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2049179896                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3572157572                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3486780085                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          85377486                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                664437687                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4235                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             98                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 110031896                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            740965992                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           350476523                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          68460641                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8808840                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2617422170                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  92                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2156741664                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          17943359                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       794308745                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    722892982                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             53                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1242691149                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.735541                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.803084                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                664210826                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4225                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             87                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 110011827                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            740901505                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           350460770                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          68439311                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8785014                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2617226795                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  84                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2156646647                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          17944068                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       794119367                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    722832560                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             45                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1243100397                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.734893                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.803138                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           447799861     36.03%     36.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           195733301     15.75%     51.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           250780419     20.18%     71.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           120973704      9.73%     81.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           105324665      8.48%     90.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            78133504      6.29%     96.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            24822476      2.00%     98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            17360375      1.40%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1762844      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           448302243     36.06%     36.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           195655717     15.74%     51.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           250740933     20.17%     71.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           121021830      9.74%     81.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           105318972      8.47%     90.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            78084268      6.28%     96.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            24856581      2.00%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            17351964      1.40%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1767889      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1242691149                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1243100397                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1146236      3.14%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1146209      3.14%      3.14% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      3.14% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.14% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.14% # attempts to use FU when none available
@@ -431,16 +431,16 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.14% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.14% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.14% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               25360136     69.42%     72.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              10022546     27.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               25356136     69.42%     72.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              10022815     27.44%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1232941102     57.17%     57.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                17091      0.00%     57.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1232880422     57.17%     57.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                17089      0.00%     57.17% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            27851332      1.29%     58.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             8254696      0.38%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            27851287      1.29%     58.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             8254693      0.38%     58.84% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt             7204650      0.33%     59.18% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.18% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.18% # Type of FU issued
@@ -465,84 +465,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.18% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.18% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.18% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            587650943     27.25%     86.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           292819094     13.58%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            587626615     27.25%     86.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           292809135     13.58%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2156741664                       # Type of FU issued
-system.cpu.iq.rate                           1.712789                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    36528918                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.016937                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5459545573                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3323652243                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1987168817                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           151101181                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           88152162                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     73609871                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2115818130                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                77449700                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         62140575                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2156646647                       # Type of FU issued
+system.cpu.iq.rate                           1.714181                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36525160                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016936                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5459761542                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3323347360                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1987047608                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           151101377                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           88072510                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     73609915                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2115719202                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                77449853                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         62169429                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    229895966                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        17367                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        75928                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    139681627                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    229831479                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        44309                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        76170                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    139665874                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         4415                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          2851                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         4419                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          2971                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              130737024                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                13158740                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                531547                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2980853453                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            734148                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             740965992                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            350476523                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 92                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 133073                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  1496                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          75928                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       25509079                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        28871                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             25537950                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2062960594                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             521127327                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          93781070                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              130717613                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                13757635                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                540247                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2980698105                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            730543                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             740901505                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            350460770                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 84                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 137779                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  1477                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          76170                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       25493824                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        28812                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             25522636                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2062857125                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             521078821                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          93789522                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     363431191                       # number of nop insts executed
-system.cpu.iew.exec_refs                    803913709                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                277349504                       # Number of branches executed
-system.cpu.iew.exec_stores                  282786382                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.638312                       # Inst execution rate
-system.cpu.iew.wb_sent                     2062843616                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2060778688                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1180081311                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1751769057                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     363471226                       # number of nop insts executed
+system.cpu.iew.exec_refs                    803855281                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                277329051                       # Number of branches executed
+system.cpu.iew.exec_stores                  282776460                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.639633                       # Inst execution rate
+system.cpu.iew.wb_sent                     2062712429                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2060657523                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1180065693                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1751826527                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.636579                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.673651                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.637885                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.673620                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       954910834                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       954754652                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          25503576                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1111954125                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.806718                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.513025                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          25488461                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1112382784                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.806022                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.513006                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    493953799     44.42%     44.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    227598258     20.47%     64.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    120157352     10.81%     75.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     59117436      5.32%     81.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     49692095      4.47%     85.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     24169379      2.17%     87.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     18838880      1.69%     89.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     16341629      1.47%     90.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    102085297      9.18%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    494456583     44.45%     44.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    227533438     20.45%     64.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    120160218     10.80%     75.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     59129443      5.32%     81.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     49651229      4.46%     85.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     24161906      2.17%     87.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     18831378      1.69%     89.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     16326025      1.47%     90.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    102132564      9.18%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1111954125                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1112382784                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           2008987604                       # Number of instructions committed
 system.cpu.commit.committedOps             2008987604                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -553,229 +553,264 @@ system.cpu.commit.branches                  266706457                       # Nu
 system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events             102085297                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass    185946986      9.26%      9.26% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu       1058512436     52.69%     61.94% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           15158      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd       27517120      1.37%     63.32% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp        8254514      0.41%     63.73% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt        6876464      0.34%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             4      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.07% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       511070026     25.44%     89.51% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      210794896     10.49%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total        2008987604                       # Class of committed instruction
+system.cpu.commit.bw_lim_events             102132564                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3968130856                       # The number of ROB reads
-system.cpu.rob.rob_writes                  6058536012                       # The number of ROB writes
-system.cpu.timesIdled                          350219                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        16507599                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3968356066                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6058204314                       # The number of ROB writes
+system.cpu.timesIdled                          347595                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        15020639                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
 system.cpu.committedOps                    1823043370                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
-system.cpu.cpi                               0.690712                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.690712                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.447780                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.447780                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2624503768                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1494046892                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  78811207                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 52661075                       # number of floating regfile writes
+system.cpu.cpi                               0.690121                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.690121                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.449021                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.449021                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2624396322                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1493942666                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  78811215                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 52660991                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               166495312                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1470280                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1470279                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        95977                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        71640                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        71640                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20109                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3159707                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3179816                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       643456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104181888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.throughput               166637932                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1470284                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1470283                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        95971                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        71642                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        71642                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20095                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3159727                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3179822                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       643008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104182336                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size::total      104825344                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus         104825344                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      914925500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      914919500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      15572000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      15573249                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2358250250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2360853250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              8345                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1652.999012                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           392562699                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             10054                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          39045.424607                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              8332                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1660.987430                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           392459292                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             10047                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          39062.336220                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1652.999012                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.807128                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.807128                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1709                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1660.987430                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.811029                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.811029                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1715                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1553                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.834473                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         785161352                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        785161352                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    392562699                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       392562699                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     392562699                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        392562699                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    392562699                       # number of overall hits
-system.cpu.icache.overall_hits::total       392562699                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12950                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12950                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12950                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12950                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12950                       # number of overall misses
-system.cpu.icache.overall_misses::total         12950                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    384762999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    384762999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    384762999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    384762999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    384762999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    384762999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    392575649                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    392575649                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    392575649                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    392575649                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    392575649                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    392575649                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1559                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.837402                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         784954455                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        784954455                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    392459292                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       392459292                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     392459292                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        392459292                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    392459292                       # number of overall hits
+system.cpu.icache.overall_hits::total       392459292                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12912                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12912                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12912                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12912                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12912                       # number of overall misses
+system.cpu.icache.overall_misses::total         12912                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    385616248                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    385616248                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    385616248                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    385616248                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    385616248                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    385616248                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    392472204                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    392472204                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    392472204                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    392472204                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    392472204                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    392472204                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000033                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000033                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000033                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000033                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000033                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000033                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29711.428494                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29711.428494                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29711.428494                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29711.428494                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29711.428494                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29711.428494                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          621                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    47.769231                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29864.951053                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 29864.951053                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 29864.951053                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 29864.951053                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 29864.951053                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 29864.951053                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          750                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          129                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                16                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    46.875000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          129                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2895                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2895                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2895                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2895                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2895                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2895                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10055                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        10055                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        10055                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        10055                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        10055                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        10055                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    283775749                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    283775749                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    283775749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    283775749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    283775749                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    283775749                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2864                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2864                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2864                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2864                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2864                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2864                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10048                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        10048                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        10048                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        10048                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        10048                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        10048                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281334000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    281334000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281334000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    281334000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281334000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    281334000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000026                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28222.351964                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28222.351964                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28222.351964                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28222.351964                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28222.351964                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28222.351964                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27999.004777                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27999.004777                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27999.004777                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 27999.004777                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27999.004777                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 27999.004777                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           443357                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32688.486835                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1090024                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           476094                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.289514                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           443359                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32688.762679                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1090020                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           476096                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.289496                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1336.366869                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    35.201228                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31316.918737                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.040783                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  1338.461138                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    35.181240                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31315.120300                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.040847                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001074                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.955717                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997573                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.955662                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997582                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32737                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          198                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          505                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5022                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26849                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5028                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26846                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999054                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13650910                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13650910                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         7293                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1053704                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1060997                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        95977                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        95977                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         4787                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4787                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         7293                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1058491                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1065784                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         7293                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1058491                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1065784                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2762                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       406521                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       409283                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        66853                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66853                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2762                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       473374                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        476136                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2762                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       473374                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       476136                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    200785000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  29850948750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  30051733750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5675940500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5675940500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    200785000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  35526889250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  35727674250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    200785000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  35526889250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  35727674250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        10055                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1460225                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1470280                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks        95977                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        95977                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        71640                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        71640                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        10055                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1531865                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1541920                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        10055                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1531865                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1541920                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.274689                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.278396                       # miss rate for ReadReq accesses
+system.cpu.l2cache.tags.tag_accesses         13650914                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13650914                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         7281                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1053719                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1061000                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        95971                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        95971                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4788                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         4788                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         7281                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1058507                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1065788                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         7281                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1058507                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1065788                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2767                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       406517                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       409284                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66854                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66854                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2767                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       473371                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        476138                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2767                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       473371                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       476138                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    198468500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  29469883250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  29668351750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5231809500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5231809500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    198468500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  34701692750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  34900161250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    198468500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  34701692750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  34900161250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        10048                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1460236                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1470284                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        95971                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        95971                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        71642                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        71642                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        10048                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1531878                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1541926                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        10048                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1531878                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1541926                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.275378                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.278391                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.278371                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.933180                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.933180                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.274689                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.309018                       # miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.933168                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.933168                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.275378                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.309014                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.308794                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.274689                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.309018                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.275378                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.309014                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.308794                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72695.510500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73430.274820                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73425.316346                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84901.806950                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84901.806950                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72695.510500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75050.360286                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75036.700123                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72695.510500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75050.360286                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75036.700123                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71726.960607                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72493.606048                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72488.423075                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78257.239657                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78257.239657                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71726.960607                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73307.601754                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73298.416110                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71726.960607                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73307.601754                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73298.416110                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -786,165 +821,165 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66908                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66908                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2762                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406521                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       409283                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66853                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66853                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2762                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       473374                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       476136                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2762                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       473374                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       476136                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    165956500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  24727472750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24893429250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4868551500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4868551500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    165956500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  29596024250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  29761980750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    165956500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  29596024250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  29761980750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.274689                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278396                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2767                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406517                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       409284                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66854                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66854                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2767                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       473371                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       476138                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2767                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       473371                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       476138                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    163545500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  24343035750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24506581250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4426416000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4426416000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    163545500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  28769451750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  28932997250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    163545500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  28769451750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  28932997250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.275378                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278391                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.278371                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.933180                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.933180                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.274689                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.309018                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.933168                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.933168                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.275378                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.309014                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.308794                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.274689                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.309018                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.275378                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.309014                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.308794                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60085.626358                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.048910                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60822.045504                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72824.727387                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72824.727387                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60085.626358                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62521.440235                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62507.310411                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60085.626358                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62521.440235                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62507.310411                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59105.710155                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59881.962501                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.714580                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66210.189368                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66210.189368                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59105.710155                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60775.695490                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60765.990637                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59105.710155                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60775.695490                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60765.990637                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1527769                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.584887                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           666211737                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1531865                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            434.902382                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         409920250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4094.584887                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999655                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999655                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1527782                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4094.589786                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           666108987                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1531878                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            434.831616                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         407842250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4094.589786                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999656                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999656                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          967                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2365                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          390                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          289                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          968                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2366                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          388                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1339886951                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1339886951                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    456456827                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       456456827                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    209754882                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      209754882                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           28                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           28                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     666211709                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        666211709                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    666211709                       # number of overall hits
-system.cpu.dcache.overall_hits::total       666211709                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1925791                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1925791                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1040014                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1040014                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses        1339722798                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1339722798                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    456374888                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       456374888                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    209734080                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      209734080                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           19                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           19                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     666108968                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        666108968                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    666108968                       # number of overall hits
+system.cpu.dcache.overall_hits::total       666108968                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1925656                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1925656                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1060816                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1060816                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2965805                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2965805                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2965805                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2965805                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  77884724250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  77884724250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  53548786128                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  53548786128                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        73000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        73000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 131433510378                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 131433510378                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 131433510378                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 131433510378                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    458382618                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    458382618                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      2986472                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2986472                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2986472                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2986472                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  77376197750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  77376197750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  46509308117                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  46509308117                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        74750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        74750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 123885505867                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 123885505867                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 123885505867                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 123885505867                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    458300544                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    458300544                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           29                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           29                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    669177514                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    669177514                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    669177514                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    669177514                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004201                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004201                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.004934                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.004934                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.034483                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.034483                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.004432                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.004432                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.004432                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.004432                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40442.978625                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40442.978625                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51488.524316                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 51488.524316                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        73000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        73000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 44316.302110                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 44316.302110                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 44316.302110                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 44316.302110                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        18203                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          134                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               374                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           20                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           20                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    669095440                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    669095440                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    669095440                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    669095440                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004202                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004202                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005032                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.005032                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.050000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.050000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.004463                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.004463                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.004463                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.004463                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40181.734302                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40181.734302                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43842.954968                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43842.954968                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        74750                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        74750                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41482.225806                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41482.225806                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41482.225806                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41482.225806                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        18571                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          133                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               384                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    48.671123                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          134                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    48.361979                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          133                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        95977                       # number of writebacks
-system.cpu.dcache.writebacks::total             95977                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       465566                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       465566                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       968374                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       968374                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        95971                       # number of writebacks
+system.cpu.dcache.writebacks::total             95971                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       465420                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       465420                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       989174                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       989174                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1433940                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1433940                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1433940                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1433940                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460225                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1460225                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71640                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        71640                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1531865                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1531865                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1531865                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1531865                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  41848820250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  41848820250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5798224000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5798224000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47647044250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  47647044250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47647044250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  47647044250                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data      1454594                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1454594                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1454594                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1454594                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460236                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1460236                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71642                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        71642                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1531878                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1531878                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1531878                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1531878                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  41467915750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  41467915750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5351919500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5351919500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46819835250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  46819835250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46819835250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  46819835250                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003186                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003186                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000340                       # mshr miss rate for WriteReq accesses
@@ -953,14 +988,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002289
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002289                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002289                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002289                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28659.158863                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28659.158863                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80935.566723                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80935.566723                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31103.944701                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 31103.944701                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31103.944701                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 31103.944701                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28398.091644                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28398.091644                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74703.658468                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74703.658468                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30563.684086                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30563.684086                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30563.684086                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30563.684086                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index 75c422cba..6bfc9d3ce 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.004711                       # Nu
 sim_ticks                                1004710587000                       # Number of ticks simulated
 final_tick                               1004710587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1945820                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1945820                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              973120006                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280320                       # Number of bytes of host memory used
-host_seconds                                  1032.46                       # Real time elapsed on the host
+host_inst_rate                                2670371                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2670371                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1335473702                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265688                       # Number of bytes of host memory used
+host_seconds                                   752.33                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -95,5 +95,40 @@ system.cpu.num_busy_cycles                 2009421175                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         266706457                       # Number of branches fetched
+system.cpu.op_class::No_OpClass             185946986      9.25%      9.25% # Class of executed instruction
+system.cpu.op_class::IntAlu                1058512437     52.68%     61.93% # Class of executed instruction
+system.cpu.op_class::IntMult                    15158      0.00%     61.93% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     61.93% # Class of executed instruction
+system.cpu.op_class::FloatAdd                27517120      1.37%     63.30% # Class of executed instruction
+system.cpu.op_class::FloatCmp                 8254514      0.41%     63.71% # Class of executed instruction
+system.cpu.op_class::FloatCvt                 6876464      0.34%     64.05% # Class of executed instruction
+system.cpu.op_class::FloatMult                      4      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::MemRead                511488910     25.45%     89.51% # Class of executed instruction
+system.cpu.op_class::MemWrite               210809477     10.49%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 2009421070                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 96fb665fa..ef8e8a3ca 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.769740                       # Nu
 sim_ticks                                2769739533000                       # Number of ticks simulated
 final_tick                               2769739533000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1066482                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1066482                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1470331870                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 289152                       # Number of bytes of host memory used
-host_seconds                                  1883.75                       # Real time elapsed on the host
+host_inst_rate                                1094265                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1094265                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1508635104                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 274392                       # Number of bytes of host memory used
+host_seconds                                  1835.92                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -109,6 +109,41 @@ system.cpu.num_busy_cycles                 5539479066                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         266706457                       # Number of branches fetched
+system.cpu.op_class::No_OpClass             185946986      9.25%      9.25% # Class of executed instruction
+system.cpu.op_class::IntAlu                1058512437     52.68%     61.93% # Class of executed instruction
+system.cpu.op_class::IntMult                    15158      0.00%     61.93% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     61.93% # Class of executed instruction
+system.cpu.op_class::FloatAdd                27517120      1.37%     63.30% # Class of executed instruction
+system.cpu.op_class::FloatCmp                 8254514      0.41%     63.71% # Class of executed instruction
+system.cpu.op_class::FloatCvt                 6876464      0.34%     64.05% # Class of executed instruction
+system.cpu.op_class::FloatMult                      4      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.05% # Class of executed instruction
+system.cpu.op_class::MemRead                511488910     25.45%     89.51% # Class of executed instruction
+system.cpu.op_class::MemWrite               210809477     10.49%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 2009421070                       # Class of executed instruction
 system.cpu.icache.tags.replacements              9046                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1478.418050                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          2009410475                       # Total number of references to valid blocks.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 067d517cb..23a63d881 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.629657                       # Number of seconds simulated
-sim_ticks                                629657386500                       # Number of ticks simulated
-final_tick                               629657386500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.628792                       # Number of seconds simulated
+sim_ticks                                628791732500                       # Number of ticks simulated
+final_tick                               628791732500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  85982                       # Simulator instruction rate (inst/s)
-host_op_rate                                   117096                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               39107572                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 322024                       # Number of bytes of host memory used
-host_seconds                                 16100.65                       # Real time elapsed on the host
+host_inst_rate                                  86286                       # Simulator instruction rate (inst/s)
+host_op_rate                                   117510                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               39191918                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321468                       # Number of bytes of host memory used
+host_seconds                                 16043.91                       # Real time elapsed on the host
 sim_insts                                  1384370590                       # Number of instructions simulated
 sim_ops                                    1885325342                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            155392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          30242880                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30398272                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       155392                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          155392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            154944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          30242560                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             30397504                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       154944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          154944                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2428                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             472545                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                474973                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2421                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             472540                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                474961                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               246788                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             48030692                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                48277480                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          246788                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             246788                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           6718371                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6718371                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           6718371                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              246788                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            48030692                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54995851                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        474973                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               246415                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             48096307                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                48342722                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          246415                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             246415                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           6727620                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                6727620                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           6727620                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              246415                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            48096307                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               55070342                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        474962                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      474973                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      474962                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 30370688                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     27584                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228672                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  30398272                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 30374848                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     22720                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4229184                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  30397568                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      431                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      355                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4296                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               29858                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29659                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29728                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29690                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           4292                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               29853                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               29663                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               29734                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               29691                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               29781                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29808                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               29619                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               29428                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               29461                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29473                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              29524                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29641                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              29683                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              29785                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              29611                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              29793                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4100                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               29812                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               29626                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               29426                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               29463                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               29476                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              29540                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              29638                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              29686                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              29802                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              29621                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              29795                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4173                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4102                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4223                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4171                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4093                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4140                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4139                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    629657309500                       # Total gap between requests
+system.physmem.totGap                    628791712500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  474973                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  474962                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,13 +97,13 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    407581                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     66607                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       273                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        18                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    407661                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     66594                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -144,30 +144,30 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      941                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      941                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      965                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     3998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4000                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3990                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4016                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4011                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
@@ -193,93 +193,93 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        28167                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      403.324742                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     187.656646                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     439.024801                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14746     52.35%     52.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         2789      9.90%     62.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          571      2.03%     64.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          164      0.58%     64.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           93      0.33%     65.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          524      1.86%     67.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          314      1.11%     68.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           86      0.31%     68.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8880     31.53%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          28167                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3992                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.707415                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.187766                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      506.851977                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           3989     99.92%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.03%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::31744-32767            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3992                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3992                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.551353                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.521439                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.024563                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3052     76.45%     76.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                627     15.71%     92.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                310      7.77%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  1      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  1      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3992                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3604221250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15074013750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2372710000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  9097082500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        7595.16                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    19170.24                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples       194074                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      178.290755                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     128.832062                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     207.398992                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          73771     38.01%     38.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        88634     45.67%     83.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        20233     10.43%     94.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          463      0.24%     94.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          411      0.21%     94.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          515      0.27%     94.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          585      0.30%     95.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          564      0.29%     95.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8898      4.58%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         194074                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4007                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.655603                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.114528                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      505.912792                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4004     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4007                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4007                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.491390                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.469672                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.863565                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3025     75.49%     75.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  1      0.02%     75.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                975     24.33%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  6      0.15%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4007                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5771153000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               14670034250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2373035000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12159.86                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31765.39                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          48.23                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           6.72                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       48.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        6.72                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30909.86                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          48.31                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           6.73                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       48.34                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        6.73                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.85                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     295971                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     49954                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   62.37                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.58                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1163724.00                       # Average gap between requests
-system.physmem.pageHitRate                      63.98                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              24.27                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     54995851                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              408896                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408896                       # Transaction distribution
+system.physmem.avgWrQLen                        18.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     296657                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     49944                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   62.51                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.56                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1162147.84                       # Average gap between requests
+system.physmem.pageHitRate                      64.10                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     162139876750                       # Time in different power states
+system.physmem.memoryStateTime::REF       20996560000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      445650242000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     55070241                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              408884                       # Transaction distribution
+system.membus.trans_dist::ReadResp             408882                       # Transaction distribution
 system.membus.trans_dist::Writeback             66098                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4296                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4296                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66077                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66077                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1024636                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1024636                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34628544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34628544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               34628544                       # Total data (bytes)
+system.membus.trans_dist::UpgradeReq             4292                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4292                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66078                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66078                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1024604                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1024604                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34627712                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            34627712                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               34627712                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1215525500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1214449500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4444359954                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4441072458                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               438199522                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         350949441                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          30620410                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            248742563                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               229772650                       # Number of BTB hits
+system.cpu.branchPred.lookups               439434227                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         352242826                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          30627071                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            250632586                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               230940186                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.373676                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                52962534                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2805242                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.142921                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                52229993                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2805540                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -365,99 +365,99 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       1259314774                       # number of cpu cycles simulated
+system.cpu.numCycles                       1257583466                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          354212583                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2278943291                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   438199522                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          282735184                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     601285341                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               157201665                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              134990206                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  592                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         11080                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          114                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 334803997                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes              11648696                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1217029612                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.574413                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.174582                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          355252330                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2281557009                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   439434227                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          283170179                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     601713503                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               156847289                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              133155767                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  595                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         11076                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          125                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 335955320                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              11758504                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1216301526                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.576674                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.174492                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                615789102     50.60%     50.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42212896      3.47%     54.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 95956201      7.88%     61.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 57716133      4.74%     66.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 72254915      5.94%     72.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 44707595      3.67%     76.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 31168110      2.56%     78.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 31500430      2.59%     81.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                225724230     18.55%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                614632846     50.53%     50.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 42470987      3.49%     54.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 96126752      7.90%     61.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 57281313      4.71%     66.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 72527941      5.96%     72.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 45003441      3.70%     76.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 31089370      2.56%     78.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 31572340      2.60%     81.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                225596536     18.55%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1217029612                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.347967                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.809669                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                405265267                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             107157501                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 560735859                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              17352207                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              126518778                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             44627065                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 11198                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3022541715                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 25538                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              126518778                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                441244328                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                38456610                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         454301                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 539911121                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              70444474                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2941731616                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    86                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                4811465                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              54362751                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              733                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2929353177                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           14237214542                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups      12151315514                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          83979009                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1216301526                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.349427                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.814239                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                405937331                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             105620938                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 561845304                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              16741500                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              126156453                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             44653834                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11972                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3026383079                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 27573                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              126156453                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                441649817                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                37679339                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         449718                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 540872152                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              69494047                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2944559238                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    81                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                4802711                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              54195204                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              788                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2928884357                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           14250328437                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      12163279231                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          83987601                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1993140090                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                936213087                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              20203                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          17724                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 179723252                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            971631963                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           486198822                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          36723664                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         38677099                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2793016392                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               27622                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2435260833                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          13305109                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       895166670                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   2343525890                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           6238                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1217029612                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.000987                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.873461                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                935744267                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              20476                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          17997                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 177752072                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            970380112                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           488270478                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          36212412                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         40741930                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2792865970                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               27850                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2433397099                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          13404605                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       895018158                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   2348989049                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           6466                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1216301526                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.000653                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.872636                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           381057421     31.31%     31.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           183026992     15.04%     46.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           204041316     16.77%     63.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           169676462     13.94%     77.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           132865899     10.92%     87.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            92968001      7.64%     95.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            37978061      3.12%     98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            12373824      1.02%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             3041636      0.25%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           380324245     31.27%     31.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           183454055     15.08%     46.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           204117167     16.78%     63.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           169768830     13.96%     77.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           132683622     10.91%     88.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            92575300      7.61%     95.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            37909888      3.12%     98.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            12415448      1.02%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             3052971      0.25%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1217029612                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1216301526                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  714935      0.82%      0.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  714605      0.81%      0.81% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                  24383      0.03%      0.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.84% # attempts to use FU when none available
@@ -486,118 +486,118 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.84% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               55166828     62.92%     63.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              31766374     36.23%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               55145870     62.89%     63.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              31799244     36.27%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1104417509     45.35%     45.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult             11223990      0.46%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     45.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         6876473      0.28%     46.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         5501794      0.23%     46.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     46.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       23394204      0.96%     47.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            839996872     34.49%     81.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           442474698     18.17%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1104322039     45.38%     45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult             11223967      0.46%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     45.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         6876477      0.28%     46.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         5502004      0.23%     46.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       23392771      0.96%     47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            838298218     34.45%     81.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           442406331     18.18%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2435260833                       # Type of FU issued
-system.cpu.iq.rate                           1.933798                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    87672520                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.036001                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6066045738                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3605651148                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2250091074                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           122483169                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           82625914                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     56426435                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2459629474                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                63303879                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         84463938                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2433397099                       # Type of FU issued
+system.cpu.iq.rate                           1.934979                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    87684102                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.036034                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6061689588                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3605336566                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2248845458                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           122494843                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           82642602                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     56425705                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2457771318                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                63309883                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         84349734                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    340244782                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        10257                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation      1430041                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    209203525                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    338992931                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        10163                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      1428185                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    211275181                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           356                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked           448                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              126518778                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                16487163                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1561706                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2793056470                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1389243                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             971631963                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            486198822                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              17636                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1558036                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  2522                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents        1430041                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       32401956                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1516006                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             33917962                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2359922616                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             794093704                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          75338217                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              126156453                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                15953141                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1561672                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2792906296                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1415032                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             970380112                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            488270478                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              17864                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1555530                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  2527                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        1428185                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       32514856                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1483129                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             33997985                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2358061254                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             792590559                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          75335845                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12456                       # number of nop insts executed
-system.cpu.iew.exec_refs                   1217365234                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                319562430                       # Number of branches executed
-system.cpu.iew.exec_stores                  423271530                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.873974                       # Inst execution rate
-system.cpu.iew.wb_sent                     2332280723                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2306517509                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1349120960                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2527351065                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         12476                       # number of nop insts executed
+system.cpu.iew.exec_refs                   1216220468                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                319843836                       # Number of branches executed
+system.cpu.iew.exec_stores                  423629909                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.875073                       # Inst execution rate
+system.cpu.iew.wb_sent                     2330961284                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2305271163                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1347649196                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2523801543                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.831566                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.533808                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.833096                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.533976                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       907720231                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       907570051                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           21384                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          30609492                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1090510834                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.728856                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.396955                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          30615394                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1090145073                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.729436                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.397108                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    450229589     41.29%     41.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    288600221     26.46%     67.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     95089363      8.72%     76.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     70207190      6.44%     82.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     46482431      4.26%     87.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     22180112      2.03%     89.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     15844912      1.45%     90.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     10980043      1.01%     91.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     90896973      8.34%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    449857024     41.27%     41.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    288588820     26.47%     67.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     95106380      8.72%     76.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     70218402      6.44%     82.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     46473981      4.26%     87.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     22183134      2.03%     89.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     15845043      1.45%     90.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10980592      1.01%     91.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     90891697      8.34%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1090510834                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1090145073                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1384381606                       # Number of instructions committed
 system.cpu.commit.committedOps             1885336358                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -608,240 +608,275 @@ system.cpu.commit.branches                  298259106                       # Nu
 system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1653698867                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              90896973                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        930022484     49.33%     49.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult        11168279      0.59%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     49.92% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd      1375288      0.07%     49.99% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     49.99% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp      6876469      0.36%     50.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt      5501172      0.29%     50.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     50.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc     22010188      1.17%     51.82% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     51.82% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.82% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.82% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       631387181     33.49%     85.31% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      276995297     14.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total        1885336358                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              90891697                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3792652105                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5712643141                       # The number of ROB writes
-system.cpu.timesIdled                          352993                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        42285162                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3792141440                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5711980108                       # The number of ROB writes
+system.cpu.timesIdled                          352856                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        41281940                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1384370590                       # Number of Instructions Simulated
 system.cpu.committedOps                    1885325342                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1384370590                       # Number of Instructions Simulated
-system.cpu.cpi                               0.909666                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.909666                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.099305                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.099305                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads              11767299799                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2220455487                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  68795103                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 49537962                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1678438007                       # number of misc regfile reads
+system.cpu.cpi                               0.908415                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.908415                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.100818                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.100818                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads              11756762903                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2218718479                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  68795802                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 49537143                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1677857394                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               13772902                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               168942873                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1493289                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1493289                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        96321                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         4299                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         4299                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        72517                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        72517                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        53208                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3179025                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3232233                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1565120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104535936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      106101056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         106101056                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       275072                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      929534000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               169149196                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1493034                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1493032                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        96318                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         4295                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         4295                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        72519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        72519                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52723                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3178995                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3231718                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1549696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104535104                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      106084800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         106084800                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       274816                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      929401499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      43545495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      43182746                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2368755772                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2371256268                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             22771                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1640.597248                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           334768394                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             24455                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          13689.159436                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             22529                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1644.627190                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           335917634                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             24213                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          13873.441292                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1640.597248                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801073                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801073                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1644.627190                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.803041                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.803041                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1684                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1545                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1552                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.822266                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         669636743                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        669636743                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    334772400                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       334772400                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     334772400                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        334772400                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    334772400                       # number of overall hits
-system.cpu.icache.overall_hits::total       334772400                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        31595                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         31595                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        31595                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          31595                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        31595                       # number of overall misses
-system.cpu.icache.overall_misses::total         31595                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    539866742                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    539866742                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    539866742                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    539866742                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    539866742                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    539866742                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    334803995                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    334803995                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    334803995                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    334803995                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    334803995                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    334803995                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000094                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000094                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000094                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000094                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000094                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000094                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17087.094224                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 17087.094224                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 17087.094224                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 17087.094224                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 17087.094224                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 17087.094224                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1720                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         671939144                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        671939144                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    335924107                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       335924107                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     335924107                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        335924107                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    335924107                       # number of overall hits
+system.cpu.icache.overall_hits::total       335924107                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        31211                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         31211                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        31211                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          31211                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        31211                       # number of overall misses
+system.cpu.icache.overall_misses::total         31211                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    530208992                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    530208992                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    530208992                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    530208992                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    530208992                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    530208992                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    335955318                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    335955318                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    335955318                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    335955318                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    335955318                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    335955318                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000093                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000093                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000093                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000093                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000093                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000093                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16987.888629                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16987.888629                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16987.888629                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16987.888629                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16987.888629                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16987.888629                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1881                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                34                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                32                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    50.588235                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    58.781250                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2842                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2842                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2842                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2842                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2842                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2842                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        28753                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        28753                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        28753                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        28753                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        28753                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        28753                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    429678502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    429678502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    429678502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    429678502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    429678502                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    429678502                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000086                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000086                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000086                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14943.779849                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14943.779849                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14943.779849                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14943.779849                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14943.779849                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14943.779849                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2702                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2702                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2702                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2702                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2702                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2702                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        28509                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        28509                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        28509                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        28509                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        28509                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        28509                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    424344751                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    424344751                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    424344751                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    424344751                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    424344751                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    424344751                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000085                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000085                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000085                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000085                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000085                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000085                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14884.589112                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14884.589112                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14884.589112                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14884.589112                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14884.589112                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14884.589112                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           442191                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32677.338993                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1109910                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           474938                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.336958                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           442179                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32677.883650                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1109649                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           474925                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.336472                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1321.185121                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    50.537350                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31305.616521                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.040319                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001542                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.955372                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997233                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32747                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          505                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5025                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26957                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999359                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13844482                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13844482                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        22025                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1058044                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1080069                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        96321                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        96321                       # number of Writeback hits
+system.cpu.l2cache.tags.occ_blocks::writebacks  1317.007846                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    51.079905                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31309.795899                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.040192                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001559                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.955499                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997250                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32746                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          509                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5033                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26955                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999329                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13842423                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13842423                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        21791                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1058039                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1079830                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        96318                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        96318                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         6440                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         6440                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        22025                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1064484                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1086509                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        22025                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1064484                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1086509                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2430                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       406492                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       408922                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         4296                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         4296                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        66077                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66077                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2430                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       472569                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        474999                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2430                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       472569                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       474999                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    176338750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  30866203500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  31042542250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4447510000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4447510000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    176338750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  35313713500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  35490052250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    176338750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  35313713500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  35490052250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        24455                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1464536                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1488991                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks        96321                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        96321                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4299                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         4299                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        72517                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        72517                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        24455                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1537053                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1561508                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        24455                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1537053                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1561508                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.099366                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.277557                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.274630                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_hits::cpu.data         6441                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         6441                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        21791                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1064480                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1086271                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        21791                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1064480                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1086271                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2424                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       406486                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       408910                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         4292                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         4292                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66078                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66078                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2424                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       472564                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        474988                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2424                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       472564                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       474988                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    173590500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  30155031750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  30328622250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4756999500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4756999500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    173590500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  34912031250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  35085621750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    173590500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  34912031250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  35085621750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        24215                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1464525                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1488740                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        96318                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        96318                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4295                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         4295                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        72519                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        72519                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        24215                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1537044                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1561259                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        24215                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1537044                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1561259                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.100103                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.277555                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.274669                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999302                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999302                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911193                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911193                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.099366                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.307451                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.304192                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.099366                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.307451                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.304192                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72567.386831                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75933.114305                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75913.113626                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67307.989164                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67307.989164                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72567.386831                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74727.105460                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74716.056771                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72567.386831                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74727.105460                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74716.056771                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911182                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911182                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.100103                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.307450                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.304234                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.100103                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.307450                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.304234                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71613.242574                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74184.674872                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74169.431538                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71990.670117                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71990.670117                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71613.242574                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73877.890085                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73866.332939                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71613.242574                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73877.890085                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73866.332939                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -861,193 +896,193 @@ system.cpu.l2cache.demand_mshr_hits::total           26                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           24                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           26                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2428                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406468                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       408896                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4296                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         4296                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66077                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66077                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2428                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       472545                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       474973                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2428                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       472545                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       474973                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    145726000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  25804582750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  25950308750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     42964296                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     42964296                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3615056500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3615056500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    145726000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  29419639250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  29565365250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    145726000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  29419639250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  29565365250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.099284                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.277540                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.274613                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2422                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406462                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       408884                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4292                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         4292                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66078                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66078                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2422                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       472540                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       474962                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2422                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       472540                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       474962                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    143052750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  25094264500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  25237317250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     42924292                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     42924292                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3924413500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3924413500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    143052750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  29018678000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  29161730750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    143052750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  29018678000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  29161730750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.100021                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.277538                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.274651                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999302                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999302                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911193                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911193                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.099284                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.307436                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.304176                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.099284                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.307436                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.304176                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60018.945634                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63484.905946                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63464.325281                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911182                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911182                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.100021                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.307434                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.304217                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.100021                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.307434                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.304217                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59063.893476                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61738.279347                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61722.437782                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54709.755286                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54709.755286                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60018.945634                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62257.857453                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62246.412428                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60018.945634                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62257.857453                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62246.412428                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.621690                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.621690                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59063.893476                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61409.992805                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61398.029211                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59063.893476                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61409.992805                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61398.029211                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1532957                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.373897                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           971355471                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1537053                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            631.959647                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         402104250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4094.373897                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999603                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999603                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1532947                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4094.376885                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           969983510                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1537043                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            631.071161                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         400583250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4094.376885                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999604                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999604                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          265                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          973                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2410                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          400                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          263                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          978                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2415                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          394                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1949798453                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1949798453                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    695221170                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       695221170                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    276100593                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      276100593                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        10000                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        10000                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses        1947074947                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1947074947                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    693859178                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       693859178                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    276090749                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      276090749                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        10001                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        10001                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         9985                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     971321763                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        971321763                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    971321763                       # number of overall hits
-system.cpu.dcache.overall_hits::total       971321763                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1953864                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1953864                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       835085                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       835085                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     969949927                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        969949927                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    969949927                       # number of overall hits
+system.cpu.dcache.overall_hits::total       969949927                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1954107                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1954107                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       844929                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       844929                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2788949                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2788949                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2788949                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2788949                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  82025897599                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  82025897599                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  54715114042                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  54715114042                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       225000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       225000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 136741011641                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 136741011641                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 136741011641                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 136741011641                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    697175034                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    697175034                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      2799036                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2799036                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2799036                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2799036                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  79576585056                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  79576585056                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  58758638704                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  58758638704                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       210750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       210750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 138335223760                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 138335223760                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 138335223760                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 138335223760                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    695813285                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    695813285                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10003                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        10003                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10004                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        10004                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         9985                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    974110712                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    974110712                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    974110712                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    974110712                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002803                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002803                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003015                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.003015                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    972748963                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    972748963                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    972748963                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    972748963                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002808                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002808                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003051                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.003051                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000300                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000300                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002863                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002863                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002863                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002863                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41981.375162                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41981.375162                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65520.412942                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65520.412942                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        75000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        75000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 49029.584851                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 49029.584851                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 49029.584851                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 49029.584851                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         2327                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          933                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                51                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              89                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.627451                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    10.483146                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002877                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002877                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002877                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002877                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40722.736808                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40722.736808                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69542.693770                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69542.693770                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        70250                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        70250                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 49422.452502                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 49422.452502                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 49422.452502                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 49422.452502                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         2414                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          988                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                54                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              92                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    44.703704                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    10.739130                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        96321                       # number of writebacks
-system.cpu.dcache.writebacks::total             96321                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       489326                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       489326                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       758271                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       758271                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        96318                       # number of writebacks
+system.cpu.dcache.writebacks::total             96318                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       489582                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       489582                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       768115                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       768115                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1247597                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1247597                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1247597                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1247597                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464538                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1464538                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      1257697                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1257697                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1257697                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1257697                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464525                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1464525                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        76814                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        76814                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1541352                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1541352                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1541352                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1541352                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  42911632024                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  42911632024                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4684436204                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4684436204                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47596068228                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  47596068228                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47596068228                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  47596068228                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002101                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002101                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1541339                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1541339                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1541339                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1541339                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  42200288024                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  42200288024                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4993959708                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4993959708                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47194247732                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  47194247732                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47194247732                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  47194247732                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002105                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002105                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000277                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000277                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001582                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.001582                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001582                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001582                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29300.456543                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29300.456543                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60984.146171                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60984.146171                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30879.428079                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30879.428079                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30879.428079                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30879.428079                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.001585                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.001585                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28815.000102                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28815.000102                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65013.665582                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65013.665582                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30618.992793                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30618.992793                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30618.992793                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30618.992793                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index c7a89f409..620dbb60e 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.945613                       # Nu
 sim_ticks                                945613126000                       # Number of ticks simulated
 final_tick                               945613126000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1077492                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1467395                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              735989505                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323780                       # Number of bytes of host memory used
-host_seconds                                  1284.82                       # Real time elapsed on the host
+host_inst_rate                                1407956                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1917442                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              961716087                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309672                       # Number of bytes of host memory used
+host_seconds                                   983.26                       # Real time elapsed on the host
 sim_insts                                  1384381606                       # Number of instructions simulated
 sim_ops                                    1885336358                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,5 +147,40 @@ system.cpu.num_busy_cycles                 1891226253                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         298259106                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 930023895     49.33%     49.33% # Class of executed instruction
+system.cpu.op_class::IntMult                 11168279      0.59%     49.92% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd             1375288      0.07%     49.99% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     49.99% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp             6876469      0.36%     50.36% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt             5501172      0.29%     50.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     50.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc           22010188      1.17%     51.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     51.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     51.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     51.82% # Class of executed instruction
+system.cpu.op_class::MemRead                631387181     33.49%     85.31% # Class of executed instruction
+system.cpu.op_class::MemWrite               276995298     14.69%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 1885337770                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index a5a3b48d5..baba5d53b 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.326119                       # Nu
 sim_ticks                                2326118592000                       # Number of ticks simulated
 final_tick                               2326118592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 546207                       # Simulator instruction rate (inst/s)
-host_op_rate                                   740969                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              919614125                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 332488                       # Number of bytes of host memory used
-host_seconds                                  2529.45                       # Real time elapsed on the host
+host_inst_rate                                 706219                       # Simulator instruction rate (inst/s)
+host_op_rate                                   958037                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1189016431                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318376                       # Number of bytes of host memory used
+host_seconds                                  1956.34                       # Real time elapsed on the host
 sim_insts                                  1381604339                       # Number of instructions simulated
 sim_ops                                    1874244941                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -161,6 +161,41 @@ system.cpu.num_busy_cycles                 4652237184                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         298259106                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 930023895     49.33%     49.33% # Class of executed instruction
+system.cpu.op_class::IntMult                 11168279      0.59%     49.92% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     49.92% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd             1375288      0.07%     49.99% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     49.99% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp             6876469      0.36%     50.36% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt             5501172      0.29%     50.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     50.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc           22010188      1.17%     51.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     51.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     51.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     51.82% # Class of executed instruction
+system.cpu.op_class::MemRead                631387181     33.49%     85.31% # Class of executed instruction
+system.cpu.op_class::MemWrite               276995298     14.69%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 1885337770                       # Class of executed instruction
 system.cpu.icache.tags.replacements             18364                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1392.317060                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1390251699                       # Total number of references to valid blocks.
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index f3edc5948..ca907eb24 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.043459                       # Number of seconds simulated
-sim_ticks                                 43458818000                       # Number of ticks simulated
-final_tick                                43458818000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.043473                       # Number of seconds simulated
+sim_ticks                                 43472869000                       # Number of ticks simulated
+final_tick                                43472869000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 114678                       # Simulator instruction rate (inst/s)
-host_op_rate                                   114678                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               56415550                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273516                       # Number of bytes of host memory used
-host_seconds                                   770.33                       # Real time elapsed on the host
+host_inst_rate                                 112027                       # Simulator instruction rate (inst/s)
+host_op_rate                                   112027                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               55129043                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 274568                       # Number of bytes of host memory used
+host_seconds                                   788.57                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -25,31 +25,31 @@ system.physmem.num_reads::cpu.data             158412                       # Nu
 system.physmem.num_reads::total                165515                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          113997                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               113997                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             10460294                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            233286787                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               243747080                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        10460294                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           10460294                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         167878657                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              167878657                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         167878657                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            10460294                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           233286787                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              411625737                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst             10456913                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            233211385                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               243668298                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        10456913                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           10456913                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         167824396                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              167824396                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         167824396                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            10456913                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           233211385                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              411492694                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        165515                       # Number of read requests accepted
 system.physmem.writeReqs                       113997                       # Number of write requests accepted
 system.physmem.readBursts                      165515                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                     113997                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10592576                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7294400                       # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM                 10592320                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       640                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7293824                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                  10592960                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                7295808                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                       10                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               10379                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10437                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10436                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10256                       # Per bank write bursts
 system.physmem.perBankRdBursts::3               10015                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               10350                       # Per bank write bursts
@@ -58,9 +58,9 @@ system.physmem.perBankRdBursts::6                9796                       # Pe
 system.physmem.perBankRdBursts::7               10273                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               10509                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               10590                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10477                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10475                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              10188                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10236                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10235                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              10580                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              10468                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              10593                       # Per bank write bursts
@@ -71,18 +71,18 @@ system.physmem.perBankWrBursts::3                6998                       # Pe
 system.physmem.perBankWrBursts::4                7125                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7170                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6769                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7092                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7216                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7083                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7217                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                6938                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7083                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7081                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6989                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               6963                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7284                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7281                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7282                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     43458797000                       # Total gap between requests
+system.physmem.totGap                     43472848000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -97,11 +97,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                 113997                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     69517                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     66164                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     19662                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     10165                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     70302                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     51581                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     34122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9498                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,45 +144,45 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      866                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6714                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8033                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8481                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8308                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     3822                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      910                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      997                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2833                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4913                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6026                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6448                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6974                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7765                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8823                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8420                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8642                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8027                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
@@ -193,83 +193,71 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        41807                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      385.014950                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     230.118388                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     358.708548                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12628     30.21%     30.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8632     20.65%     50.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4415     10.56%     61.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2749      6.58%     67.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2263      5.41%     73.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1680      4.02%     77.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1442      3.45%     80.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1629      3.90%     84.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6369     15.23%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          41807                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6909                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.954842                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      351.043824                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           6907     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        52007                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      343.898321                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     202.122220                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     343.471226                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          18183     34.96%     34.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10752     20.67%     55.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5531     10.64%     66.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3167      6.09%     72.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2729      5.25%     77.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1801      3.46%     81.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1676      3.22%     84.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1325      2.55%     86.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6843     13.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          52007                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6952                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.806818                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      349.983272                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6951     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6909                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6909                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.496599                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.404036                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.150839                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6289     91.03%     91.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 13      0.19%     91.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 61      0.88%     92.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                166      2.40%     94.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                127      1.84%     96.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 73      1.06%     97.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 63      0.91%     98.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 29      0.42%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 18      0.26%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 12      0.17%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  7      0.10%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  3      0.04%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  3      0.04%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.01%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  2      0.03%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  3      0.04%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  2      0.03%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  3      0.04%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  2      0.03%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  3      0.04%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  2      0.03%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                 19      0.28%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  5      0.07%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  2      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6909                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5306478250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                7800537000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    827545000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1666513750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       32061.57                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    10069.02                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            6952                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6951                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.395339                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.363988                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.079809                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               5950     85.60%     85.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 35      0.50%     86.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                555      7.98%     94.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                213      3.06%     97.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                101      1.45%     98.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 56      0.81%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 23      0.33%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 12      0.17%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6951                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4829573500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                7932792250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    827525000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29180.83                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47130.59                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         243.74                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         167.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      243.75                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      167.88                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47930.83                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         243.65                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         167.78                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      243.67                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      167.82                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.22                       # Data bus utilization in percentage
+system.physmem.busUtil                           3.21                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.90                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      1.31                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.84                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144461                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     82889                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.28                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  72.71                       # Row buffer hit rate for writes
-system.physmem.avgGap                       155480.97                       # Average gap between requests
-system.physmem.pageHitRate                      81.34                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              10.25                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    411625737                       # Throughput (bytes/s)
+system.physmem.avgRdQLen                         1.47                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145183                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82273                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.72                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  72.17                       # Row buffer hit rate for writes
+system.physmem.avgGap                       155531.24                       # Average gap between requests
+system.physmem.pageHitRate                      81.38                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      26086323250                       # Time in different power states
+system.physmem.memoryStateTime::REF        1451580000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       15933004250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    411492694                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq               34625                       # Transaction distribution
 system.membus.trans_dist::ReadResp              34625                       # Transaction distribution
 system.membus.trans_dist::Writeback            113997                       # Transaction distribution
@@ -281,40 +269,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total            17888768                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus               17888768                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1219845000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1219071000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1520840750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1523545750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                18742760                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          12318400                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                18742718                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          12318358                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           4775680                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             15507492                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups             15507357                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                 4664025                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             30.075947                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             30.076208                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 1660965                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               1030                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20277780                       # DTB read hits
+system.cpu.dtb.read_hits                     20277728                       # DTB read hits
 system.cpu.dtb.read_misses                      90148                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20367928                       # DTB read accesses
-system.cpu.dtb.write_hits                    14729056                       # DTB write hits
+system.cpu.dtb.read_accesses                 20367876                       # DTB read accesses
+system.cpu.dtb.write_hits                    14728971                       # DTB write hits
 system.cpu.dtb.write_misses                      7252                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14736308                       # DTB write accesses
-system.cpu.dtb.data_hits                     35006836                       # DTB hits
+system.cpu.dtb.write_accesses                14736223                       # DTB write accesses
+system.cpu.dtb.data_hits                     35006699                       # DTB hits
 system.cpu.dtb.data_misses                      97400                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 35104236                       # DTB accesses
-system.cpu.itb.fetch_hits                    12367757                       # ITB hits
+system.cpu.dtb.data_accesses                 35104099                       # DTB accesses
+system.cpu.itb.fetch_hits                    12367762                       # ITB hits
 system.cpu.itb.fetch_misses                     11021                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                12378778                       # ITB accesses
+system.cpu.itb.fetch_accesses                12378783                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -328,34 +316,34 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         86917637                       # number of cpu cycles simulated
+system.cpu.numCycles                         86945739                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken      8074236                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken     10668524                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads     74162131                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedNotTaken     10668482                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads     74162124                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites     52319250                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses    126481381                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses    126481374                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads        66044                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites       227630                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses       293674                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards       14174243                       # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards       14174248                       # Number of Registers Read Through Forwarding Logic
 system.cpu.agen_unit.agens                   35060070                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect      4449011                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.execution_unit.predictedNotTakenIncorrect       216169                       # Number of Branches Incorrectly Predicted As Not Taken).
 system.cpu.execution_unit.mispredicted        4665180                       # Number of Branches Incorrectly Predicted
 system.cpu.execution_unit.predicted           9107422                       # Number of Branches Incorrectly Predicted
 system.cpu.execution_unit.mispredictPct     33.872902                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions         44777932                       # Number of Instructions Executed.
+system.cpu.execution_unit.executions         44777931                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies             41107                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                      77191042                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                      77212885                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                          229429                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        17341864                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                         69575773                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         80.047934                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                          241035                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        17370075                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         69575664                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         80.021936                       # Percentage of cycles cpu is active
 system.cpu.comLoads                          20276638                       # Number of Load instructions committed
 system.cpu.comStores                         14613377                       # Number of Store instructions committed
 system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
@@ -367,120 +355,120 @@ system.cpu.committedInsts                    88340673                       # Nu
 system.cpu.committedOps                      88340673                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total              88340673                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.983891                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               0.984210                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.983891                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.016372                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         0.984210                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.016044                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.016372                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                 34262012                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                  52655625                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               60.581059                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                 44462439                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                  42455198                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               48.845320                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                 43887105                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                  43030532                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               49.507250                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                 64797015                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                  22120622                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               25.450096                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                 40875399                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                  46042238                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               52.972262                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         1.016044                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                 34290146                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  52655593                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               60.561442                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 44490597                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  42455142                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               48.829468                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 43915285                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                  43030454                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               49.491159                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 64825125                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  22120614                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               25.441861                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 40903528                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                  46042211                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               52.955109                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements             84371                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1905.831723                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            12250503                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1906.099937                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            12250492                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             86417                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            141.760337                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs            141.760209                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1905.831723                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.930582                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.930582                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1906.099937                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.930713                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.930713                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2046                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3         1090                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          790                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          24821911                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         24821911                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     12250503                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        12250503                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      12250503                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         12250503                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     12250503                       # number of overall hits
-system.cpu.icache.overall_hits::total        12250503                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       117244                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        117244                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       117244                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         117244                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       117244                       # number of overall misses
-system.cpu.icache.overall_misses::total        117244                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1999895234                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1999895234                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1999895234                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1999895234                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1999895234                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1999895234                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     12367747                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     12367747                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     12367747                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     12367747                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     12367747                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     12367747                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.009480                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.009480                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.009480                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.009480                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.009480                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.009480                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17057.548651                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 17057.548651                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 17057.548651                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 17057.548651                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 17057.548651                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 17057.548651                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          343                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          24821923                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         24821923                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     12250492                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12250492                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12250492                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12250492                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12250492                       # number of overall hits
+system.cpu.icache.overall_hits::total        12250492                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       117261                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        117261                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       117261                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         117261                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       117261                       # number of overall misses
+system.cpu.icache.overall_misses::total        117261                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1989588981                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1989588981                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1989588981                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1989588981                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1989588981                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1989588981                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     12367753                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     12367753                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     12367753                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     12367753                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     12367753                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     12367753                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.009481                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.009481                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.009481                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.009481                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.009481                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.009481                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16967.184153                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16967.184153                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16967.184153                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16967.184153                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16967.184153                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16967.184153                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          347                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets          192                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    22.866667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    23.133333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets           48                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        30827                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        30827                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        30827                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        30827                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        30827                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        30827                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        30844                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        30844                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        30844                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        30844                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        30844                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        30844                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        86417                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        86417                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        86417                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total        86417                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        86417                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        86417                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1419611513                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1419611513                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1419611513                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1419611513                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1419611513                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1419611513                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1409598264                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1409598264                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1409598264                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1409598264                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1409598264                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1409598264                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006987                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006987                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006987                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.006987                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006987                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.006987                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16427.456554                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16427.456554                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16427.456554                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16427.456554                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16427.456554                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16427.456554                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16311.585267                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16311.585267                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16311.585267                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16311.585267                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16311.585267                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16311.585267                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               676121104                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput               675902573                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq         146995                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        146995                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       168352                       # Transaction distribution
@@ -496,28 +484,28 @@ system.cpu.toL2Bus.data_through_bus          29383424                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy      397910000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     130829487                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     130854736                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     323146469                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     326587968                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements           131591                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30877.243576                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        30879.620467                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             151434                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           163651                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.925347                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 27092.654478                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2007.905024                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1776.684074                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.826802                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061276                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.054220                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.942299                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 27087.517417                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2008.809532                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1783.293518                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.826645                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061304                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.054422                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.942371                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32060                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        17173                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13478                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1167                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        17062                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13579                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4          108                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978394                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          3980348                       # Number of tag accesses
@@ -546,17 +534,17 @@ system.cpu.l2cache.demand_misses::total        165515                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         7103                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       158412                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       165515                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    537407000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1972226500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2509633500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12899781250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  12899781250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    537407000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  14872007750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  15409414750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    537407000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  14872007750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  15409414750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    527407000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2000529000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2527936000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12857601250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  12857601250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    527407000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  14858130250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  15385537250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    527407000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  14858130250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  15385537250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        86417                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data        60578                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       146995                       # number of ReadReq accesses(hits+misses)
@@ -581,17 +569,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.569242                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.082194                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.775211                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.569242                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75659.158102                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71659.999273                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72480.389892                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98554.368172                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98554.368172                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75659.158102                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93881.825556                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 93099.808174                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75659.158102                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93881.825556                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 93099.808174                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74251.302267                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72688.358404                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73008.981949                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98232.112843                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98232.112843                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74251.302267                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93794.221713                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 92955.546325                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74251.302267                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93794.221713                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 92955.546325                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -613,17 +601,17 @@ system.cpu.l2cache.demand_mshr_misses::total       165515
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         7103                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       158412                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       165515                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    448296500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1624855000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2073151500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11301062250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11301062250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    448296500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12925917250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  13374213750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    448296500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12925917250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  13374213750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    438280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1653149000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2091429000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11252735250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11252735250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    438280000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12905884250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  13344164250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    438280000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12905884250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  13344164250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.082194                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.454323                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.235552                       # mshr miss rate for ReadReq accesses
@@ -635,58 +623,58 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.569242
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.082194                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.775211                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.569242                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63113.684359                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59038.405639                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59874.411552                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86340.150126                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86340.150126                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63113.684359                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81596.831364                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80803.635622                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63113.684359                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81596.831364                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80803.635622                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61703.505561                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60066.455926                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60402.281588                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85970.931698                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85970.931698                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61703.505561                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81470.369985                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80622.084101                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61703.505561                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81470.369985                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80622.084101                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements            200251                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4076.081511                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            33755026                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4076.191917                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            33755204                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            204347                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            165.184838                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         302612000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4076.081511                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.995137                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.995137                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            165.185709                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         301118000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4076.191917                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.995164                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.995164                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          922                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3108                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          933                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3099                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          69984377                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         69984377                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20180293                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20180293                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13574733                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13574733                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      33755026                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         33755026                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     33755026                       # number of overall hits
-system.cpu.dcache.overall_hits::total        33755026                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        96345                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         96345                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1038644                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1038644                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1134989                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1134989                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1134989                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1134989                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   4945314984                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4945314984                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  82211352380                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  82211352380                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  87156667364                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  87156667364                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  87156667364                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  87156667364                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_hits::cpu.data     20180307                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20180307                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13574897                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13574897                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      33755204                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         33755204                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     33755204                       # number of overall hits
+system.cpu.dcache.overall_hits::total        33755204                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        96331                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         96331                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1038480                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1038480                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1134811                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1134811                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1134811                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1134811                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5018382484                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5018382484                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  82442485122                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  82442485122                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  87460867606                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  87460867606                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  87460867606                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  87460867606                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
@@ -695,40 +683,40 @@ system.cpu.dcache.demand_accesses::cpu.data     34890015                       #
 system.cpu.dcache.demand_accesses::total     34890015                       # number of demand (read+write) accesses
 system.cpu.dcache.overall_accesses::cpu.data     34890015                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004752                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004752                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071075                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.071075                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032530                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032530                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032530                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032530                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51329.233318                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51329.233318                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79152.580076                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 79152.580076                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76790.759526                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76790.759526                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76790.759526                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76790.759526                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      5467849                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004751                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004751                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071064                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.071064                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032525                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032525                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032525                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032525                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52095.197641                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 52095.197641                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79387.648411                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 79387.648411                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 77070.866960                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 77070.866960                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 77070.866960                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 77070.866960                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      5473044                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets           77                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            116872                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            116736                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.784936                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.883943                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets           77                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       168352                       # number of writebacks
 system.cpu.dcache.writebacks::total            168352                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        35578                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        35578                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       895064                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       895064                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       930642                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       930642                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       930642                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       930642                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        35564                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        35564                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       894900                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       894900                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       930464                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       930464                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       930464                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       930464                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60767                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        60767                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143580                       # number of WriteReq MSHR misses
@@ -737,14 +725,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       204347
 system.cpu.dcache.demand_mshr_misses::total       204347                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       204347                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       204347                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2366861266                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2366861266                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13170287765                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  13170287765                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15537149031                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15537149031                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15537149031                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15537149031                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2395231766                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2395231766                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13128048266                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  13128048266                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15523280032                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15523280032                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15523280032                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15523280032                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
@@ -753,14 +741,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005857                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005857                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38949.779749                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38949.779749                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91727.871326                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91727.871326                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76033.164328                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76033.164328                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76033.164328                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76033.164328                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39416.653216                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39416.653216                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91433.683424                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91433.683424                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75965.294484                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75965.294484                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75965.294484                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75965.294484                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 7573bf6de..1536d4b0d 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.024671                       # Number of seconds simulated
-sim_ticks                                 24670906500                       # Number of ticks simulated
-final_tick                                24670906500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.024636                       # Number of seconds simulated
+sim_ticks                                 24636200500                       # Number of ticks simulated
+final_tick                                24636200500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168282                       # Simulator instruction rate (inst/s)
-host_op_rate                                   168282                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52161952                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 276592                       # Number of bytes of host memory used
-host_seconds                                   472.97                       # Real time elapsed on the host
+host_inst_rate                                 166481                       # Simulator instruction rate (inst/s)
+host_op_rate                                   166481                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               51531279                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277620                       # Number of bytes of host memory used
+host_seconds                                   478.08                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            489344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10153856                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10643200                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       489344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          489344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7297088                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7297088                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               7646                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158654                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166300                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114017                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114017                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             19834861                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            411572068                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               431406929                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        19834861                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           19834861                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         295777052                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              295777052                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         295777052                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            19834861                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           411572068                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              727183981                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166300                       # Number of read requests accepted
-system.physmem.writeReqs                       114017                       # Number of write requests accepted
-system.physmem.readBursts                      166300                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114017                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10642752                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7295296                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10643200                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7297088                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            491136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10153600                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10644736                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       491136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          491136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7296704                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7296704                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               7674                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158650                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166324                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114011                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114011                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             19935542                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            412141474                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               432077016                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        19935542                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           19935542                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         296178138                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              296178138                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         296178138                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            19935542                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           412141474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              728255154                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166324                       # Number of read requests accepted
+system.physmem.writeReqs                       114011                       # Number of write requests accepted
+system.physmem.readBursts                      166324                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114011                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10644224                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       512                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7295040                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10644736                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7296704                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        8                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10427                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10465                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10308                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10056                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10424                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10403                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9851                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10318                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10615                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10435                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10464                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10314                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10058                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10432                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10406                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9849                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10311                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10614                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               10643                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10551                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10228                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10273                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10549                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10230                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10275                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              10619                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10486                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10626                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10489                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10628                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7082                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7259                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7254                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                6997                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7126                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7170                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6771                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7086                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6770                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7085                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7222                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                6941                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7084                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6991                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6963                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7287                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7083                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6990                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6966                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7286                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7286                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     24670873000                       # Total gap between requests
+system.physmem.totGap                     24636167000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166300                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166324                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114017                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     69085                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     53344                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     32724                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     11125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114011                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     69812                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     50543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     36166                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9786                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,45 +144,45 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4892                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5900                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7340                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7462                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8096                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7688                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     3526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2094                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      889                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      844                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      885                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3986                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6528                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6848                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7670                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8505                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
@@ -193,129 +193,114 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        43247                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      376.488173                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     224.222062                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     355.745587                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13435     31.07%     31.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8988     20.78%     51.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4626     10.70%     62.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2682      6.20%     68.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2451      5.67%     74.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1626      3.76%     78.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1548      3.58%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1315      3.04%     84.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6576     15.21%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          43247                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6943                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.949301                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      342.898812                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           6941     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        52591                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      341.105360                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     200.170415                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.733138                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          18652     35.47%     35.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10746     20.43%     55.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5782     10.99%     66.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3058      5.81%     72.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2757      5.24%     77.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1645      3.13%     81.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1894      3.60%     84.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1108      2.11%     86.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6949     13.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          52591                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6971                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.856692                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      342.122530                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6970     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6943                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6943                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.417831                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.341311                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.942818                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6412     92.35%     92.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 14      0.20%     92.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 48      0.69%     93.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                135      1.94%     95.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                111      1.60%     96.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 69      0.99%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 62      0.89%     98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 19      0.27%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 14      0.20%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  9      0.13%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  3      0.04%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  6      0.09%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  5      0.07%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.06%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  3      0.04%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  1      0.01%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  3      0.04%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.01%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  4      0.06%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  2      0.03%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  1      0.01%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                 10      0.14%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  2      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  2      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6943                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5579601250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                7987531250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    831465000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1576465000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       33552.83                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     9480.04                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            6971                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6971                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.351313                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.323948                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.004197                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6065     87.00%     87.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 30      0.43%     87.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                507      7.27%     94.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                200      2.87%     97.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 92      1.32%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 44      0.63%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 23      0.33%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  4      0.06%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  3      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  3      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6971                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4932812500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8051237500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    831580000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29659.28                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  48032.88                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         431.39                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         295.70                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      431.41                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      295.78                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  48409.28                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         432.06                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         296.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      432.08                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      296.18                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           5.68                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.37                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           5.69                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      2.31                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.68                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.84                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144952                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     82533                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.17                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  72.39                       # Row buffer hit rate for writes
-system.physmem.avgGap                        88010.62                       # Average gap between requests
-system.physmem.pageHitRate                      81.15                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              12.46                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    727183981                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               35502                       # Transaction distribution
-system.membus.trans_dist::ReadResp              35502                       # Transaction distribution
-system.membus.trans_dist::Writeback            114017                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130798                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130798                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446617                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 446617                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17940288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            17940288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               17940288                       # Total data (bytes)
+system.physmem.avgWrQLen                        24.48                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145935                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81773                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.75                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.72                       # Row buffer hit rate for writes
+system.physmem.avgGap                        87881.17                       # Average gap between requests
+system.physmem.pageHitRate                      81.23                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      10235619000                       # Time in different power states
+system.physmem.memoryStateTime::REF         822640000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       13577715750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    728255154                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               35531                       # Transaction distribution
+system.membus.trans_dist::ReadResp              35531                       # Transaction distribution
+system.membus.trans_dist::Writeback            114011                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130793                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130793                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446659                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 446659                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17941440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            17941440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               17941440                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1242249500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1239417000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               5.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1535210250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              6.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1541901750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              6.3                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                16545461                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10688882                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            416220                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11528806                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7341014                       # Number of BTB hits
+system.cpu.branchPred.lookups                16532258                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10678400                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            414272                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11254854                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7335293                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             63.675406                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1988101                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              40517                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.174484                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1985053                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              41515                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22395847                       # DTB read hits
-system.cpu.dtb.read_misses                     219375                       # DTB read misses
-system.cpu.dtb.read_acv                            51                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22615222                       # DTB read accesses
-system.cpu.dtb.write_hits                    15705719                       # DTB write hits
-system.cpu.dtb.write_misses                     41176                       # DTB write misses
-system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_accesses                15746895                       # DTB write accesses
-system.cpu.dtb.data_hits                     38101566                       # DTB hits
-system.cpu.dtb.data_misses                     260551                       # DTB misses
-system.cpu.dtb.data_acv                            53                       # DTB access violations
-system.cpu.dtb.data_accesses                 38362117                       # DTB accesses
-system.cpu.itb.fetch_hits                    13909771                       # ITB hits
-system.cpu.itb.fetch_misses                     35326                       # ITB misses
+system.cpu.dtb.read_hits                     22389116                       # DTB read hits
+system.cpu.dtb.read_misses                     220601                       # DTB read misses
+system.cpu.dtb.read_acv                            47                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22609717                       # DTB read accesses
+system.cpu.dtb.write_hits                    15701492                       # DTB write hits
+system.cpu.dtb.write_misses                     40930                       # DTB write misses
+system.cpu.dtb.write_acv                            4                       # DTB write access violations
+system.cpu.dtb.write_accesses                15742422                       # DTB write accesses
+system.cpu.dtb.data_hits                     38090608                       # DTB hits
+system.cpu.dtb.data_misses                     261531                       # DTB misses
+system.cpu.dtb.data_acv                            51                       # DTB access violations
+system.cpu.dtb.data_accesses                 38352139                       # DTB accesses
+system.cpu.itb.fetch_hits                    13899561                       # ITB hits
+system.cpu.itb.fetch_misses                     35223                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                13945097                       # ITB accesses
+system.cpu.itb.fetch_accesses                13934784                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -329,139 +314,139 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         49341816                       # number of cpu cycles simulated
+system.cpu.numCycles                         49272404                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15790710                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      105357061                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16545461                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9329115                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      19544756                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1999793                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                7570274                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 7578                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        314157                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           37                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13909771                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                205601                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           44679590                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.358058                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.120608                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           15777525                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      105311558                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16532258                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9320346                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      19533612                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1991452                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                7584858                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 7736                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        311235                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           81                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13899561                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                206313                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           44661692                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.357984                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.120695                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 25134834     56.26%     56.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1529938      3.42%     59.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1370308      3.07%     62.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1511826      3.38%     66.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4137251      9.26%     75.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1848058      4.14%     79.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   674230      1.51%     81.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1068805      2.39%     83.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7404340     16.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 25128080     56.26%     56.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1526401      3.42%     59.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1371052      3.07%     62.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1506745      3.37%     66.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4140649      9.27%     75.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1845293      4.13%     79.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   672736      1.51%     81.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1068547      2.39%     83.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7402189     16.57%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             44679590                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.335323                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.135249                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16882265                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               7097756                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18571135                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                780643                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1347791                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3745694                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                106722                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              103639332                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                302042                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1347791                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 17356196                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4802628                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          85206                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18838214                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               2249555                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102372003                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   486                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                   2542                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2130672                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            61646955                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             123349032                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        123030884                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            318147                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             44661692                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.335528                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.137333                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 16866897                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               7111825                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18558707                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                782025                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1342238                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3745907                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                106790                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              103587056                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                304363                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1342238                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 17337019                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4756497                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          85160                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18837400                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               2303378                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102332178                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   523                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                   2649                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2191032                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            61618182                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             123319781                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        123000606                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            319174                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9100074                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5525                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5523                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   4824517                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23234080                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16271017                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1195142                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           460766                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   90738136                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5320                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  88425930                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             95845                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        10681231                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4663960                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            737                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      44679590                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.979112                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.109137                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  9071301                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5539                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5537                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   4823048                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23221608                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16268601                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1205921                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           453901                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   90714313                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5368                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  88410610                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             95528                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        10671258                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4645313                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            785                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      44661692                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.979562                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.108908                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            16474837     36.87%     36.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             6839728     15.31%     52.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5595634     12.52%     64.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4775900     10.69%     75.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4713198     10.55%     85.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2628457      5.88%     91.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1926364      4.31%     96.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1289803      2.89%     99.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              435669      0.98%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            16438268     36.81%     36.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             6883864     15.41%     52.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5570491     12.47%     64.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4772833     10.69%     75.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4726674     10.58%     85.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2623655      5.87%     91.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1921880      4.30%     96.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1281202      2.87%     99.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              442825      0.99%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        44679590                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        44661692                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  126495      6.81%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 783002     42.16%     48.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                947503     51.02%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  125753      6.74%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 787939     42.23%     48.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                952099     51.03%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49357567     55.82%     55.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                43846      0.05%     55.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49354396     55.82%     55.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43843      0.05%     55.87% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121254      0.14%     56.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  91      0.00%     56.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              121135      0.14%     56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 59      0.00%     56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               38967      0.04%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121164      0.14%     56.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  92      0.00%     56.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              120950      0.14%     56.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 59      0.00%     56.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               38951      0.04%     56.19% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.19% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.19% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.19% # Type of FU issued
@@ -483,84 +468,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.19% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.19% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.19% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             22848069     25.84%     82.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            15894942     17.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22839676     25.83%     82.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            15891479     17.97%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               88425930                       # Type of FU issued
-system.cpu.iq.rate                           1.792109                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1857000                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.021001                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          222881148                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         101028016                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     86544064                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              603147                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             414515                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       294050                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               89981281                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  301649                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1467705                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               88410610                       # Type of FU issued
+system.cpu.iq.rate                           1.794323                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1865791                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.021104                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          222840563                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         100994037                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     86537266                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              603668                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             414920                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       294049                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               89974489                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  301912                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1467836                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2957442                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         4633                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18287                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1657640                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2944970                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5006                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18410                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1655224                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2832                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         88581                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2933                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         89330                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1347791                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3663804                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 77381                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           100225939                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            227298                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23234080                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16271017                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5320                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  49801                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  6534                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18287                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         195800                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       160651                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               356451                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              87582928                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22618546                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            843002                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1342238                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3674629                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 72016                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100198527                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            217276                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23221608                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16268601                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5368                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  49821                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  6531                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18410                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         194109                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       159104                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               353213                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              87568841                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22612881                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            841769                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9482483                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38365741                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15084551                       # Number of branches executed
-system.cpu.iew.exec_stores                   15747195                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.775024                       # Inst execution rate
-system.cpu.iew.wb_sent                       87227797                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      86838114                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33351220                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  43473707                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       9478846                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38355645                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15084252                       # Number of branches executed
+system.cpu.iew.exec_stores                   15742764                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.777239                       # Inst execution rate
+system.cpu.iew.wb_sent                       87220375                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      86831315                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33345689                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  43460058                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.759929                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.767158                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.762271                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.767272                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         8889589                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         8854011                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            311933                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     43331799                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.038703                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.791883                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            309865                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     43319454                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.039284                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.791171                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     20501224     47.31%     47.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7041698     16.25%     63.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3356099      7.75%     71.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2051116      4.73%     76.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2049317      4.73%     80.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1167384      2.69%     83.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1102119      2.54%     86.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       716210      1.65%     87.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5346632     12.34%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     20467997     47.25%     47.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7041159     16.25%     63.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3392321      7.83%     71.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2059744      4.75%     76.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2024611      4.67%     80.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1169642      2.70%     83.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1101426      2.54%     86.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       720003      1.66%     87.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5342551     12.33%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     43331799                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     43319454                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -571,229 +556,264 @@ system.cpu.commit.branches                   13754477                       # Nu
 system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5346632                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass      8748916      9.90%      9.90% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         44395413     50.25%     60.16% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           41101      0.05%     60.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     60.20% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd         113689      0.13%     60.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp             84      0.00%     60.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt         113640      0.13%     60.46% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult            50      0.00%     60.46% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv          37764      0.04%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     60.51% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        20276638     22.95%     83.46% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5342551                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    133898086                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195811124                       # The number of ROB writes
-system.cpu.timesIdled                           85852                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         4662226                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    133854244                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195734344                       # The number of ROB writes
+system.cpu.timesIdled                           83887                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         4610712                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.619936                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.619936                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.613069                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.613069                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                115913702                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57508814                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    249357                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   240037                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38036                       # number of misc regfile reads
+system.cpu.cpi                               0.619064                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.619064                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.615341                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.615341                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                115895624                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57505324                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    249507                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   239755                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38031                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1213726946                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         155524                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        155523                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       168929                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143419                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143419                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       186761                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       580053                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            766814                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5976320                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.throughput              1215125035                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         155398                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        155397                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       168938                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143416                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143416                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       186521                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       580044                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            766565                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5968640                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23967424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       29943744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus          29943744                       # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       29936064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          29936064                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      402865000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      402814000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     141399227                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     141250965                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     324564248                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     328598748                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             91332                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1925.493490                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13803368                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             93380                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            147.819319                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       19891128250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1925.493490                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.940182                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.940182                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             91212                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1925.511317                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13793650                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             93260                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            147.905318                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       19818994250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1925.511317                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.940191                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.940191                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1527                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          358                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1531                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          356                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          27912922                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         27912922                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     13803368                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13803368                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13803368                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13803368                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13803368                       # number of overall hits
-system.cpu.icache.overall_hits::total        13803368                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       106403                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        106403                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       106403                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         106403                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       106403                       # number of overall misses
-system.cpu.icache.overall_misses::total        106403                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2000796974                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2000796974                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2000796974                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2000796974                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2000796974                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2000796974                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13909771                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13909771                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13909771                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13909771                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13909771                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13909771                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007650                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007650                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007650                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007650                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007650                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007650                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18803.952652                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18803.952652                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18803.952652                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18803.952652                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18803.952652                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18803.952652                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          263                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          27892378                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27892378                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13793650                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13793650                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13793650                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13793650                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13793650                       # number of overall hits
+system.cpu.icache.overall_hits::total        13793650                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       105909                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        105909                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       105909                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         105909                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       105909                       # number of overall misses
+system.cpu.icache.overall_misses::total        105909                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1976186457                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1976186457                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1976186457                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1976186457                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1976186457                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1976186457                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13899559                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13899559                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13899559                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13899559                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13899559                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13899559                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007620                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007620                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.007620                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.007620                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.007620                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.007620                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18659.287284                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18659.287284                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18659.287284                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18659.287284                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18659.287284                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18659.287284                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          681                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.916667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    45.400000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        13022                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        13022                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        13022                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        13022                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        13022                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        13022                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        93381                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        93381                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        93381                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        93381                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        93381                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        93381                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1534559773                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1534559773                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1534559773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1534559773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1534559773                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1534559773                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006713                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006713                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006713                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006713                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006713                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006713                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16433.319123                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16433.319123                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16433.319123                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16433.319123                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16433.319123                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16433.319123                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12648                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        12648                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        12648                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        12648                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        12648                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        12648                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        93261                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        93261                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        93261                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        93261                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        93261                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        93261                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1519348535                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1519348535                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1519348535                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1519348535                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1519348535                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1519348535                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006710                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006710                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006710                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006710                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006710                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006710                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16291.360108                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16291.360108                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16291.360108                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16291.360108                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16291.360108                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16291.360108                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           132391                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30672.416469                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             159732                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164458                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.971263                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           132413                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30673.735606                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             159593                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164480                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.970288                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26335.603733                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2101.899695                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  2234.913041                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.803699                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064145                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.068204                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.936048                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 26310.881210                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2113.593767                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  2249.260629                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.802944                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064502                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.068642                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.936088                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32067                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1463                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        18089                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12275                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4           61                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1480                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        18009                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12342                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4           62                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978607                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4050853                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4050853                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        85734                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        34287                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         120021                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       168929                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168929                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12621                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12621                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        85734                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46908                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          132642                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        85734                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46908                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         132642                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         7647                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        27856                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        35503                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130798                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130798                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         7647                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158654                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        166301                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         7647                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158654                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       166301                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    583211250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2050433250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2633644500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13218958750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  13218958750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    583211250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  15269392000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  15852603250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    583211250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  15269392000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  15852603250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        93381                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        62143                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       155524                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       168929                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168929                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143419                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143419                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        93381                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       205562                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       298943                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        93381                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       205562                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       298943                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.081890                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.448256                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.228280                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911999                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911999                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.081890                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.771806                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.556297                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.081890                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.771806                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.556297                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76266.673205                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73608.315982                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74180.900206                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101063.921084                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101063.921084                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76266.673205                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96243.347158                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 95324.762028                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76266.673205                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96243.347158                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 95324.762028                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses          4049912                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4049912                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        85586                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        34280                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         119866                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       168938                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168938                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12623                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12623                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        85586                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46903                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          132489                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        85586                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        46903                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         132489                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         7675                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        27857                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        35532                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       130793                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       130793                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         7675                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       158650                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        166325                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         7675                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       158650                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       166325                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    569595000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2069573000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2639168000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13123369250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  13123369250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    569595000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  15192942250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  15762537250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    569595000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  15192942250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  15762537250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        93261                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        62137                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       155398                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       168938                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168938                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143416                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143416                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        93261                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       205553                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       298814                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        93261                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       205553                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       298814                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.082296                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.448316                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.228652                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911983                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911983                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.082296                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771820                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.556617                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.082296                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771820                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.556617                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74214.332248                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74292.745091                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74275.807723                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 100336.938903                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 100336.938903                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74214.332248                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95763.896943                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 94769.500977                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74214.332248                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95763.896943                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 94769.500977                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -802,155 +822,155 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114017                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114017                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7647                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27856                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        35503                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130798                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130798                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7647                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158654                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166301                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7647                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158654                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166301                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    486616750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1695026750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2181643500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11619308250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11619308250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    486616750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13314335000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  13800951750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    486616750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13314335000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  13800951750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.081890                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.448256                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.228280                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911999                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911999                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.081890                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771806                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.556297                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.081890                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771806                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.556297                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63634.987577                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60849.610497                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61449.553559                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88833.990199                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88833.990199                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63634.987577                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83920.575592                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82987.785702                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63634.987577                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83920.575592                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82987.785702                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       114011                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114011                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7675                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27857                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        35532                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130793                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       130793                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         7675                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158650                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166325                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         7675                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158650                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       166325                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    472615500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1714074500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2186690000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11513357750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11513357750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    472615500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13227432250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  13700047750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    472615500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13227432250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  13700047750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.082296                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.448316                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.228652                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911983                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911983                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.082296                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771820                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.556617                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.082296                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771820                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.556617                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61578.566775                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61531.195032                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61541.427446                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88027.323710                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88027.323710                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61578.566775                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83374.927513                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82369.143244                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61578.566775                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83374.927513                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82369.143244                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            201466                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4073.410780                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34191132                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            205562                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            166.330022                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         225470250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4073.410780                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.994485                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.994485                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            201457                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4073.584909                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34188310                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            205553                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            166.323576                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         223833000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4073.584909                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.994528                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.994528                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1081                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2933                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1093                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2926                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          71201646                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         71201646                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20617040                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20617040                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13574040                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13574040                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           52                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           52                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      34191080                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34191080                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34191080                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34191080                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       267573                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        267573                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1039337                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1039337                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1306910                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1306910                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1306910                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1306910                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  15791609498                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  15791609498                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  85266584825                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  85266584825                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 101058194323                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 101058194323                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 101058194323                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 101058194323                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20884613                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20884613                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          71195917                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         71195917                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20614139                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20614139                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13574109                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13574109                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           62                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           62                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      34188248                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34188248                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34188248                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34188248                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       267604                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        267604                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1039268                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1039268                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1306872                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1306872                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1306872                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1306872                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  16043231998                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  16043231998                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  85247557215                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  85247557215                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 101290789213                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 101290789213                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 101290789213                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 101290789213                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20881743                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20881743                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           52                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           52                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35497990                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35497990                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35497990                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35497990                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012812                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012812                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071122                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.071122                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036816                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036816                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036816                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036816                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59017.948365                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59017.948365                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82039.400911                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 82039.400911                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 77326.054834                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 77326.054834                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 77326.054834                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 77326.054834                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      4861037                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           62                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           62                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35495120                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35495120                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35495120                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35495120                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012815                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012815                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071118                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.071118                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036818                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036818                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036818                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036818                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59951.390854                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 59951.390854                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82026.539078                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 82026.539078                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 77506.281574                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 77506.281574                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 77506.281574                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 77506.281574                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      4834178                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          131                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            111685                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            104486                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.524529                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.266275                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          131                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168929                       # number of writebacks
-system.cpu.dcache.writebacks::total            168929                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       205428                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       205428                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       895920                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       895920                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1101348                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1101348                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1101348                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1101348                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62145                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        62145                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143417                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143417                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205562                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205562                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205562                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205562                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2457360502                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2457360502                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13489619744                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  13489619744                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15946980246                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15946980246                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15946980246                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15946980246                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks       168938                       # number of writebacks
+system.cpu.dcache.writebacks::total            168938                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       205464                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       205464                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       895855                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       895855                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1101319                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1101319                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1101319                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1101319                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62140                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62140                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143413                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143413                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205553                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205553                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205553                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205553                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2476433502                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2476433502                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13394078745                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  13394078745                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15870512247                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15870512247                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15870512247                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15870512247                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002976                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002976                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009814                       # mshr miss rate for WriteReq accesses
@@ -959,14 +979,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005791
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005791                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005791                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005791                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39542.368686                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39542.368686                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94058.722076                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94058.722076                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77577.471741                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77577.471741                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77577.471741                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77577.471741                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39852.486353                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39852.486353                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93395.150684                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93395.150684                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77208.857312                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77208.857312                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77208.857312                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77208.857312                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 9c79d9678..36b629088 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.044221                       # Nu
 sim_ticks                                 44221003000                       # Number of ticks simulated
 final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1834941                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1834940                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              918522034                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 279452                       # Number of bytes of host memory used
-host_seconds                                    48.14                       # Real time elapsed on the host
+host_inst_rate                                2624099                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2624098                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1313553455                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264796                       # Number of bytes of host memory used
+host_seconds                                    33.67                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -95,5 +95,40 @@ system.cpu.num_busy_cycles                   88442007                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          13754477                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               8748916      9.89%      9.89% # Class of executed instruction
+system.cpu.op_class::IntAlu                  44395414     50.20%     60.09% # Class of executed instruction
+system.cpu.op_class::IntMult                    41101      0.05%     60.14% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     60.14% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  113689      0.13%     60.27% # Class of executed instruction
+system.cpu.op_class::FloatCmp                      84      0.00%     60.27% # Class of executed instruction
+system.cpu.op_class::FloatCvt                  113640      0.13%     60.40% # Class of executed instruction
+system.cpu.op_class::FloatMult                     50      0.00%     60.40% # Class of executed instruction
+system.cpu.op_class::FloatDiv                   37764      0.04%     60.44% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::MemRead                 20366786     23.03%     83.47% # Class of executed instruction
+system.cpu.op_class::MemWrite                14620629     16.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   88438073                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 51324a43d..005dec492 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.133635                       # Nu
 sim_ticks                                133634727000                       # Number of ticks simulated
 final_tick                               133634727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 990858                       # Simulator instruction rate (inst/s)
-host_op_rate                                   990858                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1498890062                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 288280                       # Number of bytes of host memory used
-host_seconds                                    89.16                       # Real time elapsed on the host
+host_inst_rate                                1051168                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1051168                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1590122468                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273520                       # Number of bytes of host memory used
+host_seconds                                    84.04                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -109,6 +109,41 @@ system.cpu.num_busy_cycles                  267269454                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          13754477                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               8748916      9.89%      9.89% # Class of executed instruction
+system.cpu.op_class::IntAlu                  44395414     50.20%     60.09% # Class of executed instruction
+system.cpu.op_class::IntMult                    41101      0.05%     60.14% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     60.14% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  113689      0.13%     60.27% # Class of executed instruction
+system.cpu.op_class::FloatCmp                      84      0.00%     60.27% # Class of executed instruction
+system.cpu.op_class::FloatCvt                  113640      0.13%     60.40% # Class of executed instruction
+system.cpu.op_class::FloatMult                     50      0.00%     60.40% # Class of executed instruction
+system.cpu.op_class::FloatDiv                   37764      0.04%     60.44% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     60.44% # Class of executed instruction
+system.cpu.op_class::MemRead                 20366786     23.03%     83.47% # Class of executed instruction
+system.cpu.op_class::MemWrite                14620629     16.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   88438073                       # Class of executed instruction
 system.cpu.icache.tags.replacements             74391                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1871.686406                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            88361638                       # Total number of references to valid blocks.
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index e2e70aeb1..5913e1c51 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.026596                       # Number of seconds simulated
-sim_ticks                                 26596403000                       # Number of ticks simulated
-final_tick                                26596403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.026655                       # Number of seconds simulated
+sim_ticks                                 26655046000                       # Number of ticks simulated
+final_tick                                26655046000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 110554                       # Simulator instruction rate (inst/s)
-host_op_rate                                   156889                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               41466984                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 321816                       # Number of bytes of host memory used
-host_seconds                                   641.39                       # Real time elapsed on the host
+host_inst_rate                                 108502                       # Simulator instruction rate (inst/s)
+host_op_rate                                   153979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               40787374                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 322284                       # Number of bytes of host memory used
+host_seconds                                   653.51                       # Real time elapsed on the host
 sim_insts                                    70907629                       # Number of instructions simulated
 sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            297984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7942976                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8240960                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       297984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          297984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5372480                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5372480                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               4656                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             124109                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128765                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           83945                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                83945                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             11203921                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            298648505                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               309852426                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        11203921                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           11203921                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         202000248                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              202000248                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         202000248                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            11203921                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           298648505                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              511852674                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128766                       # Number of read requests accepted
-system.physmem.writeReqs                        83945                       # Number of write requests accepted
-system.physmem.readBursts                      128766                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      83945                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8240704                       # Total number of bytes read from DRAM
+system.physmem.bytes_read::cpu.inst            298176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7943424                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8241600                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       298176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          298176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5372544                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5372544                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4659                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             124116                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                128775                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           83946                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                83946                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             11186475                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            298008265                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               309194739                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        11186475                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           11186475                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         201558234                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              201558234                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         201558234                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            11186475                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           298008265                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              510752973                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128776                       # Number of read requests accepted
+system.physmem.writeReqs                        83946                       # Number of write requests accepted
+system.physmem.readBursts                      128776                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      83946                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8241344                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5371136                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8241024                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5372480                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   5371328                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8241664                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5372544                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            300                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8143                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8388                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8255                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8165                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8298                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                8451                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8084                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7964                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8055                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7611                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7782                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            320                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                8145                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8395                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8248                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8167                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8288                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                8447                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8087                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7963                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8065                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7608                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7787                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               7815                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               7881                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7884                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7976                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8009                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5177                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5289                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               7882                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7885                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7978                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8011                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5180                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                5377                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5291                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5157                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5267                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5201                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5199                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                5049                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                5030                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5089                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5091                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               5246                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               5144                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               5342                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5452                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               5225                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     26596386500                       # Total gap between requests
+system.physmem.totGap                     26655030500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128766                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128776                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  83945                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     71874                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     54925                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1900                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        55                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  83946                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     74138                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     53140                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1433                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        52                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,45 +144,45 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      840                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3768                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5492                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6272                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5625                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2900                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      953                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      409                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      643                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5237                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5798                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6000                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
@@ -193,109 +193,98 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        29627                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      410.695649                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     253.351666                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     359.831379                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7793     26.30%     26.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         6034     20.37%     46.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3130     10.56%     57.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2203      7.44%     64.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2053      6.93%     71.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1365      4.61%     76.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1045      3.53%     79.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1191      4.02%     83.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4813     16.25%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          29627                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5084                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.322974                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      394.325536                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5082     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        37804                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      360.014390                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     216.175335                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     343.156707                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12089     31.98%     31.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         7874     20.83%     52.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3781     10.00%     62.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2728      7.22%     70.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2397      6.34%     76.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1617      4.28%     80.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1220      3.23%     83.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1066      2.82%     86.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5032     13.31%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          37804                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5144                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.030132                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      392.032521                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5142     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5084                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5084                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.507474                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.421096                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.063173                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4555     89.59%     89.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 21      0.41%     90.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 58      1.14%     91.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                170      3.34%     94.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                125      2.46%     96.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 57      1.12%     98.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 23      0.45%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 15      0.30%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 10      0.20%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  6      0.12%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  5      0.10%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  5      0.10%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  4      0.08%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  2      0.04%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.08%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  2      0.04%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  1      0.02%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.02%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                 13      0.26%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  3      0.06%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5084                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2537399000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4590111500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    643805000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1408907500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       19706.27                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    10942.04                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            5144                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5144                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.315513                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.292869                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.917660                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4492     87.33%     87.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  6      0.12%     87.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                431      8.38%     95.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                161      3.13%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 33      0.64%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 11      0.21%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  6      0.12%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5144                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2471536000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4885992250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    643855000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19193.27                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  35648.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         309.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         201.95                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      309.85                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      202.00                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37943.27                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         309.19                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         201.51                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      309.20                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      201.56                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           4.00                       # Data bus utilization in percentage
+system.physmem.busUtil                           3.99                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.42                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.58                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.36                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.09                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     112537                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     62593                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.40                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.56                       # Row buffer hit rate for writes
-system.physmem.avgGap                       125035.31                       # Average gap between requests
-system.physmem.pageHitRate                      82.33                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              11.63                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    511852674                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               26511                       # Transaction distribution
-system.membus.trans_dist::ReadResp              26510                       # Transaction distribution
-system.membus.trans_dist::Writeback             83945                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              300                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             300                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102255                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102255                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 342076                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13613440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            13613440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               13613440                       # Total data (bytes)
+system.physmem.busUtilWrite                      1.57                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.35                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112800                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     62083                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.60                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.96                       # Row buffer hit rate for writes
+system.physmem.avgGap                       125304.53                       # Average gap between requests
+system.physmem.pageHitRate                      82.21                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      11333884750                       # Time in different power states
+system.physmem.memoryStateTime::REF         889980000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       14428773750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    510752973                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               26520                       # Transaction distribution
+system.membus.trans_dist::ReadResp              26519                       # Transaction distribution
+system.membus.trans_dist::Writeback             83946                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              320                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             320                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102256                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102256                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342137                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 342137                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13614144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            13614144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               13614144                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           934794000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           932451500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1201882201                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1211794930                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              4.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                16626299                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          12761376                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            603542                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10553987                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7772041                       # Number of BTB hits
+system.cpu.branchPred.lookups                16636502                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          12767541                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            605249                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             10577266                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7776939                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             73.640805                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1823891                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             112970                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             73.525039                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1824082                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             113194                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -381,136 +370,136 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         53192807                       # number of cpu cycles simulated
+system.cpu.numCycles                         53310093                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12548027                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       85225985                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16626299                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9595932                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      21195811                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2371567                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               10764095                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  172                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           524                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           23                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11679981                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                179230                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           46249849                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.580108                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.332376                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           12544266                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       85245132                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16636502                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9601021                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      21203621                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2373453                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               10826846                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   66                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           346                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           55                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  11685368                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                181941                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           46316681                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.577051                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.331362                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 25074842     54.22%     54.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2134843      4.62%     58.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1965334      4.25%     63.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2045724      4.42%     67.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1467866      3.17%     70.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1377638      2.98%     73.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   956719      2.07%     75.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1188096      2.57%     78.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 10038787     21.71%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 25133357     54.26%     54.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2139356      4.62%     58.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1964088      4.24%     63.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2042720      4.41%     67.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1470632      3.18%     70.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1380684      2.98%     73.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   958438      2.07%     75.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1191046      2.57%     78.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 10036360     21.67%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             46249849                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.312567                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.602209                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 14635842                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9109376                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19493309                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1372783                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1638539                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3331010                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                104505                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              116880506                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                361697                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1638539                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 16346771                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 2652791                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles        1020533                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  19105290                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5485925                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              114999580                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   152                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  17445                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4623062                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              183                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           115318587                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             529932404                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        476522297                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              2751                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             46316681                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.312070                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.599043                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 14641724                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9163742                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19491129                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1382035                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1638051                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3333190                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                105248                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              116897409                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                363517                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1638051                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 16359930                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 2678860                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles        1013546                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  19105164                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5521130                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              115000815                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   184                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  16720                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4660350                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              282                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           115331621                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             529914525                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        476510410                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2776                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 16185915                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              20374                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          20369                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13024660                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             29615928                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            22451967                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3877153                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          4417845                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  111572377                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               35991                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 107273861                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            274045                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        10831021                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     25918238                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2205                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      46249849                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.319442                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.990414                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 16198949                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              20436                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          20434                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13095384                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29625138                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            22434042                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3869725                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          4362550                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  111565619                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               36058                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 107262004                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            275498                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        10829281                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     25946611                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           2272                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      46316681                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.315840                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.990470                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            10978806     23.74%     23.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             8116860     17.55%     41.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7434269     16.07%     57.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7097763     15.35%     72.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5421519     11.72%     84.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3913580      8.46%     92.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1842525      3.98%     96.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              870168      1.88%     98.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              574359      1.24%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            11030019     23.81%     23.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             8138803     17.57%     41.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7430883     16.04%     57.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7110857     15.35%     72.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5417654     11.70%     84.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3891349      8.40%     92.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1848302      3.99%     96.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              878821      1.90%     98.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              569993      1.23%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        46249849                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        46316681                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  113368      4.58%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1353818     54.73%     59.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1006223     40.68%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  113827      4.59%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1360293     54.84%     59.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1006288     40.57%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              56655592     52.81%     52.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                91505      0.09%     52.90% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              56646184     52.81%     52.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                91539      0.09%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 217      0.00%     52.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 222      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.90% # Type of FU issued
@@ -536,84 +525,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.90% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             28893939     26.93%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21632601     20.17%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             28903042     26.95%     79.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21621010     20.16%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              107273861                       # Type of FU issued
-system.cpu.iq.rate                           2.016699                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2473411                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023057                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          263544444                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         122467509                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    105589962                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 583                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                918                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          177                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              109746981                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     291                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          2178933                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              107262004                       # Type of FU issued
+system.cpu.iq.rate                           2.012039                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2480410                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023125                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          263595997                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         122458930                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    105571537                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 600                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                932                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          176                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              109742111                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     303                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          2179776                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2308820                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6717                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        29962                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1896229                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2318030                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6495                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        30041                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1878304                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           29                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           670                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads           30                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           708                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1638539                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1135526                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 46796                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           111618146                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            297287                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              29615928                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             22451967                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              20071                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   6522                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  5186                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          29962                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         392730                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       181164                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               573894                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             106245086                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              28594669                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1028775                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1638051                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1126663                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 45667                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           111611483                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            295320                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29625138                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             22434042                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              20138                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   6203                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  5120                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          30041                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         394287                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       181285                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               575572                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             106232062                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              28604336                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1029942                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          9778                       # number of nop insts executed
-system.cpu.iew.exec_refs                     49940992                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14602318                       # Number of branches executed
-system.cpu.iew.exec_stores                   21346323                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.997358                       # Inst execution rate
-system.cpu.iew.wb_sent                      105809508                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     105590139                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  53305824                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 103866304                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          9806                       # number of nop insts executed
+system.cpu.iew.exec_refs                     49939736                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14601830                       # Number of branches executed
+system.cpu.iew.exec_stores                   21335400                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.992720                       # Inst execution rate
+system.cpu.iew.wb_sent                      105794271                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     105571713                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  53289529                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 103696689                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.985045                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.513216                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.980333                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.513898                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        10986690                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        10980049                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            500884                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     44611310                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.255760                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.762475                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            501819                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     44678630                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.252362                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.761359                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     15517142     34.78%     34.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11686207     26.20%     60.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3450926      7.74%     68.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2867812      6.43%     75.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1872959      4.20%     79.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1945129      4.36%     83.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       689747      1.55%     85.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       566134      1.27%     86.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6015254     13.48%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     15558775     34.82%     34.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11701818     26.19%     61.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3471869      7.77%     68.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2879306      6.44%     75.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1869514      4.18%     79.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1922443      4.30%     83.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       688922      1.54%     85.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       562713      1.26%     86.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6023270     13.48%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     44611310                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     44678630                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
 system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -624,243 +613,278 @@ system.cpu.commit.branches                   13741485                       # Nu
 system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6015254                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         52689456     52.36%     52.36% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           80119      0.08%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.44% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        27307108     27.14%     79.57% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20555738     20.43%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total         100632428                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               6023270                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    150189875                       # The number of ROB reads
-system.cpu.rob.rob_writes                   224886049                       # The number of ROB writes
-system.cpu.timesIdled                           80066                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         6942958                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    150242538                       # The number of ROB reads
+system.cpu.rob.rob_writes                   224871982                       # The number of ROB writes
+system.cpu.timesIdled                           79510                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6993412                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
 system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              70907629                       # Number of Instructions Simulated
-system.cpu.cpi                               0.750170                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.750170                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.333030                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.333030                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                511686083                       # number of integer regfile reads
-system.cpu.int_regfile_writes               103364033                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       870                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      762                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                49348247                       # number of misc regfile reads
+system.cpu.cpi                               0.751825                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.751825                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.330098                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.330098                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                511631717                       # number of integer regfile reads
+system.cpu.int_regfile_writes               103353872                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       846                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      710                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                49341635                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               778162370                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          87191                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         87190                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       129156                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          314                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          314                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107034                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107034                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        63123                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454609                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            517732                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2003904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18660352                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       20664256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus          20664256                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        32064                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      291006496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               775139386                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          86625                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         86624                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       129165                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          335                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          335                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       107045                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       107045                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        62039                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454624                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            516663                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1968896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18659776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       20628672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          20628672                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus        32704                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      290752497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      48441979                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      47657477                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     259878236                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     267144007                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             29471                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1806.055358                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            11644351                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             31508                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            369.568078                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             28917                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1807.865134                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            11650266                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             30950                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            376.422165                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1806.055358                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.881863                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.881863                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         2037                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1807.865134                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.882747                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.882747                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2033                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1253                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          681                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.994629                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          23391772                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         23391772                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     11644361                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        11644361                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      11644361                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         11644361                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     11644361                       # number of overall hits
-system.cpu.icache.overall_hits::total        11644361                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        35619                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         35619                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        35619                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          35619                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        35619                       # number of overall misses
-system.cpu.icache.overall_misses::total         35619                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    813918226                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    813918226                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    813918226                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    813918226                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    813918226                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    813918226                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11679980                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11679980                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11679980                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11679980                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11679980                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11679980                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003050                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.003050                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.003050                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.003050                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.003050                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.003050                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22850.675931                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22850.675931                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22850.675931                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22850.675931                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22850.675931                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22850.675931                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1148                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1259                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          672                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.992676                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          23402009                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         23402009                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     11650274                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        11650274                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      11650274                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         11650274                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     11650274                       # number of overall hits
+system.cpu.icache.overall_hits::total        11650274                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        35093                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         35093                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        35093                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          35093                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        35093                       # number of overall misses
+system.cpu.icache.overall_misses::total         35093                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    796173972                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    796173972                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    796173972                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    796173972                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    796173972                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    796173972                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     11685367                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     11685367                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     11685367                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     11685367                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     11685367                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     11685367                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003003                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.003003                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.003003                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.003003                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.003003                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.003003                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22687.543727                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22687.543727                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22687.543727                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22687.543727                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22687.543727                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22687.543727                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1584                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                22                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    52.181818                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    60.923077                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3807                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3807                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3807                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3807                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3807                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3807                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31812                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        31812                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        31812                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        31812                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        31812                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        31812                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    661574021                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    661574021                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    661574021                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    661574021                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    661574021                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    661574021                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002724                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002724                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002724                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.002724                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002724                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.002724                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20796.366811                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20796.366811                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20796.366811                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20796.366811                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20796.366811                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20796.366811                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3818                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3818                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3818                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3818                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3818                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3818                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31275                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        31275                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        31275                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        31275                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        31275                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        31275                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    647196022                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    647196022                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    647196022                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    647196022                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    647196022                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    647196022                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002676                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002676                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002676                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.002676                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002676                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.002676                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.717730                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.717730                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.717730                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.717730                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.717730                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.717730                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            95635                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29857.974256                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              88990                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           126748                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.702102                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            95645                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29867.639929                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              88414                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           126758                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.697502                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26666.144476                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1368.316766                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1823.513014                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.813786                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041758                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.055649                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.911193                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 26665.630532                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1369.813019                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1832.196377                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.813770                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041803                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.055914                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.911488                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        31113                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1837                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20828                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7917                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1847                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20513                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8219                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4          394                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949493                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          2819349                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         2819349                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        26638                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        33464                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          60102                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       129156                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       129156                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           14                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           14                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         4779                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4779                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        26638                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        38243                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           64881                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        26638                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        38243                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          64881                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         4673                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        21915                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        26588                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          300                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          300                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       102255                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       102255                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         4673                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       124170                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        128843                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         4673                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       124170                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       128843                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    362632500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1783611000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2146243500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23499                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total        23499                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8210815250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8210815250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    362632500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   9994426250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10357058750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    362632500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   9994426250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10357058750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        31311                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        55379                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        86690                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       129156                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       129156                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          314                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          314                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       107034                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       107034                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        31311                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       162413                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       193724                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        31311                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       162413                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       193724                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.149245                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.395728                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.306702                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.955414                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.955414                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955351                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955351                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.149245                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.764532                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.665085                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149245                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.764532                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.665085                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77601.647764                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81387.679671                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 80722.261923                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    78.330000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    78.330000                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80297.445113                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80297.445113                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77601.647764                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80489.862688                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80385.110173                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77601.647764                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80489.862688                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80385.110173                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses          2815092                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         2815092                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        26089                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        33429                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          59518                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       129165                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       129165                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           16                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           16                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4788                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         4788                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        26089                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        38217                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           64306                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        26089                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        38217                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          64306                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         4675                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        21921                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        26596                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          319                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          319                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       102257                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       102257                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         4675                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       124178                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        128853                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         4675                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       124178                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       128853                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    354274500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1813961250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2168235750                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        22999                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total        22999                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8348408999                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8348408999                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    354274500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10162370249                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10516644749                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    354274500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10162370249                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10516644749                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        30764                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        55350                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        86114                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       129165                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       129165                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          335                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          335                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       107045                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       107045                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        30764                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       162395                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       193159                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        30764                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       162395                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       193159                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.151963                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.396043                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.308846                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.952239                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.952239                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955271                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955271                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.151963                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.764666                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.667083                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.151963                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.764666                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.667083                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75780.641711                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82749.931572                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 81524.881561                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    72.097179                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    72.097179                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81641.442630                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81641.442630                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75780.641711                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81837.122912                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81617.383755                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75780.641711                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81837.122912                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81617.383755                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -869,202 +893,210 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        83945                       # number of writebacks
-system.cpu.l2cache.writebacks::total            83945                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           17                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks        83946                       # number of writebacks
+system.cpu.l2cache.writebacks::total            83946                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           16                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           60                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           17                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           76                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           16                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           60                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           77                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           17                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           76                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           16                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           60                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           77                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4656                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21855                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        26511                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          300                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          300                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102255                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102255                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         4656                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       124110                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       128766                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         4656                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       124110                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       128766                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    303015250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1507731500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1810746750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3014299                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3014299                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6936413750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6936413750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    303015250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8444145250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8747160500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    303015250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8444145250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8747160500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.148702                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394644                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.305814                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.955414                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.955414                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955351                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955351                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.148702                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764163                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.664688                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.148702                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764163                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.664688                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65080.594931                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68987.943262                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68301.714383                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10047.663333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10047.663333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67834.470197                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67834.470197                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65080.594931                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68037.589638                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67930.668810                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65080.594931                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68037.589638                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67930.668810                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::total           76                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4659                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21861                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        26520                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          319                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          319                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102257                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102257                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         4659                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       124118                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       128777                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         4659                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       124118                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       128777                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    294952000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1536285750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1831237750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3196819                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3196819                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7058409501                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7058409501                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    294952000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8594695251                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8889647251                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    294952000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8594695251                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8889647251                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.151443                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394959                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.307964                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.952239                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.952239                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955271                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955271                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.151443                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764297                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.666689                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.151443                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764297                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.666689                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63308.006010                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70275.181831                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69051.197210                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10021.376176                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10021.376176                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69026.174257                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69026.174257                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63308.006010                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69246.162934                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69031.327419                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63308.006010                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69246.162934                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69031.327419                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            158316                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4068.473281                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            44361466                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            162412                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            273.141554                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         367394250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4068.473281                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993280                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993280                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            158298                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.579596                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            44367951                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            162394                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            273.211763                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         366659250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.579596                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993306                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993306                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1757                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2276                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1762                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2265                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          92298894                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         92298894                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     26061245                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        26061245                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18267715                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18267715                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15989                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15989                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          92310952                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         92310952                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     26067775                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        26067775                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18267649                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18267649                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15993                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15993                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      44328960                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         44328960                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     44328960                       # number of overall hits
-system.cpu.dcache.overall_hits::total        44328960                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       125143                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        125143                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1582186                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1582186                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           44                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           44                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1707329                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1707329                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1707329                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1707329                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5010352449                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5010352449                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 122380602729                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 122380602729                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       944750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       944750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 127390955178                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 127390955178                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 127390955178                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 127390955178                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     26186388                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     26186388                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      44335424                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         44335424                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     44335424                       # number of overall hits
+system.cpu.dcache.overall_hits::total        44335424                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       124650                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        124650                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1582252                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1582252                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           41                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           41                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1706902                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1706902                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1706902                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1706902                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5082447470                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5082447470                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 124553146004                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 124553146004                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       917250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       917250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 129635593474                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 129635593474                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 129635593474                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 129635593474                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     26192425                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     26192425                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16033                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        16033                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16034                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        16034                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     46036289                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     46036289                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     46036289                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     46036289                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004779                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004779                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079708                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.079708                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002744                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002744                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037087                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037087                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037087                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037087                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40037.017244                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40037.017244                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77349.061823                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 77349.061823                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21471.590909                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21471.590909                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 74614.181085                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 74614.181085                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 74614.181085                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 74614.181085                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         4179                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1300                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               140                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              15                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    29.850000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    86.666667                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     46042326                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     46042326                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     46042326                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     46042326                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004759                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004759                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079711                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.079711                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002557                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002557                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037072                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037072                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037072                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037072                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40773.746249                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40773.746249                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78718.905714                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 78718.905714                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22371.951220                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22371.951220                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 75947.883050                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 75947.883050                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 75947.883050                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 75947.883050                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         3831                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1303                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               134                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              16                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    28.589552                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    81.437500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       129156                       # number of writebacks
-system.cpu.dcache.writebacks::total            129156                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69730                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        69730                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1474872                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1474872                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           44                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           44                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1544602                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1544602                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1544602                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1544602                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55413                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        55413                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107314                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107314                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       162727                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       162727                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       162727                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       162727                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2176479313                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2176479313                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8375757941                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8375757941                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10552237254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10552237254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10552237254                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10552237254                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002116                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002116                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005406                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005406                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003535                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003535                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003535                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003535                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39277.413477                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39277.413477                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78049.070401                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78049.070401                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64846.259404                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 64846.259404                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64846.259404                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 64846.259404                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       129165                       # number of writebacks
+system.cpu.dcache.writebacks::total            129165                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69269                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        69269                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1474904                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1474904                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           40                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           40                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1544173                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1544173                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1544173                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1544173                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55381                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        55381                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107348                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107348                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       162729                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       162729                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       162729                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       162729                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2206437312                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2206437312                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8512084920                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8512084920                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        11500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        11500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10718522232                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10718522232                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10718522232                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10718522232                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002114                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002114                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005408                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005408                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.000062                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.000062                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003534                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003534                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003534                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003534                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39841.052202                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39841.052202                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79294.303760                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79294.303760                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        11500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        11500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65867.314566                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65867.314566                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65867.314566                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65867.314566                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 987b2c223..d5f8b245c 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.053932                       # Nu
 sim_ticks                                 53932157000                       # Number of ticks simulated
 final_tick                                53932157000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1050888                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1491308                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              799239680                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 322556                       # Number of bytes of host memory used
-host_seconds                                    67.48                       # Real time elapsed on the host
+host_inst_rate                                1371353                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1946078                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1042965622                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308436                       # Number of bytes of host memory used
+host_seconds                                    51.71                       # Real time elapsed on the host
 sim_insts                                    70913181                       # Number of instructions simulated
 sim_ops                                     100632428                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,5 +147,40 @@ system.cpu.num_busy_cycles                  107864315                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          13741485                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  52691402     52.36%     52.36% # Class of executed instruction
+system.cpu.op_class::IntMult                    80119      0.08%     52.44% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  7      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::MemRead                 27307108     27.13%     79.57% # Class of executed instruction
+system.cpu.op_class::MemWrite                20555739     20.43%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  100634375                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index fecdc24fb..247ca051b 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.132689                       # Nu
 sim_ticks                                132689045000                       # Number of ticks simulated
 final_tick                               132689045000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 552138                       # Simulator instruction rate (inst/s)
-host_op_rate                                   782946                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1041052140                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 332284                       # Number of bytes of host memory used
-host_seconds                                   127.46                       # Real time elapsed on the host
+host_inst_rate                                 682193                       # Simulator instruction rate (inst/s)
+host_op_rate                                   967367                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1286269606                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318200                       # Number of bytes of host memory used
+host_seconds                                   103.16                       # Real time elapsed on the host
 sim_insts                                    70373628                       # Number of instructions simulated
 sim_ops                                      99791654                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -161,6 +161,41 @@ system.cpu.num_busy_cycles                  265378090                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          13741485                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  52691402     52.36%     52.36% # Class of executed instruction
+system.cpu.op_class::IntMult                    80119      0.08%     52.44% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  7      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     52.44% # Class of executed instruction
+system.cpu.op_class::MemRead                 27307108     27.13%     79.57% # Class of executed instruction
+system.cpu.op_class::MemWrite                20555739     20.43%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  100634375                       # Class of executed instruction
 system.cpu.icache.tags.replacements             16890                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1736.497265                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            78126161                       # Total number of references to valid blocks.
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index e0d531dce..56e5d21a1 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.068149                       # Nu
 sim_ticks                                 68148672000                       # Number of ticks simulated
 final_tick                                68148672000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1921737                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1946620                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              974440461                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 287756                       # Number of bytes of host memory used
-host_seconds                                    69.94                       # Real time elapsed on the host
+host_inst_rate                                2339703                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2369997                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1186374997                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273296                       # Number of bytes of host memory used
+host_seconds                                    57.44                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -65,5 +65,40 @@ system.cpu.num_busy_cycles                  136297345                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          12719095                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              11445042      8.40%      8.40% # Class of executed instruction
+system.cpu.op_class::IntAlu                  66342070     48.68%     57.07% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     57.07% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     57.07% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  325584      0.24%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::MemRead                 37296721     27.36%     84.68% # Class of executed instruction
+system.cpu.op_class::MemWrite                20884381     15.32%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  136293798                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 43a817a48..736480ca6 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.202242                       # Nu
 sim_ticks                                202242260000                       # Number of ticks simulated
 final_tick                               202242260000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 840358                       # Simulator instruction rate (inst/s)
-host_op_rate                                   851239                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1264562009                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296592                       # Number of bytes of host memory used
-host_seconds                                   159.93                       # Real time elapsed on the host
+host_inst_rate                                1069571                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1083420                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1609480248                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282012                       # Number of bytes of host memory used
+host_seconds                                   125.66                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -77,6 +77,41 @@ system.cpu.num_busy_cycles                  404484520                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          12719095                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              11445042      8.40%      8.40% # Class of executed instruction
+system.cpu.op_class::IntAlu                  66342070     48.68%     57.07% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     57.07% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     57.07% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  325584      0.24%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::MemRead                 37296721     27.36%     84.68% # Class of executed instruction
+system.cpu.op_class::MemWrite                20884381     15.32%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  136293798                       # Class of executed instruction
 system.cpu.icache.tags.replacements            184976                       # number of replacements
 system.cpu.icache.tags.tagsinuse          2004.815325                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           134366547                       # Total number of references to valid blocks.
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index f20aedd28..df378c8bf 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.007337                       # Number of seconds simulated
-sim_ticks                                1007336591500                       # Number of ticks simulated
-final_tick                               1007336591500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.005768                       # Number of seconds simulated
+sim_ticks                                1005767806500                       # Number of ticks simulated
+final_tick                               1005767806500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 109896                       # Simulator instruction rate (inst/s)
-host_op_rate                                   109896                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               60832901                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265436                       # Number of bytes of host memory used
-host_seconds                                 16559.08                       # Real time elapsed on the host
+host_inst_rate                                 106626                       # Simulator instruction rate (inst/s)
+host_op_rate                                   106626                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               58930745                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266468                       # Number of bytes of host memory used
+host_seconds                                 17066.95                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             54976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125365056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125420032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         125365120                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125420096                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        54976                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           54976                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65155520                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65155520                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     65155584                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65155584                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                859                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1958829                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1959688                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1018055                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1018055                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                54576                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            124452002                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               124506578                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           54576                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              54576                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          64680982                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               64680982                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          64680982                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               54576                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           124452002                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              189187560                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1959688                       # Number of read requests accepted
-system.physmem.writeReqs                      1018055                       # Number of write requests accepted
-system.physmem.readBursts                     1959688                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1018055                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125336064                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     83968                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65153920                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125420032                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65155520                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1312                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu.data            1958830                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1959689                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1018056                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1018056                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                54661                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            124646185                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               124700846                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           54661                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              54661                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          64781934                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               64781934                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          64781934                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               54661                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           124646185                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              189482780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1959689                       # Number of read requests accepted
+system.physmem.writeReqs                      1018056                       # Number of write requests accepted
+system.physmem.readBursts                     1959689                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1018056                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125339392                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     80704                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65154112                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125420096                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65155584                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1261                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118685                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114026                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116162                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117671                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117731                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117464                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119807                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124441                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126920                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118688                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              114039                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116164                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117666                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117733                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117466                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119809                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124448                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126913                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              130015                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128574                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130216                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             125899                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125145                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122505                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123115                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128579                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130223                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             125906                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125163                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122509                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123107                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               61223                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               61467                       # Per bank write bursts
 system.physmem.perBankWrBursts::2               60558                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61215                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61216                       # Per bank write bursts
 system.physmem.perBankWrBursts::4               61647                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63083                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64136                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63085                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64137                       # Per bank write bursts
 system.physmem.perBankWrBursts::7               65614                       # Per bank write bursts
 system.physmem.perBankWrBursts::8               65332                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               65769                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65294                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65608                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64146                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64202                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64550                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               65770                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65297                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65611                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64139                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64200                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64551                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              64186                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1007336518500                       # Total gap between requests
+system.physmem.totGap                    1005767733500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1959688                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1959689                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1018055                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1664981                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    198590                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     70959                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     23846                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1018056                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1667897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    193105                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     75870                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     21555                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,76 +144,76 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26939                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    28117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    34916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    48946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    53936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    56821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    58079                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    58536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    58949                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    59504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    64559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    64811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    64584                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    72712                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    62778                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    60810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                    14814                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     4880                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1773                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    29926                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    31516                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    51008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60493                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60664                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    60587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    60540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    60592                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    60684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    60779                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62031                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    62029                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    60742                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59460                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1266500                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      109.102187                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      83.148932                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     142.836675                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         979529     77.34%     77.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       199046     15.72%     93.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        36524      2.88%     95.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        14982      1.18%     97.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         8864      0.70%     97.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4419      0.35%     98.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         2809      0.22%     98.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2238      0.18%     98.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        18089      1.43%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1266500                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         58142                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.680816                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      161.230571                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          58099     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           17      0.03%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            6      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1810756                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      105.200206                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.912098                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     131.997170                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1417049     78.26%     78.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       275870     15.24%     93.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        50109      2.77%     96.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20785      1.15%     97.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12643      0.70%     98.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6844      0.38%     98.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5544      0.31%     98.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3818      0.21%     99.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        18094      1.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1810756                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59345                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.999023                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      160.520477                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          59305     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           12      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            9      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            9      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
@@ -222,120 +222,98 @@ system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% #
 system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           58142                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         58142                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.509374                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.424358                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.849185                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              29010     49.90%     49.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1046      1.80%     51.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               6657     11.45%     63.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19              16493     28.37%     91.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20               3312      5.70%     97.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21               1061      1.82%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                264      0.45%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 97      0.17%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 56      0.10%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 17      0.03%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 18      0.03%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 13      0.02%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  5      0.01%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  6      0.01%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.01%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  5      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  5      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  3      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  3      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  2      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  2      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                 28      0.05%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  9      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  6      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54                  1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::59                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           58142                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    19659284500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               80383790750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9791880000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 50932626250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       10038.56                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    26007.58                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total           59345                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59345                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.154486                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.116028                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.157894                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27533     46.39%     46.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1478      2.49%     48.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              25288     42.61%     91.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4106      6.92%     98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                708      1.19%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                151      0.25%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 51      0.09%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 15      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  6      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59345                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    39644301500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76364826500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9792140000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20242.92                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41046.15                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         124.42                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          64.68                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      124.51                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       64.68                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  38992.92                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         124.62                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          64.78                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      124.70                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       64.78                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.48                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.97                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.51                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.03                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     753336                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    422191                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   38.47                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.47                       # Row buffer hit rate for writes
-system.physmem.avgGap                       338288.60                       # Average gap between requests
-system.physmem.pageHitRate                      39.49                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              12.29                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    189187560                       # Throughput (bytes/s)
+system.physmem.avgWrQLen                        24.55                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     749188                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    416511                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   38.25                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  40.91                       # Row buffer hit rate for writes
+system.physmem.avgGap                       337761.54                       # Average gap between requests
+system.physmem.pageHitRate                      39.16                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     297166155500                       # Time in different power states
+system.physmem.memoryStateTime::REF       33584720000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      675014883250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    189482780                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq             1178393                       # Transaction distribution
 system.membus.trans_dist::ReadResp            1178393                       # Transaction distribution
-system.membus.trans_dist::Writeback           1018055                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            781295                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           781295                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4937431                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4937431                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190575552                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           190575552                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              190575552                       # Total data (bytes)
+system.membus.trans_dist::Writeback           1018056                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            781296                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           781296                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4937434                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4937434                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190575680                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           190575680                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              190575680                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         11782666500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy         11779296500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        18347417750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        18345408000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               326511183                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         252559725                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect         138218265                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            220270477                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               135614039                       # Number of BTB hits
+system.cpu.branchPred.lookups               326515024                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         252570896                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect         138240520                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            220728385                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               135412850                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.567052                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             61.348181                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                16767439                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  6                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    444830139                       # DTB read hits
+system.cpu.dtb.read_hits                    444825863                       # DTB read hits
 system.cpu.dtb.read_misses                    4897078                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                449727217                       # DTB read accesses
-system.cpu.dtb.write_hits                   160844128                       # DTB write hits
+system.cpu.dtb.read_accesses                449722941                       # DTB read accesses
+system.cpu.dtb.write_hits                   160844247                       # DTB write hits
 system.cpu.dtb.write_misses                   1701304                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               162545432                       # DTB write accesses
-system.cpu.dtb.data_hits                    605674267                       # DTB hits
+system.cpu.dtb.write_accesses               162545551                       # DTB write accesses
+system.cpu.dtb.data_hits                    605670110                       # DTB hits
 system.cpu.dtb.data_misses                    6598382                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                612272649                       # DTB accesses
-system.cpu.itb.fetch_hits                   232118114                       # ITB hits
+system.cpu.dtb.data_accesses                612268492                       # DTB accesses
+system.cpu.itb.fetch_hits                   231919747                       # ITB hits
 system.cpu.itb.fetch_misses                        22                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               232118136                       # ITB accesses
+system.cpu.itb.fetch_accesses               231919769                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -349,34 +327,34 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       2014673184                       # number of cpu cycles simulated
+system.cpu.numCycles                       2011535614                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken    172428181                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken    154083002                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads   1667622783                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken    172226277                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken    154288747                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads   1667639381                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites   1376202617                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses   3043825400                       # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads          231                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses   3043841998                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads          229                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites          345                       # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses          576                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards      651695392                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                  617886274                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect    120493688                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect     11126119                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted      131619807                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted          83580161                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     61.161629                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions       1139354623                       # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses          574                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      651725578                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                  617883712                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect    120527925                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect     11114137                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted      131642062                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          83557916                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     61.171968                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions       1139358188                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                75                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                    1742144730                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                    1742007028                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                         7512368                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       442846963                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                       1571826221                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         78.018918                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                         7502506                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       439794636                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                       1571740978                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         78.136373                       # Percentage of cycles cpu is active
 system.cpu.comLoads                         444595663                       # Number of Load instructions committed
 system.cpu.comStores                        160728502                       # Number of Store instructions committed
 system.cpu.comBranches                      214632552                       # Number of Branches instructions committed
@@ -388,226 +366,226 @@ system.cpu.committedInsts                  1819780127                       # Nu
 system.cpu.committedOps                    1819780127                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total            1819780127                       # Number of Instructions committed (Total)
-system.cpu.cpi                               1.107097                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               1.105373                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         1.107097                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.903263                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         1.105373                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.904672                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.903263                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                827756857                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                1186916327                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               58.913591                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles               1081059316                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                 933613868                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               46.340711                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles               1042290381                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                 972382803                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               48.265039                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles               1605047974                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                 409625210                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               20.332092                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                993337465                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                1021335719                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               50.694858                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         0.904672                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                824896841                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                1186638773                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               58.991686                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles               1077691733                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 933843881                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               46.424427                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles               1039140389                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 972395225                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               48.340940                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles               1601912902                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                 409622712                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               20.363682                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                990187341                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                1021348273                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               50.774556                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           668.288600                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           232116975                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           668.237280                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           231918592                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               859                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          270217.665891                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          269986.719441                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   668.288600                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.326313                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.326313                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   668.237280                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.326288                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.326288                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          858                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          785                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.418945                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         464237087                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        464237087                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    232116975                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       232116975                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     232116975                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        232116975                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    232116975                       # number of overall hits
-system.cpu.icache.overall_hits::total       232116975                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1139                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1139                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1139                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1139                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1139                       # number of overall misses
-system.cpu.icache.overall_misses::total          1139                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     81449500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     81449500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     81449500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     81449500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     81449500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     81449500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    232118114                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    232118114                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    232118114                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    232118114                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    232118114                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    232118114                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         463840351                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        463840351                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    231918592                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       231918592                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     231918592                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        231918592                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    231918592                       # number of overall hits
+system.cpu.icache.overall_hits::total       231918592                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1154                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1154                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1154                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1154                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1154                       # number of overall misses
+system.cpu.icache.overall_misses::total          1154                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     83508500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     83508500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     83508500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     83508500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     83508500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     83508500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    231919746                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    231919746                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    231919746                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    231919746                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    231919746                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    231919746                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000005                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000005                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000005                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000005                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71509.657594                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 71509.657594                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 71509.657594                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 71509.657594                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 71509.657594                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 71509.657594                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72364.384749                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 72364.384749                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 72364.384749                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 72364.384749                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 72364.384749                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 72364.384749                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          162                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          418                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          162                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          418                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          280                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          280                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          280                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          280                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          280                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          280                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          295                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          295                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          295                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          295                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          295                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          295                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          859                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          859                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          859                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          859                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          859                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          859                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     63326500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     63326500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     63326500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     63326500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     63326500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     63326500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61831500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     61831500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61831500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     61831500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61831500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     61831500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73721.187427                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73721.187427                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73721.187427                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 73721.187427                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73721.187427                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 73721.187427                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71980.791618                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71980.791618                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71980.791618                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71980.791618                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71980.791618                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71980.791618                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               813589109                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        7222688                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7222688                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3693283                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1889624                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1889624                       # Transaction distribution
+system.cpu.toL2Bus.throughput               814858454                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7222692                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7222692                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3693285                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1889623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1889623                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1718                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21916189                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          21917907                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21916197                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          21917915                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819503104                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      819558080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         819558080                       # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819503424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      819558400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         819558400                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10096080500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy    10096085000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1443000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1445000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13971303500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13977776250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements          1926957                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30916.680897                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8958690                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1956750                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.578352                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      67897094750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14926.990701                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    34.739406                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15954.950790                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.455536                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001060                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.486906                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.943502                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements          1926959                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30915.615811                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            8958694                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1956752                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.578349                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      67887905750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14928.983043                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    34.785512                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15951.847256                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.455596                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001062                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.486812                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.943470                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29793                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          586                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          752                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          592                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          746                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12815                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15482                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909210                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        106291134                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       106291134                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.data      6044295                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6044295                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3693283                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3693283                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1108329                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1108329                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7152624                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7152624                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7152624                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7152624                       # number of overall hits
+system.cpu.l2cache.tags.tag_accesses        106291175                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106291175                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.data      6044299                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6044299                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3693285                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3693285                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1108327                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1108327                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7152626                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7152626                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7152626                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7152626                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst          859                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data      1177534                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total      1178393                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       781295                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       781295                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       781296                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       781296                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          859                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1958829                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1959688                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1958830                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1959689                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          859                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1958829                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1959688                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     62463500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  95853275750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  95915739250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68840007000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  68840007000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     62463500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 164693282750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 164755746250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     62463500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 164693282750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 164755746250                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::cpu.data      1958830                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1959689                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     60968500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  94791357750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  94852326250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  65779017750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  65779017750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     60968500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 160570375500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 160631344000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     60968500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 160570375500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 160631344000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          859                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7221829                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7222688                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3693283                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3693283                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889624                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1889624                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7221833                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7222692                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3693285                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3693285                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889623                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1889623                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          859                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9111453                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9112312                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9111456                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9112315                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          859                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9111453                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9112312                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9111456                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9112315                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163052                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.163152                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413466                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.413466                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.163151                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413467                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.413467                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.214985                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.215059                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.214985                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.215059                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72716.530850                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81401.705386                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 81395.374251                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88110.133816                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88110.133816                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72716.530850                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84077.417044                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 84072.437169                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72716.530850                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84077.417044                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 84072.437169                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70976.135041                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80499.890237                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 80492.947811                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84192.185484                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84192.185484                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70976.135041                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81972.593589                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81967.773458                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70976.135041                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81972.593589                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81967.773458                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -616,94 +594,94 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1018055                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1018055                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1018056                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1018056                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          859                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1177534                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total      1178393                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       781295                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       781295                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       781296                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       781296                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          859                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1958829                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1959688                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1958830                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1959689                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          859                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1958829                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1959688                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     51686000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  81095366750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  81147052750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  59075528500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  59075528500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     51686000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140170895250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 140222581250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     51686000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140170895250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 140222581250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1958830                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1959689                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     50186500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  80032548250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  80082734750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  56010972750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  56010972750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     50186500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 136043521000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 136093707500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     50186500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 136043521000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 136093707500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163052                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163152                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413466                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413466                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163151                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413467                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413467                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214985                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.215059                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214985                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.215059                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60169.965076                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68868.811219                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68862.470118                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75612.321210                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75612.321210                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60169.965076                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71558.515445                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71553.523444                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60169.965076                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71558.515445                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71553.523444                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58424.330617                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67966.231336                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67959.275683                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71689.824023                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71689.824023                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58424.330617                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69451.417938                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69446.584382                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58424.330617                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69451.417938                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69446.584382                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9107357                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4082.325879                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           593298406                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9111453                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.115674                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       12706876000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4082.325879                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.996662                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.996662                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9107360                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4082.305318                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           593299863                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9111456                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.115813                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       12706320250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4082.305318                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.996657                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.996657                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          560                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2879                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          619                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          574                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2872                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          612                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1219759783                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1219759783                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    437268768                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       437268768                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    156029638                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      156029638                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     593298406                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        593298406                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    593298406                       # number of overall hits
-system.cpu.dcache.overall_hits::total       593298406                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7326895                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7326895                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4698864                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4698864                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data     12025759                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       12025759                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     12025759                       # number of overall misses
-system.cpu.dcache.overall_misses::total      12025759                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 180765205750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 180765205750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 250221551250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 250221551250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 430986757000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 430986757000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 430986757000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 430986757000                       # number of overall miss cycles
+system.cpu.dcache.tags.tag_accesses        1219759786                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1219759786                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    437268763                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       437268763                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    156031100                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      156031100                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     593299863                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        593299863                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    593299863                       # number of overall hits
+system.cpu.dcache.overall_hits::total       593299863                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7326900                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7326900                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4697402                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4697402                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data     12024302                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       12024302                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     12024302                       # number of overall misses
+system.cpu.dcache.overall_misses::total      12024302                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 179720219500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 179720219500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 246249534250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 246249534250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 425969753750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 425969753750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 425969753750                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 425969753750                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
@@ -714,54 +692,54 @@ system.cpu.dcache.overall_accesses::cpu.data    605324165
 system.cpu.dcache.overall_accesses::total    605324165                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016480                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.016480                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029235                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029235                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.019867                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.019867                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.019867                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.019867                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24671.461206                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24671.461206                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53251.498926                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53251.498926                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 35838.632472                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 35838.632472                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35838.632472                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35838.632472                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     11447989                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      7764770                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            416735                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           73422                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    27.470668                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   105.755359                       # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029226                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029226                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.019864                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.019864                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.019864                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.019864                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24528.821125                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24528.821125                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52422.495296                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 52422.495296                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 35425.736459                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 35425.736459                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35425.736459                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35425.736459                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     10235273                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      7848261                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            412771                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           73432                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    24.796492                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   106.877941                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3693283                       # number of writebacks
-system.cpu.dcache.writebacks::total           3693283                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       104624                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       104624                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2809682                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2809682                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2914306                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2914306                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2914306                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2914306                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222271                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7222271                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3693285                       # number of writebacks
+system.cpu.dcache.writebacks::total           3693285                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       104626                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       104626                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2808220                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2808220                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2912846                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2912846                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2912846                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2912846                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222274                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7222274                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889182                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total      1889182                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9111453                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9111453                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9111453                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9111453                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 163647011750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 163647011750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  81975016250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  81975016250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245622028000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 245622028000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245622028000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 245622028000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9111456                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9111456                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9111456                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9111456                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162584714500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 162584714500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  78915202250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  78915202250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 241499916750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 241499916750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 241499916750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 241499916750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011754                       # mshr miss rate for WriteReq accesses
@@ -770,14 +748,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015052
 system.cpu.dcache.demand_mshr_miss_rate::total     0.015052                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015052                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.015052                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22658.663978                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22658.663978                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43391.804628                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43391.804628                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26957.503704                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26957.503704                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26957.503704                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26957.503704                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22511.568309                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22511.568309                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41772.154430                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41772.154430                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26505.085109                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26505.085109                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26505.085109                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26505.085109                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 2f4d3475f..c3541208a 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.682192                       # Number of seconds simulated
-sim_ticks                                682191807000                       # Number of ticks simulated
-final_tick                               682191807000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.680209                       # Number of seconds simulated
+sim_ticks                                680209231000                       # Number of ticks simulated
+final_tick                               680209231000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 139307                       # Simulator instruction rate (inst/s)
-host_op_rate                                   139307                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               54741914                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 268504                       # Number of bytes of host memory used
-host_seconds                                 12461.96                       # Real time elapsed on the host
+host_inst_rate                                 134123                       # Simulator instruction rate (inst/s)
+host_op_rate                                   134123                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52551522                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 268516                       # Number of bytes of host memory used
+host_seconds                                 12943.66                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             61696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125800064                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125861760                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65265984                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65265984                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                964                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1965626                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1966590                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1019781                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1019781                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                90438                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            184405709                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               184496147                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           90438                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              90438                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          95671017                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               95671017                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          95671017                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               90438                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           184405709                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              280167164                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1966590                       # Number of read requests accepted
-system.physmem.writeReqs                      1019781                       # Number of write requests accepted
-system.physmem.readBursts                     1966590                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1019781                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125780416                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     81344                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65264896                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125861760                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65265984                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1271                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             61568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         125794880                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125856448                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65262848                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65262848                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                962                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1965545                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1966507                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1019732                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1019732                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                90513                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            184935567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               185026081                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           90513                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              90513                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          95945255                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               95945255                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          95945255                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               90513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           184935567                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              280971335                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1966507                       # Number of read requests accepted
+system.physmem.writeReqs                      1019732                       # Number of write requests accepted
+system.physmem.readBursts                     1966507                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1019732                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125774784                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     81664                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65260864                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125856448                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65262848                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1276                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118991                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114394                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116519                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              118029                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              118142                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117777                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              120156                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124892                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              127514                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130376                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             129025                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130742                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126628                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125605                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122932                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123597                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61284                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61572                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60658                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61323                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61765                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63192                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64214                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65706                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65482                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               65855                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65405                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65740                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64329                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64310                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64647                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64282                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118983                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              114362                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116533                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              118021                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              118095                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117780                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              120157                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124901                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              127484                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130413                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             129050                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130729                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126632                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125586                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122901                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123604                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61270                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61551                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60668                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61328                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61752                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63187                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64234                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65693                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65471                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               65863                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65411                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65720                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64318                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64300                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64642                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64293                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    682191684500                       # Total gap between requests
+system.physmem.totGap                    680209108500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1966590                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1966507                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1019781                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1642976                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    230548                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     69552                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     22230                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1019732                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1643607                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    226349                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     73697                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     21571                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    23411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    24830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    31804                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    47471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    54150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    57221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    58425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    59086                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    59586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    60134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    64812                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    65271                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    65616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    73465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    64939                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    61899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    60584                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                    17452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     5357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1832                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      358                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    28201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    29888                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    50211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56677                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60086                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    60607                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    60720                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    60883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61463                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    63111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    63876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    61304                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61887                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    60350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59595                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
@@ -193,139 +193,130 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1251998                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      113.111439                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      84.586325                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     150.844327                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         955672     76.33%     76.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       201584     16.10%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        38062      3.04%     95.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        16101      1.29%     96.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         9606      0.77%     97.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4835      0.39%     97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3234      0.26%     98.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2576      0.21%     98.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20328      1.62%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1251998                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         58888                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.373692                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      161.339848                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          58850     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           11      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1771936                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      107.810521                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.950451                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     136.949127                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1375751     77.64%     77.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       273384     15.43%     93.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        53057      2.99%     96.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21092      1.19%     97.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12942      0.73%     97.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6638      0.37%     98.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4973      0.28%     98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3952      0.22%     98.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20147      1.14%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1771936                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59540                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.963117                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      163.210264                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          59503     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           10      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            8      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           58888                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         58888                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.317009                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.233410                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.918536                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17           34047     57.82%     57.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19           20086     34.11%     91.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21            4266      7.24%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23             290      0.49%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              84      0.14%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              30      0.05%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29              14      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               5      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               4      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               3      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               2      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39              12      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41              19      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43               9      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45               1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47               4      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-65               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::78-79               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::86-87               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-89               1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-105             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::106-107             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           58888                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    20653307250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               80037239750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9826595000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 49557337500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       10508.88                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    25215.93                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total           59540                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59540                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.126318                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.084701                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.213811                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              29197     49.04%     49.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1546      2.60%     51.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              22630     38.01%     89.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4967      8.34%     97.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                921      1.55%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                191      0.32%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 48      0.08%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 11      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  6      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  3      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  4      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59540                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    40008960000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76857041250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9826155000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20358.40                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  40724.81                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         184.38                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          95.67                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      184.50                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       95.67                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39108.40                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         184.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          95.94                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      185.03                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       95.95                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.19                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.44                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.75                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.29                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     797879                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    422825                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   40.60                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.46                       # Row buffer hit rate for writes
-system.physmem.avgGap                       228435.01                       # Average gap between requests
-system.physmem.pageHitRate                      40.89                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               7.23                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    280167164                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             1191439                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1191439                       # Transaction distribution
-system.membus.trans_dist::Writeback           1019781                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            775151                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           775151                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4952961                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4952961                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191127744                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           191127744                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              191127744                       # Total data (bytes)
+system.physmem.avgWrQLen                        24.89                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     795143                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    417847                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.46                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  40.98                       # Row buffer hit rate for writes
+system.physmem.avgGap                       227781.20                       # Average gap between requests
+system.physmem.pageHitRate                      40.64                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     135240615750                       # Time in different power states
+system.physmem.memoryStateTime::REF       22713600000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      522252858000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    280971335                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1191350                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1191350                       # Transaction distribution
+system.membus.trans_dist::Writeback           1019732                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            775157                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           775157                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4952746                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4952746                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191119296                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           191119296                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              191119296                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         11872683000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy         11871718000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        18474077250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        18474668250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               381618384                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         296575373                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          16092188                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            262164042                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               259697812                       # Number of BTB hits
+system.cpu.branchPred.lookups               381496982                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         296448748                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          16088801                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            262281784                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               259596653                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.059280                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                24705469                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3069                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.976242                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                24710775                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3135                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    613976008                       # DTB read hits
-system.cpu.dtb.read_misses                   11261750                       # DTB read misses
+system.cpu.dtb.read_hits                    613956448                       # DTB read hits
+system.cpu.dtb.read_misses                   11261576                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                625237758                       # DTB read accesses
-system.cpu.dtb.write_hits                   212363538                       # DTB write hits
-system.cpu.dtb.write_misses                   7134748                       # DTB write misses
+system.cpu.dtb.read_accesses                625218024                       # DTB read accesses
+system.cpu.dtb.write_hits                   212357219                       # DTB write hits
+system.cpu.dtb.write_misses                   7142526                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               219498286                       # DTB write accesses
-system.cpu.dtb.data_hits                    826339546                       # DTB hits
-system.cpu.dtb.data_misses                   18396498                       # DTB misses
+system.cpu.dtb.write_accesses               219499745                       # DTB write accesses
+system.cpu.dtb.data_hits                    826313667                       # DTB hits
+system.cpu.dtb.data_misses                   18404102                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                844736044                       # DTB accesses
-system.cpu.itb.fetch_hits                   391110222                       # ITB hits
-system.cpu.itb.fetch_misses                        44                       # ITB misses
+system.cpu.dtb.data_accesses                844717769                       # DTB accesses
+system.cpu.itb.fetch_hits                   391069582                       # ITB hits
+system.cpu.itb.fetch_misses                        39                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               391110266                       # ITB accesses
+system.cpu.itb.fetch_accesses               391069621                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -339,138 +330,137 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1364383615                       # number of cpu cycles simulated
+system.cpu.numCycles                       1360418463                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          402585287                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3161125101                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   381618384                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          284403281                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     574536383                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               140665925                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              188120516                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  124                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1448                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles            4                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 391110222                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8062763                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1282059246                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.465662                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.145744                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          402539494                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3160334453                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   381496982                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          284307428                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     574405529                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               140578200                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              186557630                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   26                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1439                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 391069582                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8066485                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1280247946                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.468533                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.146412                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                707522863     55.19%     55.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42675531      3.33%     58.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 21787283      1.70%     60.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 39707555      3.10%     63.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                129310443     10.09%     73.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 61549431      4.80%     78.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 38571496      3.01%     81.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 28142716      2.20%     83.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                212791928     16.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                705842417     55.13%     55.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 42672657      3.33%     58.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 21781408      1.70%     60.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 39699602      3.10%     63.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                129277672     10.10%     73.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 61541075      4.81%     78.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 38576961      3.01%     81.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 28126887      2.20%     83.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                212729267     16.62%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1282059246                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.279700                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.316889                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                434597074                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             169317553                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 542454813                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              18875119                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              116814687                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             58354170                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   898                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3088496267                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2037                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              116814687                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                457547940                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               113953082                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           6967                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 535589228                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              58147342                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3006454755                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                609106                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1833248                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              51828481                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2247677853                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3898974365                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3898830865                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            143499                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1280247946                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.280426                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.323061                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                434538205                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             167760960                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 542351250                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              18854501                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              116743030                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             58351365                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   885                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3087789939                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2070                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              116743030                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                457481337                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               112438612                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7413                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 535473100                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              58104454                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3005831981                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                610085                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1830591                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              51785017                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2247201366                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3898074686                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3897930349                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            144336                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                871474890                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                178                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            177                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 123676155                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            679702242                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           255475560                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          67614908                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         37053481                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2724914461                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 131                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2509610552                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3196332                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       979670705                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    416123894                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            102                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1282059246                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.957484                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.971278                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                870998403                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                181                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            180                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 123645792                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            679622906                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           255441649                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          67625349                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         36837000                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2724438630                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 139                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2509429146                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3195077                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       979206212                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    415660734                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            110                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1280247946                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.960112                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.971405                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           440049739     34.32%     34.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           203670606     15.89%     50.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           185671301     14.48%     64.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           153363283     11.96%     76.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           133052268     10.38%     87.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            80767651      6.30%     93.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            65047769      5.07%     98.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            15319478      1.19%     99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             5117151      0.40%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           438364734     34.24%     34.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           203576191     15.90%     50.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           185673841     14.50%     64.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           153359678     11.98%     76.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           133007255     10.39%     87.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            80763135      6.31%     93.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            65057682      5.08%     98.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            15327988      1.20%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             5117442      0.40%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1282059246                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1280247946                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2188252     11.81%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11925862     64.39%     76.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4407339     23.80%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2183926     11.79%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11926883     64.38%     76.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4416070     23.84%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1643881644     65.50%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                   99      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1643735577     65.50%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                  113      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 265      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 274      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                  15      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 161      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 23      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 163      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 33      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                  25      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.50% # Type of FU issued
@@ -493,84 +483,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.50% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            641614566     25.57%     91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           224113754      8.93%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            641577426     25.57%     91.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           224115520      8.93%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2509610552                       # Type of FU issued
-system.cpu.iq.rate                           1.839373                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    18521453                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007380                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6321098058                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3703474382                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2413201675                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1900077                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1218284                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       852187                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2527192648                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  939357                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         62588107                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2509429146                       # Type of FU issued
+system.cpu.iq.rate                           1.844601                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    18526879                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007383                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6318927693                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3702533179                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2413056574                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1900501                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1218976                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       851931                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2527016485                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  939540                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         62611923                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    235106579                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       263309                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       109146                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     94747058                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    235027243                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       263015                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       108918                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     94713147                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          184                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1530387                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          189                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1519116                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              116814687                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                54760955                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1302145                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2867095326                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           8936600                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             679702242                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            255475560                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                131                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 285836                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 18373                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         109146                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10363389                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8561306                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             18924695                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2462265598                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             625238282                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          47344954                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              116743030                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                54024400                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1298779                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2866611550                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           8938226                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             679622906                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            255441649                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                139                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 284739                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 17925                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         108918                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10360501                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8559141                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18919642                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2462113163                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             625218563                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          47315983                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     142180734                       # number of nop insts executed
-system.cpu.iew.exec_refs                    844736593                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                300891924                       # Number of branches executed
-system.cpu.iew.exec_stores                  219498311                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.804673                       # Inst execution rate
-system.cpu.iew.wb_sent                     2442007403                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2414053862                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1388335082                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1764294016                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     142172781                       # number of nop insts executed
+system.cpu.iew.exec_refs                    844718328                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                300875979                       # Number of branches executed
+system.cpu.iew.exec_stores                  219499765                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.809820                       # Inst execution rate
+system.cpu.iew.wb_sent                     2441867145                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2413908505                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1388259644                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1764197986                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.769337                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       1.774387                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.786907                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       826637792                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       826160079                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          16091391                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1165244559                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.561715                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.500982                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          16088003                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1163504916                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.564050                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.502160                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    651170378     55.88%     55.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    175014835     15.02%     70.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     86149099      7.39%     78.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     53527990      4.59%     82.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     34710349      2.98%     85.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     26102733      2.24%     88.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     21568948      1.85%     89.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     22887442      1.96%     91.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     94112785      8.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    649463962     55.82%     55.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    174969107     15.04%     70.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     86152065      7.40%     78.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     53532710      4.60%     82.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     34727147      2.98%     85.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26083842      2.24%     88.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     21573250      1.85%     89.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     22881203      1.97%     91.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     94121630      8.09%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1165244559                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1163504916                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
 system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -581,224 +571,259 @@ system.cpu.commit.branches                  214632552                       # Nu
 system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              94112785                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass     83736345      4.60%      4.60% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu       1130719227     62.13%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult              75      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd            166      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp             13      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt            100      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult            11      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv             24      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       444595663     24.43%     91.17% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              94121630                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3631770492                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5409749589                       # The number of ROB writes
-system.cpu.timesIdled                          953701                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        82324369                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3629544291                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5408721730                       # The number of ROB writes
+system.cpu.timesIdled                          949757                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        80170517                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
-system.cpu.cpi                               0.785915                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.785915                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.272402                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.272402                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3318200326                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1932098427                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     30699                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      520                       # number of floating regfile writes
+system.cpu.cpi                               0.783631                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.783631                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.276110                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.276110                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3317990648                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1931970641                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     30869                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      545                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1210780745                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        7297678                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7297678                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3724768                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1883565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1883565                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1928                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22085326                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22087254                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825923008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      825984704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         825984704                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              1214348707                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7297685                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7297685                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3725127                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1883613                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1883613                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1924                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22085799                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          22087723                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825949632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      826011200                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         826011200                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10177843430                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy    10178394945                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1605500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1603000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14065476499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14072846750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           773.695817                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           391108717                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               964                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          405714.436722                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           772.655537                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           391068098                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               962                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          406515.694387                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   773.695817                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.377781                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.377781                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          963                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          906                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.470215                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         782221404                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        782221404                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    391108717                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       391108717                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     391108717                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        391108717                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    391108717                       # number of overall hits
-system.cpu.icache.overall_hits::total       391108717                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1503                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1503                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1503                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1503                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1503                       # number of overall misses
-system.cpu.icache.overall_misses::total          1503                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    108284500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    108284500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    108284500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    108284500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    108284500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    108284500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    391110220                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    391110220                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    391110220                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    391110220                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    391110220                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    391110220                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst   772.655537                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.377273                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.377273                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          961                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          902                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.469238                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         782140126                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        782140126                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    391068098                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       391068098                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     391068098                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        391068098                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    391068098                       # number of overall hits
+system.cpu.icache.overall_hits::total       391068098                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1484                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1484                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1484                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1484                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1484                       # number of overall misses
+system.cpu.icache.overall_misses::total          1484                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    102456750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    102456750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    102456750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    102456750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    102456750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    102456750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    391069582                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    391069582                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    391069582                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    391069582                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    391069582                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    391069582                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72045.575516                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72045.575516                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72045.575516                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72045.575516                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72045.575516                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72045.575516                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          349                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69040.936658                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69040.936658                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69040.936658                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69040.936658                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69040.936658                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69040.936658                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          407                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    69.800000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   203.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          539                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          539                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          539                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          539                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          539                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          539                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          964                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          964                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          964                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          964                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          964                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          964                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75722000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     75722000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75722000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     75722000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75722000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     75722000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          522                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          522                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          522                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          522                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          522                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          522                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          962                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          962                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          962                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          962                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          962                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          962                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     71417000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     71417000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     71417000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     71417000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     71417000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     71417000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78549.792531                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78549.792531                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78549.792531                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 78549.792531                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78549.792531                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 78549.792531                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74238.045738                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74238.045738                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74238.045738                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 74238.045738                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74238.045738                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 74238.045738                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1933885                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31421.269549                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            9058254                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1963664                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.612935                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      28359986250                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14571.956791                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.815575                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.497182                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.444701                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000818                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.513382                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.958901                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29779                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          974                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements          1933800                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31420.392793                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            9058700                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1963581                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.613357                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      28339083250                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14569.495652                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.490666                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 16824.406475                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.444626                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000808                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.513440                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.958874                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29781                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          150                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          975                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          593                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17299                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10767                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908783                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        107095317                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       107095317                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.data      6106239                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6106239                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3724768                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3724768                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1108414                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1108414                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7214653                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7214653                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7214653                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7214653                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          964                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1190475                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1191439                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       775151                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       775151                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          964                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1965626                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1966590                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          964                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1965626                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1966590                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     74752000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  99906666750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  99981418750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  65179640000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  65179640000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     74752000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 165086306750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 165161058750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     74752000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 165086306750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 165161058750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          964                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7296714                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7297678                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3724768                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3724768                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1883565                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1883565                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          964                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9180279                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9181243                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          964                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9180279                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9181243                       # number of overall (read+write) accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17306                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10757                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908844                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        107098594                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       107098594                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.data      6106335                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6106335                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3725127                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3725127                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1108456                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1108456                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7214791                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7214791                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7214791                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7214791                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          962                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1190388                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1191350                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       775157                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       775157                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          962                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1965545                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1966507                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          962                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1965545                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1966507                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     70450000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  97815753000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  97886203000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  63988346750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  63988346750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     70450000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 161804099750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 161874549750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     70450000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 161804099750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 161874549750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          962                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7296723                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7297685                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3725127                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3725127                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1883613                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1883613                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          962                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9180336                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9181298                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          962                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9180336                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9181298                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163152                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.163263                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411534                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.411534                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163140                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.163250                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411527                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.411527                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.214114                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.214196                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.214104                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.214186                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.214114                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214196                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77543.568465                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83921.683992                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 83916.523423                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84086.378009                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84086.378009                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77543.568465                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83986.631613                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 83983.473296                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77543.568465                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83986.631613                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 83983.473296                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.214104                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214186                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73232.848233                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82171.319771                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 82164.102069                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82548.885903                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82548.885903                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73232.848233                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82320.221491                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82315.776018                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73232.848233                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82320.221491                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82315.776018                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -807,188 +832,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1019781                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1019781                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          964                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1190475                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1191439                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       775151                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       775151                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          964                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1965626                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1966590                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          964                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1965626                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1966590                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     62625000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  84983280750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  85045905750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  55444498500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  55444498500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     62625000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140427779250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 140490404250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     62625000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140427779250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 140490404250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks      1019732                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1019732                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          962                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1190388                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1191350                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       775157                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       775157                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          962                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1965545                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1966507                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          962                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1965545                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1966507                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     58345500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  82892612500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  82950958000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  54245247750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  54245247750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     58345500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137137860250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 137196205750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     58345500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137137860250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 137196205750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163152                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163263                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411534                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411534                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163140                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163250                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411527                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411527                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214114                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214196                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214104                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214186                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214114                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214196                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64963.692946                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71386.027216                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71380.830869                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71527.352090                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71527.352090                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64963.692946                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71441.759139                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71438.583665                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64963.692946                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71441.759139                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71438.583665                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214104                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214186                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60650.207900                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69634.953057                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69627.697990                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69979.691533                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69979.691533                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60650.207900                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69770.908450                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69766.446674                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60650.207900                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69770.908450                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69766.446674                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9176183                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.522150                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           694277633                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9180279                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             75.627073                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        5178034250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.522150                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997930                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997930                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9176240                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.503872                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           694248122                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9180336                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             75.623389                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        5175532250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.503872                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997926                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997926                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          705                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2966                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          421                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          694                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2982                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          416                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1430905565                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1430905565                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    538740047                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       538740047                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    155537583                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      155537583                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     694277630                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        694277630                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    694277630                       # number of overall hits
-system.cpu.dcache.overall_hits::total       694277630                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     11394090                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      11394090                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5190919                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5190919                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses        1430846728                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1430846728                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    538710092                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       538710092                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155538028                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155538028                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            2                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            2                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     694248120                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        694248120                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    694248120                       # number of overall hits
+system.cpu.dcache.overall_hits::total       694248120                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     11394599                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      11394599                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5190474                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5190474                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     16585009                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       16585009                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     16585009                       # number of overall misses
-system.cpu.dcache.overall_misses::total      16585009                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 335805939499                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 335805939499                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 289123962439                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 289123962439                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       201500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       201500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 624929901938                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 624929901938                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 624929901938                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 624929901938                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    550134137                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    550134137                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     16585073                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       16585073                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     16585073                       # number of overall misses
+system.cpu.dcache.overall_misses::total      16585073                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 331603001250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 331603001250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 288972510585                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 288972510585                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       129500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       129500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 620575511835                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 620575511835                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 620575511835                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 620575511835                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    550104691                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    550104691                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    710862639                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    710862639                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    710862639                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    710862639                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020711                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.020711                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032296                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032296                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.250000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.250000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023331                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023331                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.023331                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.023331                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29471.940234                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 29471.940234                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55698.030048                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55698.030048                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data       201500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total       201500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37680.407767                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37680.407767                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37680.407767                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37680.407767                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     11880802                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      8587513                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            745209                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            3                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            3                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    710833193                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    710833193                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    710833193                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    710833193                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020714                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.020714                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032293                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032293                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.333333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.333333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023332                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023332                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.023332                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.023332                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29101.770168                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 29101.770168                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55673.626452                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55673.626452                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data       129500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total       129500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37417.713617                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37417.713617                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37417.713617                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37417.713617                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     11561530                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      8659652                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            743678                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets           65135                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.942913                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   131.841759                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.546419                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   132.949290                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3724768                       # number of writebacks
-system.cpu.dcache.writebacks::total           3724768                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4097367                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4097367                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3307364                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3307364                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      7404731                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      7404731                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      7404731                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      7404731                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7296723                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7296723                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1883555                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1883555                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3725127                       # number of writebacks
+system.cpu.dcache.writebacks::total           3725127                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4097867                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4097867                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3306871                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3306871                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      7404738                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      7404738                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      7404738                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      7404738                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7296732                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7296732                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1883603                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1883603                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9180278                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9180278                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9180278                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9180278                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 169103281751                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 169103281751                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  78582140948                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  78582140948                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data       199500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total       199500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 247685422699                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 247685422699                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 247685422699                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 247685422699                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9180335                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9180335                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9180335                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9180335                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167014367250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 167014367250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77391574454                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  77391574454                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data       127500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total       127500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244405941704                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 244405941704                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244405941704                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 244405941704                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013264                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013264                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011719                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011719                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012914                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012914                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012914                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012914                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23175.236576                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23175.236576                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41720.120171                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41720.120171                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data       199500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total       199500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26980.165818                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26980.165818                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26980.165818                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26980.165818                       # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.333333                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012915                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012915                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012915                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012915                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22888.927159                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22888.927159                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41086.988317                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41086.988317                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data       127500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total       127500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.769398                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.769398                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.769398                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.769398                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index b81e9af80..f3e627477 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.913189                       # Nu
 sim_ticks                                913189263000                       # Number of ticks simulated
 final_tick                               913189263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1966439                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1966439                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              986784511                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 271364                       # Number of bytes of host memory used
-host_seconds                                   925.42                       # Real time elapsed on the host
+host_inst_rate                                2693565                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2693565                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1351665756                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256712                       # Number of bytes of host memory used
+host_seconds                                   675.60                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -95,5 +95,40 @@ system.cpu.num_busy_cycles                 1826378527                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         214632552                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              83736345      4.58%      4.58% # Class of executed instruction
+system.cpu.op_class::IntAlu                1130719228     61.91%     66.50% # Class of executed instruction
+system.cpu.op_class::IntMult                       75      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatAdd                     166      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatCmp                      13      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatCvt                     100      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatMult                     11      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatDiv                      24      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::MemRead                449492741     24.61%     91.11% # Class of executed instruction
+system.cpu.op_class::MemWrite               162429806      8.89%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 1826378509                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index c20c38ead..2ba96be4b 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.623386                       # Nu
 sim_ticks                                2623386226000                       # Number of ticks simulated
 final_tick                               2623386226000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1078959                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1078959                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1555422646                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280076                       # Number of bytes of host memory used
-host_seconds                                  1686.61                       # Real time elapsed on the host
+host_inst_rate                                1099630                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1099630                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1585220760                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265440                       # Number of bytes of host memory used
+host_seconds                                  1654.90                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -109,6 +109,41 @@ system.cpu.num_busy_cycles                 5246772452                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         214632552                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              83736345      4.58%      4.58% # Class of executed instruction
+system.cpu.op_class::IntAlu                1130719228     61.91%     66.50% # Class of executed instruction
+system.cpu.op_class::IntMult                       75      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatAdd                     166      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatCmp                      13      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatCvt                     100      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatMult                     11      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatDiv                      24      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::MemRead                449492741     24.61%     91.11% # Class of executed instruction
+system.cpu.op_class::MemWrite               162429806      8.89%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 1826378509                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 1                       # number of replacements
 system.cpu.icache.tags.tagsinuse           612.458646                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1826377708                       # Total number of references to valid blocks.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 06e7873ee..980e25610 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.530994                       # Number of seconds simulated
-sim_ticks                                530994193500                       # Number of ticks simulated
-final_tick                               530994193500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.528386                       # Number of seconds simulated
+sim_ticks                                528386107000                       # Number of ticks simulated
+final_tick                               528386107000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125227                       # Simulator instruction rate (inst/s)
-host_op_rate                                   139700                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43051016                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313040                       # Number of bytes of host memory used
-host_seconds                                 12334.07                       # Real time elapsed on the host
+host_inst_rate                                 123376                       # Simulator instruction rate (inst/s)
+host_op_rate                                   137635                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               42206077                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313484                       # Number of bytes of host memory used
+host_seconds                                 12519.20                       # Real time elapsed on the host
 sim_insts                                  1544563023                       # Number of instructions simulated
 sim_ops                                    1723073835                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             47488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         143709888                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            143757376                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        47488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           47488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     70419456                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          70419456                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                742                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2245467                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2246209                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1100304                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1100304                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                89432                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            270643050                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               270732482                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           89432                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              89432                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         132618128                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              132618128                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         132618128                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               89432                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           270643050                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              403350610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2246209                       # Number of read requests accepted
-system.physmem.writeReqs                      1100304                       # Number of write requests accepted
-system.physmem.readBursts                     2246209                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1100304                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                143663936                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     93440                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  70418368                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 143757376                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               70419456                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1460                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             47936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         143742400                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            143790336                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        47936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           47936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     70434560                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          70434560                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                749                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2245975                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2246724                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1100540                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1100540                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                90722                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            272040461                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               272131182                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           90722                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              90722                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         133301310                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              133301310                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         133301310                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               90722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           272040461                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              405432492                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2246724                       # Number of read requests accepted
+system.physmem.writeReqs                      1100540                       # Number of write requests accepted
+system.physmem.readBursts                     2246724                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1100540                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                143697408                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     92928                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  70433344                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 143790336                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               70434560                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1452                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              139551                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              136202                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              133682                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              136207                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              134706                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              135350                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              136147                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              135992                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              143786                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              146457                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             144536                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             146082                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             145807                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             145943                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             141988                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             142313                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               69095                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               67437                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               65633                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               66265                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               66084                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               66429                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               67953                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               68751                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               70388                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               70973                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              70609                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              70934                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              70330                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              70711                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              69591                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              69104                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              139707                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              136292                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              133767                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              136231                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              134692                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              135454                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              136225                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              136115                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              143769                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              146465                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             144332                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             146005                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             145798                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             145907                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             142108                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             142405                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               69150                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               67464                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               65717                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               66314                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               66158                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               66498                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               67950                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               68767                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               70393                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               70943                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              70514                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              70857                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              70359                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              70734                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              69641                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              69062                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    530994124500                       # Total gap between requests
+system.physmem.totGap                    528386038000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2246209                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2246724                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1100304                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1619262                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    446010                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    134777                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     44683                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1100540                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1622160                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    446140                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    134185                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     42773                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,163 +144,159 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    17958                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    19185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    29573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    48522                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    58770                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    63067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    64531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    65202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    65713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    66239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    70263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    71854                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    72330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    80202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    72456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    68391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    66809                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    65859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                    22753                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     6508                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1933                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      609                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    24008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    25689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    49841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    60617                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    65166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    66484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    66755                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    66961                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    67037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    67317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    67353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    67677                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    68712                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    70133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    67405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    67796                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    66043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    65172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1604351                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      105.964762                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      82.430314                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     134.227606                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1240784     77.34%     77.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       261404     16.29%     93.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        44793      2.79%     96.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        17157      1.07%     97.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        10128      0.63%     98.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4810      0.30%     98.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3056      0.19%     98.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2546      0.16%     98.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19673      1.23%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1604351                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         64945                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        34.562861                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      155.173168                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          64902     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           18      0.03%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      2026945                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      105.641008                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.595213                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     129.312456                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1568777     77.40%     77.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       317859     15.68%     93.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        67458      3.33%     96.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23638      1.17%     97.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        14371      0.71%     98.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6663      0.33%     98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4947      0.24%     98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3635      0.18%     99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19597      0.97%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        2026945                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         65065                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        34.467994                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      154.943879                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          65024     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           17      0.03%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071           12      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            6      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            4      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           64945                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         64945                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.941828                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.872806                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.740981                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17           45649     70.29%     70.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19           15339     23.62%     93.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21            3628      5.59%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23             219      0.34%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              37      0.06%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              12      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29              13      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               7      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39               4      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41              17      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43               3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45               2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::66-67               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-69               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-77               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-81               2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::82-83               1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-85               1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-89               1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::90-91               1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           64945                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    28406230500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               98095071750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  11223745000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 58465096250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       12654.52                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    26045.27                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total           65065                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         65065                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.914178                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.872771                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.215883                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              38677     59.44%     59.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1561      2.40%     61.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              18560     28.53%     90.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4956      7.62%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                979      1.50%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                233      0.36%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 49      0.08%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 12      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  5      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  7      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  3      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  3      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 10      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           65065                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    49926066500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               92024916500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  11226360000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22236.09                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  43699.80                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         270.56                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         132.62                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      270.73                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      132.62                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40986.09                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         271.96                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         133.30                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      272.13                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      133.30                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.15                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.11                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           3.17                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      1.04                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.38                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     908698                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    419053                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   40.48                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  38.09                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158670.87                       # Average gap between requests
-system.physmem.pageHitRate                      39.69                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               6.04                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    403350610                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             1419771                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1419771                       # Transaction distribution
-system.membus.trans_dist::Writeback           1100304                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            826438                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           826438                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5592722                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5592722                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    214176832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           214176832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              214176832                       # Total data (bytes)
+system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.15                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     904882                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    413955                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.30                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  37.61                       # Row buffer hit rate for writes
+system.physmem.avgGap                       157856.10                       # Average gap between requests
+system.physmem.pageHitRate                      39.42                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      96247983250                       # Time in different power states
+system.physmem.memoryStateTime::REF       17643860000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      414492555250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    405432371                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1420231                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1420230                       # Transaction distribution
+system.membus.trans_dist::Writeback           1100540                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            826493                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           826493                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5593987                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5593987                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    214224832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           214224832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              214224832                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         12918660500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy         12921710000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        21056537500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        21064187250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              4.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               303422540                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         249650550                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15218950                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            174790549                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               161666933                       # Number of BTB hits
+system.cpu.branchPred.lookups               303120066                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         249328718                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15217036                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            172898211                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               161402010                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.491805                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                17552768                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                208                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             93.350885                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                17552010                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                206                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -386,99 +382,99 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1061988388                       # number of cpu cycles simulated
+system.cpu.numCycles                       1056772215                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          298972523                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2188716520                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   303422540                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          179219701                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     435616214                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                87982008                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              163592873                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles          298543809                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2186558852                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   303120066                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          178954020                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     435169965                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                87664150                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              162830797                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            98                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 289402821                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               5967581                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          968083151                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.501232                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.206704                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles            66                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 289028116                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               5928471                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          966231390                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.503805                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.207339                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                532467013     55.00%     55.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 25400980      2.62%     57.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 39071584      4.04%     61.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 48282365      4.99%     66.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 43747142      4.52%     71.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 46387901      4.79%     75.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 38401401      3.97%     79.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 18925667      1.95%     81.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                175399098     18.12%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                531061564     54.96%     54.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25270109      2.62%     57.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 39059321      4.04%     61.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 48280752      5.00%     66.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 43652123      4.52%     71.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 46384495      4.80%     75.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 38400203      3.97%     79.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 18890593      1.96%     81.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                175232230     18.14%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            968083151                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.285712                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.060961                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                331186258                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             141449476                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 405224090                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              20322579                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               69900748                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             46031045                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   725                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2368410495                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2465                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               69900748                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                354622933                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                70003752                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          18690                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 400463677                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              73073351                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2305921736                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                149865                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                5017686                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              60142463                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               10                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2281817078                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           10647699630                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       9761875654                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               372                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            966231390                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.286836                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.069092                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                330688304                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             140707592                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 404837901                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              20311495                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               69686098                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             46045464                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   686                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2366336890                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2408                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               69686098                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                354035761                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                69333450                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          19564                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 400161334                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              72995183                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2304279831                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                149122                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                5007808                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              60068670                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               28                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2280029311                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           10640069170                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       9754807461                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               523                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1706319930                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                575497148                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                824                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            821                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 160915749                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            624658588                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           220783882                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          86055084                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         71680407                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2202175358                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 849                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2018579412                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           4016690                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       474511400                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1127247409                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            679                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     968083151                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.085130                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.905910                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                573709381                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                838                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            835                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 160867468                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            624344109                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           220690096                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          85895596                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         71104649                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2201067148                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 872                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2018188753                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           4009836                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       473419118                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1122820623                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            702                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     966231390                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.088722                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.905985                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           285219249     29.46%     29.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           153603913     15.87%     45.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           160908478     16.62%     61.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           120369215     12.43%     74.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           123515877     12.76%     87.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            73725483      7.62%     94.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            38349194      3.96%     98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             9869125      1.02%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2522617      0.26%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           283676122     29.36%     29.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           153451692     15.88%     45.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           160814353     16.64%     61.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           120202627     12.44%     74.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           123594762     12.79%     87.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            73761984      7.63%     94.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            38320993      3.97%     98.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             9885308      1.02%     99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2523549      0.26%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       968083151                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       966231390                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  891948      3.74%      3.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   5659      0.02%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  893685      3.74%      3.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5601      0.02%      3.77% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.77% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.77% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.77% # attempts to use FU when none available
@@ -506,13 +502,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.77% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.77% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.77% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               18285123     76.74%     80.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4644794     19.49%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               18261914     76.52%     80.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4703701     19.71%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1236892590     61.28%     61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               924644      0.05%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1236629707     61.27%     61.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               925874      0.05%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
@@ -534,90 +530,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              35      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              54      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc             20      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              5      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc             25      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult             11      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            587766580     29.12%     90.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           192995535      9.56%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            587570237     29.11%     90.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           193062842      9.57%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2018579412                       # Type of FU issued
-system.cpu.iq.rate                           1.900755                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    23827524                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.011804                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5033085915                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2676877502                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1957286875                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 274                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                546                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          114                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2042406797                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     139                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         64607409                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2018188753                       # Type of FU issued
+system.cpu.iq.rate                           1.909767                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    23864901                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.011825                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5030483281                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2674676202                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1957157350                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 352                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                748                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          139                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2042053478                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     176                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         64607819                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    138731819                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       269264                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       192926                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     45936837                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    138417340                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       267938                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       192339                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     45843051                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4636852                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       4440345                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               69900748                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                32985264                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1607893                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2202176322                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           7875030                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             624658588                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            220783882                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                787                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 480489                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 97297                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         192926                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        8154150                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      9614096                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             17768246                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1987907812                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             573917969                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          30671600                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               69686098                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                32530520                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1603302                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2201068109                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           7883109                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             624344109                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            220690096                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                810                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 479479                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 96880                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         192339                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        8149711                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      9614325                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             17764036                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1987581145                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             573715440                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          30607608                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           115                       # number of nop insts executed
-system.cpu.iew.exec_refs                    764035004                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                238344765                       # Number of branches executed
-system.cpu.iew.exec_stores                  190117035                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.871873                       # Inst execution rate
-system.cpu.iew.wb_sent                     1965721385                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1957286989                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1295353169                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2059124619                       # num instructions consuming a value
+system.cpu.iew.exec_nop                            89                       # number of nop insts executed
+system.cpu.iew.exec_refs                    763896054                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                238343533                       # Number of branches executed
+system.cpu.iew.exec_stores                  190180614                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.880804                       # Inst execution rate
+system.cpu.iew.wb_sent                     1965589817                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1957157489                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1295200215                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2058841803                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.843040                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.629080                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.852015                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.629092                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       479201419                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       478093326                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15218256                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    898182403                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.918401                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.718632                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15216382                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    896545292                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.921904                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.720119                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    409520932     45.59%     45.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    193341126     21.53%     67.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     72856392      8.11%     75.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     35266381      3.93%     79.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     18923261      2.11%     81.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     30757515      3.42%     84.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19970325      2.22%     86.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11453537      1.28%     88.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    106092934     11.81%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    407981027     45.51%     45.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    193272762     21.56%     67.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     72814151      8.12%     75.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     35242500      3.93%     79.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     18951832      2.11%     81.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     30763398      3.43%     84.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19961065      2.23%     86.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11413875      1.27%     88.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106144682     11.84%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    898182403                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    896545292                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1544563041                       # Number of instructions committed
 system.cpu.commit.committedOps             1723073853                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -628,99 +624,133 @@ system.cpu.commit.branches                  213462426                       # Nu
 system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1536941841                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events             106092934                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu       1061599714     61.61%     61.61% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          700322      0.04%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.65% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       485926769     28.20%     89.85% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      174847045     10.15%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total        1723073853                       # Class of committed instruction
+system.cpu.commit.bw_lim_events             106144682                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2994364142                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4474601624                       # The number of ROB writes
-system.cpu.timesIdled                         1160522                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        93905237                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2991567190                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4472170576                       # The number of ROB writes
+system.cpu.timesIdled                         1153872                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        90540825                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563023                       # Number of Instructions Simulated
 system.cpu.committedOps                    1723073835                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1544563023                       # Number of Instructions Simulated
-system.cpu.cpi                               0.687566                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.687566                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.454407                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.454407                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               9955508978                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1937309574                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       108                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      108                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               737568033                       # number of misc regfile reads
+system.cpu.cpi                               0.684188                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.684188                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.461586                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.461586                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               9954183829                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1937102211                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       137                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      142                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               737626428                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1613255878                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        7708873                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7708872                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3782409                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1893555                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1893555                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1549                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22985720                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22987269                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        49536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    856579904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      856629440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         856629440                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus           64                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10474986844                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput              1621046225                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7708753                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7708752                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3781180                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1893479                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1893479                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1556                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22984087                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          22985643                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        49792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    856488512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      856538304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         856538304                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy    10473041845                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1289999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1300248                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14746367742                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14753489741                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.8                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                17                       # number of replacements
-system.cpu.icache.tags.tagsinuse           631.201883                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           289401615                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               772                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          374872.558290                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                20                       # number of replacements
+system.cpu.icache.tags.tagsinuse           629.404083                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           289026911                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               778                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          371499.885604                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   631.201883                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.308204                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.308204                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          755                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   629.404083                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.307326                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.307326                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          758                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          729                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.368652                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         578806417                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        578806417                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    289401622                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       289401622                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     289401622                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        289401622                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    289401622                       # number of overall hits
-system.cpu.icache.overall_hits::total       289401622                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1199                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1199                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1199                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1199                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1199                       # number of overall misses
-system.cpu.icache.overall_misses::total          1199                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     84823499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     84823499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     84823499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     84823499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     84823499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     84823499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    289402821                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    289402821                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    289402821                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    289402821                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    289402821                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    289402821                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          730                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.370117                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         578057010                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        578057010                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    289026911                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       289026911                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     289026911                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        289026911                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    289026911                       # number of overall hits
+system.cpu.icache.overall_hits::total       289026911                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1205                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1205                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1205                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1205                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1205                       # number of overall misses
+system.cpu.icache.overall_misses::total          1205                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     80982998                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     80982998                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     80982998                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     80982998                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     80982998                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     80982998                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    289028116                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    289028116                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    289028116                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    289028116                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    289028116                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    289028116                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70745.203503                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70745.203503                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70745.203503                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70745.203503                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70745.203503                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70745.203503                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67205.807469                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67205.807469                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67205.807469                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67205.807469                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67205.807469                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67205.807469                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          202                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
@@ -729,133 +759,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs    50.500000
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          424                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          424                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          424                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          424                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          424                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          424                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          775                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          775                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          775                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          775                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          775                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          775                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     56494501                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     56494501                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     56494501                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     56494501                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     56494501                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     56494501                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          427                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          427                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          427                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          427                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          427                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          427                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          778                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          778                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          778                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          778                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          778                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          778                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     55589252                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     55589252                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     55589252                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     55589252                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     55589252                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     55589252                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72896.130323                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72896.130323                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72896.130323                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72896.130323                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72896.130323                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72896.130323                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71451.480720                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71451.480720                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71451.480720                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71451.480720                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71451.480720                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71451.480720                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          2213521                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31530.649727                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            9247246                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          2243295                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.122171                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      21629133000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14295.824986                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    20.209231                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 17214.615510                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.436274                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000617                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.525348                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.962239                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29774                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements          2214034                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31529.362843                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            9245387                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2243807                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.120402                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      21611639250                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14288.917834                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    20.667187                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 17219.777822                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.436063                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000631                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.525506                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.962200                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29773                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1889                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        23754                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3955                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908630                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        111215565                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       111215565                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           31                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      6289061                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6289092                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3782409                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3782409                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1067117                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1067117                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           31                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7356178                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7356209                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           31                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7356178                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7356209                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          743                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1419037                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1419780                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       826438                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       826438                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          743                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2245475                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2246218                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          743                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2245475                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2246218                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     55398500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 122091721000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 122147119500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  73834470750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  73834470750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     55398500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 195926191750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 195981590250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     55398500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 195926191750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 195981590250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          774                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7708098                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7708872                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3782409                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3782409                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            3                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            3                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1893555                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1893555                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          774                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9601653                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9602427                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          774                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9601653                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9602427                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.959948                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.184097                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.184175                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.436448                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.436448                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.959948                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.233863                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.233922                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.959948                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.233863                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.233922                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74560.565276                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86038.433811                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 86032.427207                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89340.604800                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89340.604800                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74560.565276                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87253.784500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87249.585859                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74560.565276                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87253.784500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87249.585859                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1894                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        23771                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3939                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908600                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        111204582                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       111204582                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst           27                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      6288484                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6288511                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3781180                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3781180                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1066986                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1066986                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           27                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7355470                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7355497                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           27                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      7355470                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7355497                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          751                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1419491                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1420242                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       826493                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       826493                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          751                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2245984                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2246735                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          751                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2245984                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2246735                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     54536250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 119001772500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 119056308750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  70780259250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  70780259250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     54536250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 189782031750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 189836568000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     54536250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 189782031750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 189836568000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          778                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7707975                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7708753                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3781180                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3781180                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1893479                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1893479                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          778                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9601454                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9602232                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          778                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9601454                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9602232                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.965296                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.184159                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.184238                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.436494                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.436494                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.965296                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.233921                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.233980                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965296                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.233921                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.233980                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72618.175766                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83834.115539                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 83828.184739                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85639.272504                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85639.272504                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72618.175766                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84498.389904                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 84494.418790                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72618.175766                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84498.389904                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 84494.418790                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -864,195 +890,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1100304                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1100304                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            8                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            9                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            9                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            8                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            9                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          742                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1419029                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1419771                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       826438                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       826438                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          742                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2245467                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2246209                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          742                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2245467                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2246209                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     45997000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 104316352250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 104362349250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  63474835750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  63474835750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     45997000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 167791188000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 167837185000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     45997000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 167791188000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 167837185000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.958656                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.184096                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.184174                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.436448                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.436448                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.958656                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.233863                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.233921                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.958656                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.233863                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.233921                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61990.566038                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73512.487941                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73506.466360                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76805.320847                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76805.320847                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61990.566038                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74724.406103                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74720.199679                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61990.566038                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74724.406103                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74720.199679                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks      1100540                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1100540                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            9                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           11                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           11                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           11                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          749                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1419482                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1420231                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       826493                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       826493                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          749                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2245975                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2246724                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          749                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2245975                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2246724                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     44958250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101218844750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101263803000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60411500250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60411500250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     44958250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 161630345000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 161675303250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     44958250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 161630345000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 161675303250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.962725                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.184158                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.184236                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.436494                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.436494                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.962725                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.233920                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.233979                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.962725                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.233920                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.233979                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60024.365821                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71306.888534                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71300.938368                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73093.783311                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73093.783311                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60024.365821                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71964.445285                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71960.464770                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60024.365821                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71964.445285                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71960.464770                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9597556                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4088.017894                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           656035033                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9601652                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             68.325225                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        3543401250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4088.017894                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998051                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998051                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9597357                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.971590                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           656031329                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9601453                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             68.326255                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        3540268250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.971590                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998040                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998040                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          619                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2366                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1110                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          640                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2362                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1093                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1355956994                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1355956994                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    489079777                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       489079777                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    166955126                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      166955126                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           64                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           64                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses        1355949467                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1355949467                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    489075849                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       489075849                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    166955354                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      166955354                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           65                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           65                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     656034903                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        656034903                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    656034903                       # number of overall hits
-system.cpu.dcache.overall_hits::total       656034903                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     11511719                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      11511719                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5630921                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5630921                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     656031203                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        656031203                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    656031203                       # number of overall hits
+system.cpu.dcache.overall_hits::total       656031203                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     11511982                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      11511982                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5630693                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5630693                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     17142640                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       17142640                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     17142640                       # number of overall misses
-system.cpu.dcache.overall_misses::total      17142640                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 356637028987                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 356637028987                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 299385068793                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 299385068793                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       231500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       231500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 656022097780                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 656022097780                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 656022097780                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 656022097780                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    500591496                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    500591496                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     17142675                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       17142675                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     17142675                       # number of overall misses
+system.cpu.dcache.overall_misses::total      17142675                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 350608925483                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 350608925483                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 296498774019                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 296498774019                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       225500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       225500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 647107699502                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 647107699502                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 647107699502                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 647107699502                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    500587831                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    500587831                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           67                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           67                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           68                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           68                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    673177543                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    673177543                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    673177543                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    673177543                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022996                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.022996                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032627                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032627                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.044776                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.044776                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    673173878                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    673173878                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    673173878                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    673173878                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022997                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.022997                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032625                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032625                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.044118                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.044118                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.025465                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.025465                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.025465                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.025465                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30980.345245                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30980.345245                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53168.046363                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53168.046363                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77166.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77166.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38268.440437                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38268.440437                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38268.440437                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38268.440437                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     23433940                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3966170                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1210564                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30456.000147                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30456.000147                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52657.598988                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 52657.598988                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37748.350214                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37748.350214                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37748.350214                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37748.350214                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     22019527                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3996591                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1208409                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets           65132                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    19.357870                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    60.894338                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    18.221916                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    61.361405                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3782409                       # number of writebacks
-system.cpu.dcache.writebacks::total           3782409                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3803620                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3803620                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3737364                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3737364                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      3781180                       # number of writebacks
+system.cpu.dcache.writebacks::total           3781180                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3804007                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3804007                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3737214                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3737214                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      7540984                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      7540984                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      7540984                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      7540984                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7708099                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7708099                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1893557                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1893557                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9601656                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9601656                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9601656                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9601656                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194575797258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 194575797258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  86895396246                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  86895396246                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 281471193504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 281471193504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 281471193504                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 281471193504                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data      7541221                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      7541221                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      7541221                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      7541221                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7707975                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7707975                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1893479                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1893479                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9601454                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9601454                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9601454                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9601454                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191480901509                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 191480901509                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83841557570                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  83841557570                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275322459079                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 275322459079                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275322459079                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 275322459079                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015398                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015398                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010972                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010972                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010971                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010971                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014263                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014263                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014263                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014263                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25243.032978                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25243.032978                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45890.034599                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45890.034599                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29314.859177                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29314.859177                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29314.859177                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29314.859177                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24841.920415                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24841.920415                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44279.106116                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44279.106116                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28675.079741                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28675.079741                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28675.079741                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28675.079741                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index c3140695a..38623e444 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.861538                       # Nu
 sim_ticks                                861538200000                       # Number of ticks simulated
 final_tick                               861538200000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2200753                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2455102                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1227552560                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258852                       # Number of bytes of host memory used
-host_seconds                                   701.83                       # Real time elapsed on the host
+host_inst_rate                                1785934                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1992340                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              996171702                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 301680                       # Number of bytes of host memory used
+host_seconds                                   864.85                       # Real time elapsed on the host
 sim_insts                                  1544563041                       # Number of instructions simulated
 sim_ops                                    1723073853                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,5 +147,40 @@ system.cpu.num_busy_cycles                 1723076401                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         213462426                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                1061599760     61.61%     61.61% # Class of executed instruction
+system.cpu.op_class::IntMult                   700322      0.04%     61.65% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::MemRead                485926769     28.20%     89.85% # Class of executed instruction
+system.cpu.op_class::MemWrite               174847046     10.15%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 1723073900                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 77908b2aa..de9b22f80 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.391205                       # Nu
 sim_ticks                                2391205115000                       # Number of ticks simulated
 final_tick                               2391205115000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1176543                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1313033                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1828326739                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 268744                       # Number of bytes of host memory used
-host_seconds                                  1307.87                       # Real time elapsed on the host
+host_inst_rate                                 867002                       # Simulator instruction rate (inst/s)
+host_op_rate                                   967582                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1347305237                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 310408                       # Number of bytes of host memory used
+host_seconds                                  1774.81                       # Real time elapsed on the host
 sim_insts                                  1538759601                       # Number of instructions simulated
 sim_ops                                    1717270334                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -161,6 +161,41 @@ system.cpu.num_busy_cycles                 4782410230                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         213462426                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                1061599760     61.61%     61.61% # Class of executed instruction
+system.cpu.op_class::IntMult                   700322      0.04%     61.65% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     61.65% # Class of executed instruction
+system.cpu.op_class::MemRead                485926769     28.20%     89.85% # Class of executed instruction
+system.cpu.op_class::MemWrite               174847046     10.15%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 1723073900                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 7                       # number of replacements
 system.cpu.icache.tags.tagsinuse           514.976015                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1544564952                       # Total number of references to valid blocks.
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index e876090ca..84901d870 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.846007                       # Nu
 sim_ticks                                2846007227500                       # Number of ticks simulated
 final_tick                               2846007227500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1097459                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1709940                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1038328376                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292828                       # Number of bytes of host memory used
-host_seconds                                  2740.95                       # Real time elapsed on the host
+host_inst_rate                                1186122                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1848085                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1122213991                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278740                       # Number of bytes of host memory used
+host_seconds                                  2536.06                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -66,5 +66,40 @@ system.cpu.num_busy_cycles                 5692014456                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         248500691                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               2494522      0.05%      0.05% # Class of executed instruction
+system.cpu.op_class::IntAlu                3006647871     64.15%     64.20% # Class of executed instruction
+system.cpu.op_class::IntMult                     6215      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::IntDiv                       904      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::MemRead               1239184746     26.44%     90.64% # Class of executed instruction
+system.cpu.op_class::MemWrite               438528338      9.36%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 4686862596                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 119344b4f..bc5edc6ef 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.882581                       # Nu
 sim_ticks                                5882580526000                       # Number of ticks simulated
 final_tick                               5882580526000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 532297                       # Simulator instruction rate (inst/s)
-host_op_rate                                   829367                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1040955661                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302560                       # Number of bytes of host memory used
-host_seconds                                  5651.13                       # Real time elapsed on the host
+host_inst_rate                                 693030                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1079804                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1355284560                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 288492                       # Number of bytes of host memory used
+host_seconds                                  4340.48                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -82,6 +82,41 @@ system.cpu.num_busy_cycles                11765161052                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         248500691                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               2494522      0.05%      0.05% # Class of executed instruction
+system.cpu.op_class::IntAlu                3006647871     64.15%     64.20% # Class of executed instruction
+system.cpu.op_class::IntMult                     6215      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::IntDiv                       904      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.20% # Class of executed instruction
+system.cpu.op_class::MemRead               1239184746     26.44%     90.64% # Class of executed instruction
+system.cpu.op_class::MemWrite               438528338      9.36%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                 4686862596                       # Class of executed instruction
 system.cpu.icache.tags.replacements                10                       # number of replacements
 system.cpu.icache.tags.tagsinuse           555.705054                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          4013232208                       # Total number of references to valid blocks.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 17c346b69..bb082f445 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.041684                       # Number of seconds simulated
-sim_ticks                                 41683573000                       # Number of ticks simulated
-final_tick                                41683573000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.041682                       # Number of seconds simulated
+sim_ticks                                 41681685000                       # Number of ticks simulated
+final_tick                                41681685000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 119929                       # Simulator instruction rate (inst/s)
-host_op_rate                                   119929                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               54395175                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269084                       # Number of bytes of host memory used
-host_seconds                                   766.31                       # Real time elapsed on the host
+host_inst_rate                                 117228                       # Simulator instruction rate (inst/s)
+host_op_rate                                   117228                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53167547                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 270132                       # Number of bytes of host memory used
+host_seconds                                   783.97                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          178816                       # Nu
 system.physmem.num_reads::cpu.inst               2794                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2144                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  4938                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              4289843                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3291848                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 7581692                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         4289843                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            4289843                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             4289843                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3291848                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7581692                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              4290038                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3291997                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7582035                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         4290038                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            4290038                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             4290038                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3291997                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7582035                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          4938                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        4938                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     41683192000                       # Total gap between requests
+system.physmem.totGap                     41681611000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                      3265                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       435                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        77                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1049                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       546                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        74                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -186,28 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          284                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      541.521127                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     335.427822                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     417.351632                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             58     20.42%     20.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           54     19.01%     39.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           24      8.45%     47.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           12      4.23%     52.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           10      3.52%     55.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            9      3.17%     58.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            5      1.76%     60.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            5      1.76%     62.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          107     37.68%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            284                       # Bytes accessed per row activation
-system.physmem.totQLat                       37971250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 131493750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          856                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      367.551402                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     223.659981                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     343.121338                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            258     30.14%     30.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          183     21.38%     51.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           95     11.10%     62.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           63      7.36%     69.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           46      5.37%     75.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           30      3.50%     78.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           51      5.96%     84.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           22      2.57%     87.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          108     12.62%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            856                       # Bytes accessed per row activation
+system.physmem.totQLat                       35422000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 128009500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     24690000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    68832500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        7689.60                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13939.35                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        7173.35                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26628.95                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25923.35                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           7.58                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        7.58                       # Average system read bandwidth in MiByte/s
@@ -218,14 +216,18 @@ system.physmem.busUtilRead                       0.06                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4086                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4077                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.75                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   82.56                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8441310.65                       # Average gap between requests
-system.physmem.pageHitRate                      82.75                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               1.04                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      7581692                       # Throughput (bytes/s)
+system.physmem.avgGap                      8440990.48                       # Average gap between requests
+system.physmem.pageHitRate                      82.56                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      39211333500                       # Time in different power states
+system.physmem.memoryStateTime::REF        1391780000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1076956500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      7582035                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                3216                       # Transaction distribution
 system.membus.trans_dist::ReadResp               3216                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1722                       # Transaction distribution
@@ -236,40 +238,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              316032                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 316032                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             5776500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             5782000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           45941000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           45945000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                13412627                       # Number of BP lookups
+system.cpu.branchPred.lookups                13412628                       # Number of BP lookups
 system.cpu.branchPred.condPredicted           9650146                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           4269214                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              7424479                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 3768497                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups              7424480                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 3768498                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             50.757730                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             50.757737                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 1029619                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                126                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     19996264                       # DTB read hits
+system.cpu.dtb.read_hits                     19996260                       # DTB read hits
 system.cpu.dtb.read_misses                         10                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 19996274                       # DTB read accesses
-system.cpu.dtb.write_hits                     6501866                       # DTB write hits
+system.cpu.dtb.read_accesses                 19996270                       # DTB read accesses
+system.cpu.dtb.write_hits                     6501862                       # DTB write hits
 system.cpu.dtb.write_misses                        23                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6501889                       # DTB write accesses
-system.cpu.dtb.data_hits                     26498130                       # DTB hits
+system.cpu.dtb.write_accesses                 6501885                       # DTB write accesses
+system.cpu.dtb.data_hits                     26498122                       # DTB hits
 system.cpu.dtb.data_misses                         33                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 26498163                       # DTB accesses
-system.cpu.itb.fetch_hits                     9956950                       # ITB hits
+system.cpu.dtb.data_accesses                 26498155                       # DTB accesses
+system.cpu.itb.fetch_hits                     9956951                       # ITB hits
 system.cpu.itb.fetch_misses                        49                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                 9956999                       # ITB accesses
+system.cpu.itb.fetch_accesses                 9957000                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -283,10 +285,10 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         83367147                       # number of cpu cycles simulated
+system.cpu.numCycles                         83363371                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken      5905662                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedTaken      5905663                       # Number of Branches Predicted As Taken (True).
 system.cpu.branch_predictor.predictedNotTaken      7506965                       # Number of Branches Predicted As Not Taken (False).
 system.cpu.regfile_manager.intRegFileReads     73570553                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites     62575472                       # Number of Writes to Int. Register File
@@ -305,12 +307,12 @@ system.cpu.execution_unit.executions         57404027                       # Nu
 system.cpu.mult_div_unit.multiplies            458253                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                      82970332                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                      82970271                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                           10410                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7759392                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                         75607755                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         90.692506                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                           10393                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7755613                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         75607758                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         90.696618                       # Percentage of cycles cpu is active
 system.cpu.comLoads                          19996198                       # Number of Load instructions committed
 system.cpu.comStores                          6501103                       # Number of Store instructions committed
 system.cpu.comBranches                       10240685                       # Number of Branches instructions committed
@@ -322,36 +324,36 @@ system.cpu.committedInsts                    91903056                       # Nu
 system.cpu.committedOps                      91903056                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total              91903056                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.907121                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               0.907079                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.907121                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.102389                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         0.907079                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.102439                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.102389                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                 27686803                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                  55680344                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               66.789312                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                 34115467                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                  49251680                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               59.078044                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                 33515800                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         1.102439                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                 27683021                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  55680350                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               66.792345                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 34111687                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  49251684                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               59.080725                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 33512024                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                  49851347                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               59.797353                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                 65340657                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                  18026490                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               21.623014                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                 29507392                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization               59.800061                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 65336871                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  18026500                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               21.624006                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 29503616                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                  53859755                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               64.605491                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization               64.608418                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements              7635                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1492.188372                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1492.194030                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs             9945551                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              9520                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs           1044.700735                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1492.188372                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.728608                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.728608                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1492.194030                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.728610                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.728610                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1885                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
@@ -359,44 +361,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          613
 system.cpu.icache.tags.age_task_id_blocks_1024::3          136                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          959                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.920410                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          19923420                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         19923420                       # Number of data accesses
+system.cpu.icache.tags.tag_accesses          19923422                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         19923422                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst      9945551                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total         9945551                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst       9945551                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total          9945551                       # number of demand (read+write) hits
 system.cpu.icache.overall_hits::cpu.inst      9945551                       # number of overall hits
 system.cpu.icache.overall_hits::total         9945551                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        11399                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         11399                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        11399                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          11399                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        11399                       # number of overall misses
-system.cpu.icache.overall_misses::total         11399                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    329283500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    329283500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    329283500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    329283500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    329283500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    329283500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9956950                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9956950                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9956950                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9956950                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9956950                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9956950                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst        11400                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         11400                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        11400                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          11400                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        11400                       # number of overall misses
+system.cpu.icache.overall_misses::total         11400                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    327908250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    327908250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    327908250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    327908250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    327908250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    327908250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9956951                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9956951                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9956951                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9956951                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9956951                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9956951                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001145                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.001145                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.001145                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.001145                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001145                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001145                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28887.051496                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28887.051496                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28887.051496                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28887.051496                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28887.051496                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28887.051496                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28763.881579                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28763.881579                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28763.881579                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28763.881579                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28763.881579                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28763.881579                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            7                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -405,38 +407,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs            7
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1879                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1879                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1879                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1879                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1879                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1879                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1880                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1880                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1880                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1880                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1880                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1880                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         9520                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         9520                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         9520                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total         9520                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         9520                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         9520                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    268822750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    268822750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    268822750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    268822750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    268822750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    268822750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    268503000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    268503000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    268503000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    268503000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    268503000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    268503000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000956                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000956                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000956                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000956                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000956                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000956                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28237.683824                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28237.683824                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28237.683824                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28237.683824                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28237.683824                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28237.683824                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28204.096639                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28204.096639                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28204.096639                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 28204.096639                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28204.096639                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 28204.096639                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                18194218                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput                18195042                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq           9995                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          9995                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
@@ -452,21 +454,21 @@ system.cpu.toL2Bus.data_through_bus            758400                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy        6032000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      14800250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      14805000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3515750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3522500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2189.597840                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         2189.603987                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               6793                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3282                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             2.069775                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.844631                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1820.766792                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   350.986416                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.844250                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1820.772066                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   350.987671                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000545                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055565                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055566                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.010711                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.066821                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         3282                       # Occupied blocks per task id
@@ -502,17 +504,17 @@ system.cpu.l2cache.demand_misses::total          4938                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2794                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2144                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         4938                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    191765250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32319750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    224085000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    125611500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    125611500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    191765250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    157931250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    349696500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    191765250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    157931250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    349696500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    191445500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     31242750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    222688250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    121662250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    121662250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    191445500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    152905000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    344350500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    191445500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    152905000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    344350500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         9520                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          475                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         9995                       # number of ReadReq accesses(hits+misses)
@@ -537,17 +539,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.420506                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.293487                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964462                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.420506                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68634.663565                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76587.085308                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69678.171642                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72945.121951                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72945.121951                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68634.663565                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73661.963619                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70817.436209                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68634.663565                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73661.963619                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70817.436209                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68520.221904                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74034.952607                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69243.858831                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70651.713124                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70651.713124                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68520.221904                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71317.630597                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69734.811665                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68520.221904                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71317.630597                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69734.811665                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -567,17 +569,17 @@ system.cpu.l2cache.demand_mshr_misses::total         4938
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2794                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2144                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         4938                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    156642750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     27057250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    183700000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    104540000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    104540000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    156642750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    131597250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    288240000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    156642750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    131597250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    288240000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    156316500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     25982750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    182299250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    100579250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    100579250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    156316500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    126562000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    282878500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    156316500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    126562000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    282878500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.293487                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.888421                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.321761                       # mshr miss rate for ReadReq accesses
@@ -589,25 +591,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.420506
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.293487                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.420506                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56063.976378                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64116.706161                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57120.646766                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60708.478513                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60708.478513                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.976378                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61379.314366                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58371.810450                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.976378                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61379.314366                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58371.810450                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55947.208304                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61570.497630                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56685.090174                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58408.391405                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58408.391405                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55947.208304                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59030.783582                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57286.046983                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55947.208304                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59030.783582                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57286.046983                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1441.382253                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26488456                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1441.383569                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26488452                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2223                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11915.634728                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11915.632928                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1441.382253                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  1441.383569                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.351900                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.351900                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2066                       # Occupied blocks per task id
@@ -619,30 +621,30 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4         1372
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.504395                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          52996825                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         52996825                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     19995621                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        19995621                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492835                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492835                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      26488456                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26488456                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26488456                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26488456                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          577                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           577                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8268                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8268                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         8845                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           8845                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         8845                       # number of overall misses
-system.cpu.dcache.overall_misses::total          8845                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     40979500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     40979500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    507652000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    507652000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    548631500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    548631500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    548631500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    548631500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_hits::cpu.data     19995619                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        19995619                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492833                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492833                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      26488452                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26488452                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26488452                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26488452                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          579                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           579                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8270                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8270                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         8849                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           8849                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         8849                       # number of overall misses
+system.cpu.dcache.overall_misses::total          8849                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     39903000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     39903000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    493053000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    493053000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    532956000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    532956000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    532956000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    532956000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
@@ -659,32 +661,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000334
 system.cpu.dcache.demand_miss_rate::total     0.000334                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000334                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000334                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71021.663778                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71021.663778                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61399.612966                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61399.612966                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62027.303561                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62027.303561                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62027.303561                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62027.303561                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        25755                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68917.098446                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68917.098446                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59619.467956                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59619.467956                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 60227.822353                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 60227.822353                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60227.822353                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60227.822353                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        24052                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               844                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               836                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.515403                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    28.770335                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          102                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          102                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6520                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6520                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         6622                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         6622                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         6622                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         6622                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          104                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          104                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6522                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6522                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         6626                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         6626                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         6626                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         6626                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          475                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          475                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1748                       # number of WriteReq MSHR misses
@@ -693,14 +695,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2223
 system.cpu.dcache.demand_mshr_misses::total         2223                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2223                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2223                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     33343250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     33343250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    127629000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    127629000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    160972250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    160972250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    160972250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    160972250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     32266250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     32266250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    123679750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    123679750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    155946000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    155946000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    155946000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    155946000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000269                       # mshr miss rate for WriteReq accesses
@@ -709,14 +711,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70196.315789                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70196.315789                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73014.302059                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73014.302059                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72412.168241                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72412.168241                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72412.168241                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72412.168241                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67928.947368                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67928.947368                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70755.005721                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70755.005721                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70151.147099                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 70151.147099                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70151.147099                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 70151.147099                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index c3a9e9ab9..c2ef654cc 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,60 +1,60 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.023455                       # Number of seconds simulated
-sim_ticks                                 23455364500                       # Number of ticks simulated
-final_tick                                23455364500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.023496                       # Number of seconds simulated
+sim_ticks                                 23495860500                       # Number of ticks simulated
+final_tick                                23495860500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 164985                       # Simulator instruction rate (inst/s)
-host_op_rate                                   164985                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               45970553                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 272156                       # Number of bytes of host memory used
-host_seconds                                   510.23                       # Real time elapsed on the host
+host_inst_rate                                 162171                       # Simulator instruction rate (inst/s)
+host_op_rate                                   162171                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               45264552                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273204                       # Number of bytes of host memory used
+host_seconds                                   519.08                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            195968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            138624                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               334592                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       195968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          195968                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3062                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2166                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5228                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8354933                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              5910119                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14265052                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8354933                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8354933                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8354933                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5910119                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               14265052                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5228                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            196096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            138432                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               334528                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       196096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          196096                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3064                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5227                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              8345981                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              5891761                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14237742                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8345981                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8345981                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8345981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5891761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               14237742                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5227                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5228                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5227                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   334592                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   334528                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    334592                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    334528                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 469                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 290                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 301                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 519                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 291                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 302                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 524                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 220                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 227                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 226                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 220                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 288                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 285                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 236                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 280                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                248                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                255                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                401                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                338                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                254                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                398                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                336                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                491                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                447                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     23455237500                       # Total gap between requests
+system.physmem.totGap                     23495733500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5228                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5227                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1321                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       517                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1191                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       631                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                       112                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,90 +186,92 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          339                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      526.348083                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     311.933424                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     425.197716                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             81     23.89%     23.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           64     18.88%     42.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           21      6.19%     48.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           17      5.01%     53.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            9      2.65%     56.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            8      2.36%     59.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            7      2.06%     61.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            3      0.88%     61.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          129     38.05%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            339                       # Bytes accessed per row activation
-system.physmem.totQLat                       42838250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 141220750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26140000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    72242500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8194.00                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13818.38                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples          867                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      383.188005                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     230.923786                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     354.572905                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            252     29.07%     29.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          197     22.72%     51.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           79      9.11%     60.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           57      6.57%     67.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           42      4.84%     72.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           41      4.73%     77.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           51      5.88%     82.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           24      2.77%     85.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          124     14.30%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            867                       # Bytes accessed per row activation
+system.physmem.totQLat                       41053500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 139059750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26135000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7854.12                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27012.39                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          14.27                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26604.12                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          14.24                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       14.27                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       14.24                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.11                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4346                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4351                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.13                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.24                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4486464.71                       # Average gap between requests
-system.physmem.pageHitRate                      83.13                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               1.10                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     14265052                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                3523                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3523                       # Transaction distribution
+system.physmem.avgGap                      4495070.50                       # Average gap between requests
+system.physmem.pageHitRate                      83.24                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      21787630000                       # Time in different power states
+system.physmem.memoryStateTime::REF         784420000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT         919340000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     14237742                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                3522                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3522                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1705                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1705                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10456                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10456                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              334592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 334592                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10454                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10454                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              334528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 334528                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             6760500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             6755000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           48963750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           48973500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14848335                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10770516                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            922016                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8296689                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6955595                       # Number of BTB hits
+system.cpu.branchPred.lookups                14867597                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10786733                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            927657                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8507235                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6975722                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.835793                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1468520                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3112                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             81.997523                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1468896                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3134                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     23116922                       # DTB read hits
-system.cpu.dtb.read_misses                     193562                       # DTB read misses
-system.cpu.dtb.read_acv                             4                       # DTB read access violations
-system.cpu.dtb.read_accesses                 23310484                       # DTB read accesses
-system.cpu.dtb.write_hits                     7068693                       # DTB write hits
-system.cpu.dtb.write_misses                      1118                       # DTB write misses
-system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7069811                       # DTB write accesses
-system.cpu.dtb.data_hits                     30185615                       # DTB hits
-system.cpu.dtb.data_misses                     194680                       # DTB misses
-system.cpu.dtb.data_acv                             6                       # DTB access violations
-system.cpu.dtb.data_accesses                 30380295                       # DTB accesses
-system.cpu.itb.fetch_hits                    14732180                       # ITB hits
-system.cpu.itb.fetch_misses                       100                       # ITB misses
+system.cpu.dtb.read_hits                     23141508                       # DTB read hits
+system.cpu.dtb.read_misses                     194908                       # DTB read misses
+system.cpu.dtb.read_acv                             2                       # DTB read access violations
+system.cpu.dtb.read_accesses                 23336416                       # DTB read accesses
+system.cpu.dtb.write_hits                     7073051                       # DTB write hits
+system.cpu.dtb.write_misses                      1111                       # DTB write misses
+system.cpu.dtb.write_acv                            1                       # DTB write access violations
+system.cpu.dtb.write_accesses                 7074162                       # DTB write accesses
+system.cpu.dtb.data_hits                     30214559                       # DTB hits
+system.cpu.dtb.data_misses                     196019                       # DTB misses
+system.cpu.dtb.data_acv                             3                       # DTB access violations
+system.cpu.dtb.data_accesses                 30410578                       # DTB accesses
+system.cpu.itb.fetch_hits                    14761442                       # ITB hits
+system.cpu.itb.fetch_misses                       106                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                14732280                       # ITB accesses
+system.cpu.itb.fetch_accesses                14761548                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -283,238 +285,238 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         46910730                       # number of cpu cycles simulated
+system.cpu.numCycles                         46991722                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15458006                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      126949517                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14848335                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            8424115                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      22129467                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4471319                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                5547804                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  111                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2176                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           15493602                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      127144789                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14867597                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            8444618                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22164191                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4494518                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                5543985                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  114                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2326                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  14732180                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                325492                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           46652781                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.721156                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.376288                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  14761442                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                326314                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           46736650                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.720451                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.375825                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24523314     52.57%     52.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2362460      5.06%     57.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1191709      2.55%     60.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1744531      3.74%     63.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2756035      5.91%     69.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1149513      2.46%     72.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1216156      2.61%     74.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   771099      1.65%     76.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 10937964     23.45%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 24572459     52.58%     52.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2364267      5.06%     57.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1190852      2.55%     60.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1750659      3.75%     63.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2760354      5.91%     69.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1155374      2.47%     72.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1219764      2.61%     74.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   773397      1.65%     76.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 10949524     23.43%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             46652781                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.316523                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.706194                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17279755                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               4249359                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  20525557                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1094653                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3503457                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2516236                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12079                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              123971467                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 32460                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3503457                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18421615                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  960025                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           8092                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20456033                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3303559                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              121144333                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    76                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 398869                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2427038                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            88958437                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             157404324                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        150359413                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           7044910                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             46736650                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.316388                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.705685                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17320813                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               4244089                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  20558459                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1092640                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3520649                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2518881                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12242                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              124135665                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 32164                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3520649                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 18467014                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  956444                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7682                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20482522                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3302339                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              121292511                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    99                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 405307                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2418029                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            89077183                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             157604141                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        150534696                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           7069444                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 20531076                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                753                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            746                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   8762869                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             25364686                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8245053                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2579677                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           916866                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  105436349                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1901                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  96572685                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            177506                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        20788885                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     15603704                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1512                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      46652781                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.070031                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.877189                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 20649822                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                718                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            707                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8775432                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             25394818                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8253633                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2570331                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           907077                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  105549830                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2075                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  96657653                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            179218                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        20902238                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     15662437                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1686                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      46736650                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.068134                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.876130                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            12130850     26.00%     26.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             9330795     20.00%     46.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             8389374     17.98%     63.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6281972     13.47%     77.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4924466     10.56%     88.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2864469      6.14%     94.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1724344      3.70%     97.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              801135      1.72%     99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              205376      0.44%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            12165151     26.03%     26.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             9350062     20.01%     46.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             8404811     17.98%     64.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6298333     13.48%     77.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4922419     10.53%     88.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2869013      6.14%     94.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1725015      3.69%     97.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              796629      1.70%     99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              205217      0.44%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        46652781                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        46736650                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  187827     11.99%     11.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   195      0.01%     12.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     12.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  7087      0.45%     12.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                 5615      0.36%     12.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                842803     53.78%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 445934     28.46%     95.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                 77665      4.96%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  189767     12.10%     12.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     12.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     12.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   186      0.01%     12.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     12.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  7209      0.46%     12.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                 5897      0.38%     12.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                843167     53.74%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 445094     28.37%     95.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                 77619      4.95%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              58739096     60.82%     60.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               479860      0.50%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2798014      2.90%     64.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115391      0.12%     64.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2386555      2.47%     66.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             310970      0.32%     67.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              759904      0.79%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             23830824     24.68%     92.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7151745      7.41%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              58783696     60.82%     60.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               479813      0.50%     61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2802274      2.90%     64.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115457      0.12%     64.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2387860      2.47%     66.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             311147      0.32%     67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              760157      0.79%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             23859982     24.69%     92.60% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7156941      7.40%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               96572685                       # Type of FU issued
-system.cpu.iq.rate                           2.058648                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1567126                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.016227                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          226432918                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         117523015                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     87074868                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15109865                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            8738386                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7061397                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               90154911                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 7984893                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1517468                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               96657653                       # Type of FU issued
+system.cpu.iq.rate                           2.056908                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1568939                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016232                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          226667825                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         117702286                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87133167                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15132288                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            8786528                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7070448                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               90230128                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 7996457                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1520956                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      5368488                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        18513                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        34393                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1743950                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      5398620                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        18484                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        34785                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1752530                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        10556                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          2089                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        10530                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          2127                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3503457                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  134155                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 17977                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           115673905                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            371989                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              25364686                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8245053                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1901                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   2671                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    35                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          34393                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         533358                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       495038                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1028396                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              95341973                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23310954                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1230712                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3520649                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  133897                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 18217                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           115793083                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            374761                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              25394818                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8253633                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               2075                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2932                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    43                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          34785                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         541104                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       495336                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1036440                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              95417746                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23336859                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1239907                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      10235655                       # number of nop insts executed
-system.cpu.iew.exec_refs                     30380968                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12023807                       # Number of branches executed
-system.cpu.iew.exec_stores                    7070014                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.032413                       # Inst execution rate
-system.cpu.iew.wb_sent                       94656410                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      94136265                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  64475750                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  89852391                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      10241178                       # number of nop insts executed
+system.cpu.iew.exec_refs                     30411225                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12030179                       # Number of branches executed
+system.cpu.iew.exec_stores                    7074366                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.030522                       # Inst execution rate
+system.cpu.iew.wb_sent                       94727613                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      94203615                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  64511907                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  89904657                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.006711                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.717574                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.004685                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.717559                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        23771863                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        23891142                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            910264                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     43149324                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.129884                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.746526                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            915882                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     43216001                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.126598                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.743951                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     16704227     38.71%     38.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      9920088     22.99%     61.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4481212     10.39%     72.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2253745      5.22%     77.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1606057      3.72%     81.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1123881      2.60%     83.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       722151      1.67%     85.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       820935      1.90%     87.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5517028     12.79%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     16755601     38.77%     38.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      9919008     22.95%     61.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4484606     10.38%     72.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2269127      5.25%     77.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1610437      3.73%     81.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1128955      2.61%     83.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       722092      1.67%     85.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       821021      1.90%     87.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5505154     12.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     43149324                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     43216001                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -525,230 +527,264 @@ system.cpu.commit.branches                   10240685                       # Nu
 system.cpu.commit.fp_insts                    6862061                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5517028                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass      7723353      8.40%      8.40% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         51001542     55.49%     63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          458252      0.50%     64.40% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     64.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd        2732464      2.97%     67.37% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp         104605      0.11%     67.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt        2333953      2.54%     70.02% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult        296445      0.32%     70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv         754822      0.82%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt           318      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.17% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        19996198     21.76%     92.93% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5505154                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    153306174                       # The number of ROB reads
-system.cpu.rob.rob_writes                   234877097                       # The number of ROB writes
-system.cpu.timesIdled                            5272                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          257949                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    153504004                       # The number of ROB reads
+system.cpu.rob.rob_writes                   235133069                       # The number of ROB writes
+system.cpu.timesIdled                            5418                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          255072                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
-system.cpu.cpi                               0.557269                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.557269                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.794466                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.794466                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                129050731                       # number of integer regfile reads
-system.cpu.int_regfile_writes                70522819                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6187407                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6043154                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  714454                       # number of misc regfile reads
+system.cpu.cpi                               0.558231                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.558231                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.791373                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.791373                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                129151691                       # number of integer regfile reads
+system.cpu.int_regfile_writes                70572840                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6193374                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6052358                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  714605                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                37351626                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          11849                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         11849                       # Transaction distribution
+system.cpu.toL2Bus.throughput                37684936                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          11995                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         11995                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          109                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1731                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1731                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22666                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4603                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             27269                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       725312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         876096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            876096                       # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22964                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4597                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             27561                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       734848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         885440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            885440                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        6953500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy        7026500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      17562000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      17802750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3539750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3545000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              9398                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1599.250917                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            14718111                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             11333                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1298.695050                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              9548                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1597.278061                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            14747183                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11482                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1284.374064                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1599.250917                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.780884                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.780884                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1935                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1597.278061                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.779921                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.779921                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1934                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          761                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          760                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          929                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.944824                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          29475691                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         29475691                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     14718111                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        14718111                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      14718111                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         14718111                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     14718111                       # number of overall hits
-system.cpu.icache.overall_hits::total        14718111                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        14068                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         14068                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        14068                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          14068                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        14068                       # number of overall misses
-system.cpu.icache.overall_misses::total         14068                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    413989500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    413989500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    413989500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    413989500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    413989500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    413989500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     14732179                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     14732179                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     14732179                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     14732179                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     14732179                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     14732179                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000955                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000955                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000955                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000955                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000955                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000955                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29427.743816                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29427.743816                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29427.743816                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29427.743816                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29427.743816                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29427.743816                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          165                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::4          930                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.944336                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          29534364                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         29534364                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     14747183                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        14747183                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      14747183                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         14747183                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     14747183                       # number of overall hits
+system.cpu.icache.overall_hits::total        14747183                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        14258                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         14258                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        14258                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          14258                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        14258                       # number of overall misses
+system.cpu.icache.overall_misses::total         14258                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    414157250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    414157250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    414157250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    414157250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    414157250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    414157250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     14761441                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     14761441                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     14761441                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     14761441                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     14761441                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     14761441                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000966                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000966                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000966                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000966                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000966                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000966                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29047.359377                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 29047.359377                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 29047.359377                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 29047.359377                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 29047.359377                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 29047.359377                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          308                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    41.250000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    61.600000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2735                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2735                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2735                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2735                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2735                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2735                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11333                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        11333                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        11333                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        11333                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        11333                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        11333                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    305304500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    305304500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    305304500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    305304500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    305304500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    305304500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000769                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000769                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000769                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000769                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000769                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000769                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26939.424689                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26939.424689                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26939.424689                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 26939.424689                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26939.424689                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 26939.424689                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2776                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2776                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2776                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2776                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2776                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2776                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11482                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        11482                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        11482                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        11482                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        11482                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        11482                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    306274750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    306274750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    306274750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    306274750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    306274750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    306274750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000778                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000778                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000778                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000778                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000778                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000778                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26674.338094                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26674.338094                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26674.338094                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 26674.338094                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26674.338094                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 26674.338094                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2413.657208                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               8341                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3590                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.323398                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2409.001155                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               8488                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3589                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.365004                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.675331                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2012.279201                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   383.702676                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.673690                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2011.868133                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   379.459331                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000539                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061410                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.011710                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.073659                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3590                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          904                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2435                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109558                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           114833                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          114833                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8271                       # number of ReadReq hits
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061397                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.011580                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.073517                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3589                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          909                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2431                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109528                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           116000                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          116000                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8418                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           55                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           8326                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           8473                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks          109                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          109                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8271                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         8418                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           81                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            8352                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8271                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            8499                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8418                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           81                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           8352                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3062                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          461                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3523                       # number of ReadReq misses
+system.cpu.l2cache.overall_hits::total           8499                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3064                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          458                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3522                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1705                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1705                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3062                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         2166                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5228                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3062                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         2166                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5228                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    211253500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     36622500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    247876000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    125606750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    125606750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    211253500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    162229250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    373482750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    211253500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    162229250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    373482750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        11333                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          516                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        11849                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst         3064                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2163                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5227                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3064                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2163                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5227                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    210607000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     35793000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    246400000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    122677500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    122677500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    210607000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    158470500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    369077500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    210607000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    158470500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    369077500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        11482                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          513                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        11995                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          109                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          109                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1731                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1731                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        11333                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         2247                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        13580                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        11333                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         2247                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        13580                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.270184                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.893411                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.297325                       # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        11482                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2244                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        13726                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        11482                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2244                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        13726                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.266852                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.892788                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.293622                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.984980                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.984980                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.270184                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.963952                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.384978                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.270184                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.963952                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.384978                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68991.998694                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79441.431670                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70359.352824                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73669.648094                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73669.648094                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68991.998694                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74898.084026                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71438.934583                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68991.998694                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74898.084026                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71438.934583                       # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.266852                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.963904                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.380810                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.266852                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.963904                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.380810                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68735.966057                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78150.655022                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69960.249858                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71951.612903                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71951.612903                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68735.966057                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73264.216366                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70609.814425                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68735.966057                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73264.216366                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70609.814425                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -757,187 +793,186 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3062                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          461                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3523                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3064                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          458                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3522                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1705                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1705                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3062                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         2166                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5228                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3062                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         2166                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5228                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    172480500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     30915000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    203395500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    104707750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    104707750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    172480500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    135622750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    308103250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    172480500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    135622750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    308103250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.270184                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.893411                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.297325                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3064                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2163                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5227                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3064                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2163                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5227                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    171789000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     30123000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    201912000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    101752000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    101752000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171789000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    131875000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    303664000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171789000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    131875000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    303664000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.266852                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.892788                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.293622                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.984980                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.984980                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.270184                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963952                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.384978                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.270184                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963952                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.384978                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56329.359895                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67060.737527                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.607721                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61412.170088                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61412.170088                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56329.359895                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62614.381348                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.291890                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56329.359895                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62614.381348                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.291890                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.266852                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963904                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.380810                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.266852                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963904                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.380810                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56066.906005                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65770.742358                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57328.790460                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59678.592375                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59678.592375                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56066.906005                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60968.562182                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58095.274536                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56066.906005                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60968.562182                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58095.274536                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements               159                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1460.308394                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28078942                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2247                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12496.191366                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1456.991941                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28100018                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2244                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12522.289661                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1460.308394                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.356521                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.356521                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2088                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1456.991941                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355711                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355711                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2085                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          541                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1391                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.509766                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          56178581                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         56178581                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21585827                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21585827                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492868                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492868                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          247                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          247                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28078695                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28078695                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28078695                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28078695                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          989                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           989                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8235                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8235                       # number of WriteReq misses
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1388                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.509033                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          56220748                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         56220748                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21606921                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21606921                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492872                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492872                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          225                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          225                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28099793                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28099793                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28099793                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28099793                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1002                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1002                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8231                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8231                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9224                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9224                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9224                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9224                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     64012750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     64012750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    517866286                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    517866286                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9233                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9233                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9233                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9233                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     62924000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     62924000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    508720531                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    508720531                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        92750                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        92750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    581879036                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    581879036                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    581879036                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    581879036                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     21586816                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     21586816                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    571644531                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    571644531                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    571644531                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    571644531                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     21607923                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     21607923                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          248                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          248                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28087919                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28087919                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28087919                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28087919                       # number of overall (read+write) accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          226                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          226                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28109026                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28109026                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28109026                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28109026                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000046                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000046                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001267                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001267                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.004032                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.004032                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001266                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001266                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.004425                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.004425                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000328                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000328                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000328                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000328                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64724.721941                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 64724.721941                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62886.009229                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62886.009229                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62798.403194                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62798.403194                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61805.434455                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61805.434455                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        92750                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        92750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63083.156548                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63083.156548                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63083.156548                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63083.156548                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        24818                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61913.195170                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61913.195170                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61913.195170                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61913.195170                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        23691                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               346                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               343                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    71.728324                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    69.069971                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          109                       # number of writebacks
 system.cpu.dcache.writebacks::total               109                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          474                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          474                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6504                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6504                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         6978                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         6978                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         6978                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         6978                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          515                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          515                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          490                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          490                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6500                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6500                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         6990                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         6990                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         6990                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         6990                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          512                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          512                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1731                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         1731                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2246                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2246                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2246                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2246                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     37612750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     37612750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    127737997                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    127737997                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         2243                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2243                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2243                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2243                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36779750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36779750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    124808747                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    124808747                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        90250                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        90250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    165350747                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    165350747                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    165350747                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    165350747                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    161588497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    161588497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    161588497                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    161588497                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000266                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.004032                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.004032                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.004425                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.004425                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000080                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000080                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000080                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000080                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73034.466019                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73034.466019                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73794.336800                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73794.336800                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71835.449219                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71835.449219                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72102.106875                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72102.106875                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        90250                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        90250                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73620.101069                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73620.101069                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73620.101069                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73620.101069                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72041.238074                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72041.238074                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72041.238074                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72041.238074                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index 632b87104..5bf6c1d3d 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.045952                       # Nu
 sim_ticks                                 45951567500                       # Number of ticks simulated
 final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1649677                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1649676                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              824838449                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275016                       # Number of bytes of host memory used
-host_seconds                                    55.71                       # Real time elapsed on the host
+host_inst_rate                                2663178                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2663177                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1331588953                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260384                       # Number of bytes of host memory used
+host_seconds                                    34.51                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -95,5 +95,40 @@ system.cpu.num_busy_cycles                   91903136                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          10240685                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               7723353      8.40%      8.40% # Class of executed instruction
+system.cpu.op_class::IntAlu                  51001543     55.49%     63.90% # Class of executed instruction
+system.cpu.op_class::IntMult                   458252      0.50%     64.40% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     64.40% # Class of executed instruction
+system.cpu.op_class::FloatAdd                 2732464      2.97%     67.37% # Class of executed instruction
+system.cpu.op_class::FloatCmp                  104605      0.11%     67.48% # Class of executed instruction
+system.cpu.op_class::FloatCvt                 2333953      2.54%     70.02% # Class of executed instruction
+system.cpu.op_class::FloatMult                 296445      0.32%     70.35% # Class of executed instruction
+system.cpu.op_class::FloatDiv                  754822      0.82%     71.17% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                    318      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::MemRead                 19996208     21.76%     92.93% # Class of executed instruction
+system.cpu.op_class::MemWrite                 6501126      7.07%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   91903089                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index bb6abdd34..88e7e1e1c 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.118729                       # Nu
 sim_ticks                                118729316000                       # Number of ticks simulated
 final_tick                               118729316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1382014                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1382013                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1785419086                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233256                       # Number of bytes of host memory used
-host_seconds                                    66.50                       # Real time elapsed on the host
+host_inst_rate                                1199929                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1199929                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1550185026                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269088                       # Number of bytes of host memory used
+host_seconds                                    76.59                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -101,6 +101,41 @@ system.cpu.num_busy_cycles                  237458632                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          10240685                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               7723353      8.40%      8.40% # Class of executed instruction
+system.cpu.op_class::IntAlu                  51001543     55.49%     63.90% # Class of executed instruction
+system.cpu.op_class::IntMult                   458252      0.50%     64.40% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     64.40% # Class of executed instruction
+system.cpu.op_class::FloatAdd                 2732464      2.97%     67.37% # Class of executed instruction
+system.cpu.op_class::FloatCmp                  104605      0.11%     67.48% # Class of executed instruction
+system.cpu.op_class::FloatCvt                 2333953      2.54%     70.02% # Class of executed instruction
+system.cpu.op_class::FloatMult                 296445      0.32%     70.35% # Class of executed instruction
+system.cpu.op_class::FloatDiv                  754822      0.82%     71.17% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                    318      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.17% # Class of executed instruction
+system.cpu.op_class::MemRead                 19996208     21.76%     92.93% # Class of executed instruction
+system.cpu.op_class::MemWrite                 6501126      7.07%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   91903089                       # Class of executed instruction
 system.cpu.icache.tags.replacements              6681                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1418.052773                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            91894580                       # Total number of references to valid blocks.
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 975655111..d4466739f 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.074212                       # Number of seconds simulated
-sim_ticks                                 74211770500                       # Number of ticks simulated
-final_tick                                74211770500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.074209                       # Number of seconds simulated
+sim_ticks                                 74208571000                       # Number of ticks simulated
+final_tick                                74208571000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 109728                       # Simulator instruction rate (inst/s)
-host_op_rate                                   120142                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               47260193                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 316324                       # Number of bytes of host memory used
-host_seconds                                  1570.28                       # Real time elapsed on the host
+host_inst_rate                                 109569                       # Simulator instruction rate (inst/s)
+host_op_rate                                   119969                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47190079                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 316768                       # Number of bytes of host memory used
+host_seconds                                  1572.55                       # Real time elapsed on the host
 sim_insts                                   172303021                       # Number of instructions simulated
 sim_ops                                     188656503                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            131072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            112000                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               243072                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       131072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          131072                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               2048                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1750                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3798                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1766189                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1509195                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3275383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1766189                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1766189                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1766189                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1509195                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3275383                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          3799                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            131456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            111808                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               243264                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       131456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          131456                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               2054                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1747                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3801                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1771440                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1506672                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3278112                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1771440                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1771440                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1771440                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1506672                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3278112                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          3802                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        3799                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        3802                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   243136                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   243328                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    243136                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    243328                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 306                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 215                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 132                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 216                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 134                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 308                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 298                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 299                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 300                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 265                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 218                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 217                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 246                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 214                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 215                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                289                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                192                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                190                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                208                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                219                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                218                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                200                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     74211752000                       # Total gap between requests
+system.physmem.totGap                     74208552500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3799                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    3802                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      2838                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       780                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       138                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        36                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      2914                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       704                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        38                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -186,28 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          252                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      398.476190                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     217.440190                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     401.372897                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             87     34.52%     34.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           58     23.02%     57.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           17      6.75%     64.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            5      1.98%     66.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            7      2.78%     69.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            8      3.17%     72.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            4      1.59%     73.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            3      1.19%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           63     25.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            252                       # Bytes accessed per row activation
-system.physmem.totQLat                       23847500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 100702500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     18995000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    57860000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6277.31                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15230.32                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples          765                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      315.649673                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.993895                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     311.806865                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            244     31.90%     31.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          208     27.19%     59.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           73      9.54%     68.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           46      6.01%     74.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           29      3.79%     78.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           70      9.15%     87.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           12      1.57%     89.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           15      1.96%     91.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           68      8.89%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            765                       # Bytes accessed per row activation
+system.physmem.totQLat                       30320750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 101608250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     19010000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7974.95                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26507.63                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  26724.95                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.28                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.28                       # Average system read bandwidth in MiByte/s
@@ -216,40 +214,44 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       3018                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       3030                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.44                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.69                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19534549.09                       # Average gap between requests
-system.physmem.pageHitRate                      79.44                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.21                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      3275383                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                2728                       # Transaction distribution
-system.membus.trans_dist::ReadResp               2727                       # Transaction distribution
+system.physmem.avgGap                     19518293.66                       # Average gap between requests
+system.physmem.pageHitRate                      79.69                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      70857777500                       # Time in different power states
+system.physmem.memoryStateTime::REF        2477800000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT         867720500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      3278112                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                2731                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2730                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1071                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1071                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7597                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7597                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       243072                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              243072                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 243072                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7603                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   7603                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       243264                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              243264                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 243264                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             4687500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             4745000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           35592500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           35718000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                94795806                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          74795654                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6279989                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             44691885                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                43051051                       # Number of BTB hits
+system.cpu.branchPred.lookups                94830067                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          74823235                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6280063                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             44671635                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                43055955                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             96.328564                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 4354918                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              88426                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             96.383208                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 4354004                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              88575                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -335,135 +337,135 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        148423542                       # number of cpu cycles simulated
+system.cpu.numCycles                        148417143                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           39654967                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      380195915                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    94795806                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           47405969                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      80368300                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                27279262                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                7212539                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                    9                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          5988                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           39654365                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      380231735                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    94830067                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           47409959                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      80369944                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                27285630                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                7202415                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   10                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          5794                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
 system.cpu.fetch.IcacheWaitRetryStallCycles           50                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  36848695                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1833193                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          148225221                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.802047                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.153051                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  36851066                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1832690                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          148222429                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.802512                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.153204                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 68026374     45.89%     45.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  5263091      3.55%     49.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 10536182      7.11%     56.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 10285653      6.94%     63.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  8660137      5.84%     69.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  6544581      4.42%     73.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  6243734      4.21%     77.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  8007959      5.40%     83.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 24657510     16.64%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 68020985     45.89%     45.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  5256509      3.55%     49.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 10534999      7.11%     56.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 10284828      6.94%     63.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  8666572      5.85%     69.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  6537070      4.41%     73.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  6246175      4.21%     77.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  8016813      5.41%     83.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 24658478     16.64%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            148225221                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.638684                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.561561                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 45510679                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               5881311                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  74801618                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1201370                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               20830243                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             14327753                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                164034                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              392767808                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                749358                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               20830243                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 50895494                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  723680                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         602483                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  70555782                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4617539                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              371309891                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    37                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 338990                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               3664355                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               25                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           631718613                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1588504211                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1506839397                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           3198087                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            148222429                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.638943                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.561913                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 45507597                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               5871716                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  74805608                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1201041                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               20836467                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             14340186                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                164591                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              392845308                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                733522                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               20836467                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 50894479                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  722812                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         602318                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  70557272                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4609081                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              371354915                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    44                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 338748                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3656059                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               24                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           631764461                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1588652531                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1506975247                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           3198470                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             298044139                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                333674474                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              25005                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          25002                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13030816                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             43005440                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16429294                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           5701095                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          3639070                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  329189812                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               47090                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 249460239                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            787524                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       139505237                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    362363758                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1874                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     148225221                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.682981                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.761692                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                333720322                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              25119                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          25116                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13019783                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             43012506                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16421309                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           5620383                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          3639856                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  329245944                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               47173                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 249482695                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            793526                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       139565421                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    362544222                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1957                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     148222429                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.683164                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.761970                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            56054819     37.82%     37.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            22642547     15.28%     53.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            24806201     16.74%     69.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20327492     13.71%     83.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12550892      8.47%     92.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             6518173      4.40%     96.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             4029511      2.72%     99.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1113373      0.75%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              182213      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            56049781     37.81%     37.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            22646407     15.28%     53.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            24808421     16.74%     69.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20317592     13.71%     83.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12547069      8.47%     92.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             6521251      4.40%     96.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             4032352      2.72%     99.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1118421      0.75%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              181135      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       148225221                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       148222429                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  964965     38.34%     38.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   5593      0.22%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                99      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc               49      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     38.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1170821     46.51%     85.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                375623     14.92%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  964061     38.35%     38.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5595      0.22%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                96      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     38.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc               48      0.00%     38.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     38.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     38.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     38.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1168003     46.46%     85.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                376162     14.96%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             194894311     78.13%     78.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               979316      0.39%     78.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             194908316     78.12%     78.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               978999      0.39%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.52% # Type of FU issued
@@ -482,93 +484,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.52% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33075      0.01%     78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33072      0.01%     78.53% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          164356      0.07%     78.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          254647      0.10%     78.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv           76432      0.03%     78.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         465549      0.19%     78.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206388      0.08%     79.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc        71859      0.03%     79.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          164299      0.07%     78.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          255151      0.10%     78.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76428      0.03%     78.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         465968      0.19%     78.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         206368      0.08%     79.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        71868      0.03%     79.03% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt            321      0.00%     79.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             38358541     15.38%     94.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13955444      5.59%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             38371220     15.38%     94.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13950685      5.59%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              249460239                       # Type of FU issued
-system.cpu.iq.rate                           1.680732                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2517150                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010090                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          646712991                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         466571759                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    237891174                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3737382                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2188885                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1841279                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              250102160                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1875229                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          2007089                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              249482695                       # Type of FU issued
+system.cpu.iq.rate                           1.680956                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2513965                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010077                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          646755779                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         466684925                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    237894917                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3739531                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2191886                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1842592                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              250120414                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1876246                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          2009109                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13155956                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11631                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18977                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      3784660                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13163022                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11141                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18733                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3776675                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           11                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads           14                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked           100                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               20830243                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   18508                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   911                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           329253924                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            785902                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              43005440                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16429294                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              24682                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    206                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   274                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18977                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3891616                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3758665                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7650281                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             242960344                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              36855491                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           6499895                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               20836467                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   18579                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   909                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           329310121                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            781513                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              43012506                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16421309                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              24765                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    190                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   272                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18733                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3888765                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3761308                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7650073                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             242977304                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              36862847                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6505391                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         17022                       # number of nop insts executed
-system.cpu.iew.exec_refs                     50506525                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 53424421                       # Number of branches executed
-system.cpu.iew.exec_stores                   13651034                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.636939                       # Inst execution rate
-system.cpu.iew.wb_sent                      240787816                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     239732453                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 148473522                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 267271209                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         17004                       # number of nop insts executed
+system.cpu.iew.exec_refs                     50511963                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 53432662                       # Number of branches executed
+system.cpu.iew.exec_stores                   13649116                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.637124                       # Inst execution rate
+system.cpu.iew.wb_sent                      240796428                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     239737509                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 148472463                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 267293668                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.615192                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.555516                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.615295                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.555466                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       140583033                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       140639228                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6126865                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    127394978                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.480992                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.186196                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6126680                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    127385962                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.481096                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.186061                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     57713917     45.30%     45.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     31674198     24.86%     70.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13788488     10.82%     80.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      7625423      5.99%     86.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4380329      3.44%     90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1321262      1.04%     91.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1701589      1.34%     92.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1311888      1.03%     93.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      7877884      6.18%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     57702305     45.30%     45.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     31675528     24.87%     70.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13782422     10.82%     80.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      7634808      5.99%     86.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4379316      3.44%     90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1319569      1.04%     91.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1705598      1.34%     92.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1313930      1.03%     93.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      7872486      6.18%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    127394978                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    127385962                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            172317409                       # Number of instructions committed
 system.cpu.commit.committedOps              188670891                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -579,230 +581,265 @@ system.cpu.commit.branches                   40300311                       # Nu
 system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 150106217                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               7877884                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        144055022     76.35%     76.35% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          908940      0.48%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     76.83% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd        32754      0.02%     76.85% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     76.85% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp       154829      0.08%     76.93% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt       238880      0.13%     77.06% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv        76016      0.04%     77.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       437591      0.23%     77.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult       200806      0.11%     77.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc        71617      0.04%     77.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt          318      0.00%     77.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        29849484     15.82%     93.30% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       12644634      6.70%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total         188670891                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               7872486                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    448765817                       # The number of ROB reads
-system.cpu.rob.rob_writes                   679447245                       # The number of ROB writes
-system.cpu.timesIdled                            2831                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          198321                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    448818394                       # The number of ROB reads
+system.cpu.rob.rob_writes                   679565858                       # The number of ROB writes
+system.cpu.timesIdled                            2789                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          194714                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303021                       # Number of Instructions Simulated
 system.cpu.committedOps                     188656503                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             172303021                       # Number of Instructions Simulated
-system.cpu.cpi                               0.861410                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.861410                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.160887                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.160887                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1079439987                       # number of integer regfile reads
-system.cpu.int_regfile_writes               384873432                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2912671                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2497165                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                64868455                       # number of misc regfile reads
+system.cpu.cpi                               0.861373                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.861373                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.160937                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.160937                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1079497274                       # number of integer regfile reads
+system.cpu.int_regfile_writes               384888160                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2912753                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2499155                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                64874393                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                 5152821                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq           4879                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          4878                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           18                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1079                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1079                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8203                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3730                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             11933                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       262464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       119936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         382400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            382400                       # Total data (bytes)
+system.cpu.toL2Bus.throughput                 5170292                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           4896                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          4895                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           19                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1081                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1081                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8239                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3733                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             11972                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       263616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       120064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         383680                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            383680                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        3006000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy        3017000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6511747                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6548996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3051239                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3099487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              2374                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1347.666302                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            36843383                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4101                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           8983.999756                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2388                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1346.753946                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            36845676                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4119                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           8945.296431                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1347.666302                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.658040                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.658040                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1727                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1346.753946                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.657595                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.657595                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1731                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          534                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           28                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1040                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.843262                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          73701491                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         73701491                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     36843383                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        36843383                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      36843383                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         36843383                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     36843383                       # number of overall hits
-system.cpu.icache.overall_hits::total        36843383                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5312                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5312                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5312                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5312                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5312                       # number of overall misses
-system.cpu.icache.overall_misses::total          5312                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    224724996                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    224724996                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    224724996                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    224724996                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    224724996                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    224724996                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     36848695                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     36848695                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     36848695                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     36848695                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     36848695                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     36848695                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000144                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000144                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000144                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000144                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000144                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000144                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42305.157380                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42305.157380                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42305.157380                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42305.157380                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42305.157380                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42305.157380                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1646                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::2          541                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           30                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1037                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.845215                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          73706251                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         73706251                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     36845676                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        36845676                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      36845676                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         36845676                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     36845676                       # number of overall hits
+system.cpu.icache.overall_hits::total        36845676                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5390                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5390                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5390                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5390                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5390                       # number of overall misses
+system.cpu.icache.overall_misses::total          5390                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    228751995                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    228751995                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    228751995                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    228751995                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    228751995                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    228751995                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     36851066                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     36851066                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     36851066                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     36851066                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     36851066                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     36851066                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000146                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000146                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000146                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000146                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000146                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000146                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42440.073284                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42440.073284                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42440.073284                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42440.073284                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42440.073284                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42440.073284                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1596                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                19                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    86.631579                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           84                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1210                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1210                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1210                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1210                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1210                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1210                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4102                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4102                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4102                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4102                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4102                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4102                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    167739253                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    167739253                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    167739253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    167739253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    167739253                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    167739253                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000111                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000111                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000111                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000111                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000111                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000111                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40892.065578                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40892.065578                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40892.065578                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40892.065578                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40892.065578                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40892.065578                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1270                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1270                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1270                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1270                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1270                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1270                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4120                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4120                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4120                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4120                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4120                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4120                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    167326504                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    167326504                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    167326504                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    167326504                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    167326504                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    167326504                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000112                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000112                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000112                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000112                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000112                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000112                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40613.229126                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40613.229126                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40613.229126                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40613.229126                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40613.229126                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40613.229126                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         1968.326603                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               2138                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2737                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.781147                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         1966.490721                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               2149                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             2739                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.784593                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     4.994032                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1425.493487                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   537.839084                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000152                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043503                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks     4.023907                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1424.627361                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   537.839452                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000123                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043476                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.016414                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.060069                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2737                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::total     0.060013                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2739                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          602                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           28                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1971                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.083527                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            51624                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           51624                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         2050                       # number of ReadReq hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          607                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           29                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1969                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.083588                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            51788                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           51788                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         2061                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           87                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           2137                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks           18                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           18                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         2050                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           95                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            2145                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         2050                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           95                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           2145                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2052                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          690                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         2742                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_hits::total           2148                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           19                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           19                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           10                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           10                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         2061                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           97                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            2158                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2061                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           97                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           2158                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2059                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          689                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         2748                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1071                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1071                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2052                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1761                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          3813                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2052                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1761                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         3813                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    143127750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     50855750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    193983500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     72887500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     72887500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    143127750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    123743250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    266871000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    143127750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    123743250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    266871000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         4102                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          777                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         4879                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks           18                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           18                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1079                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1079                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4102                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1856                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         5958                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4102                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1856                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         5958                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.500244                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.888031                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.562000                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992586                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.992586                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.500244                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.948815                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.639980                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.500244                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.948815                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.639980                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69750.365497                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73703.985507                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70745.258935                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68055.555556                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68055.555556                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69750.365497                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70268.739353                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69989.771833                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69750.365497                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70268.739353                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69989.771833                       # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst         2059                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1760                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          3819                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2059                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1760                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         3819                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    142590000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     50403250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    192993250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     74281750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     74281750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    142590000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    124685000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    267275000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    142590000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    124685000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    267275000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4120                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          776                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         4896                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           19                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           19                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1081                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1081                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4120                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1857                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         5977                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4120                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1857                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         5977                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.499757                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.887887                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.561275                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.990749                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.990749                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.499757                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.947765                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.638949                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.499757                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.947765                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.638949                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69252.064109                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73154.208999                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70230.440320                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69357.376284                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69357.376284                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69252.064109                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70843.750000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69985.598324                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69252.064109                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70843.750000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69985.598324                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -811,178 +848,178 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           14                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           11                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2049                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          679                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2728                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           13                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           13                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           13                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2055                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          676                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2731                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1071                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1071                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2049                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1750                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         3799                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2049                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1750                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         3799                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    117223750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     41708750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    158932500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     59427500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     59427500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    117223750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    101136250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    218360000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    117223750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    101136250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    218360000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.499512                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.873874                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.559131                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992586                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992586                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.499512                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.942888                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.637630                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.499512                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.942888                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.637630                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57210.224500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61426.730486                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58259.714076                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55487.861811                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.861811                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57210.224500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57792.142857                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57478.283759                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57210.224500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57792.142857                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57478.283759                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2055                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1747                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3802                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2055                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1747                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         3802                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    116514500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     41206750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    157721250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     60687250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     60687250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    116514500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    101894000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    218408500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    116514500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    101894000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    218408500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.498786                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.871134                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.557802                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.990749                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.990749                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.498786                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.940765                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.636105                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.498786                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.940765                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.636105                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56698.053528                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60956.730769                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57752.196997                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56664.098973                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56664.098973                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56698.053528                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58325.128792                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57445.686481                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56698.053528                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58325.128792                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57445.686481                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                59                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1407.038554                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            46795712                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1856                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          25213.206897                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements                60                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1407.063073                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            46801066                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1857                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          25202.512655                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1407.038554                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.343515                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.343515                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1407.063073                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.343521                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.343521                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1797                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          353                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          354                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1378                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.438721                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          93612504                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         93612504                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     34394263                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        34394263                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12356566                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12356566                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        22476                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        22476                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          93623269                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         93623269                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     34399630                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        34399630                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12356556                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12356556                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        22473                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        22473                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      46750829                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         46750829                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     46750829                       # number of overall hits
-system.cpu.dcache.overall_hits::total        46750829                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1889                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1889                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         7721                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         7721                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      46756186                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         46756186                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     46756186                       # number of overall hits
+system.cpu.dcache.overall_hits::total        46756186                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1907                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1907                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         7731                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         7731                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9610                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9610                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9610                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9610                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    119060977                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    119060977                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    479134996                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    479134996                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9638                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9638                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9638                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9638                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    121525225                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    121525225                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    489452496                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    489452496                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       142500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       142500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    598195973                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    598195973                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    598195973                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    598195973                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     34396152                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     34396152                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    610977721                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    610977721                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    610977721                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    610977721                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     34401537                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     34401537                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22478                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        22478                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22475                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        22475                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     46760439                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     46760439                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     46760439                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     46760439                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     46765824                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     46765824                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     46765824                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     46765824                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000055                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000055                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000624                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000624                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000625                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000625                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000089                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000089                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000206                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000206                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000206                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000206                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.574378                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.574378                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62056.080300                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62056.080300                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63725.865233                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63725.865233                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63310.373302                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63310.373302                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        71250                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        71250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62247.239646                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62247.239646                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62247.239646                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62247.239646                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          566                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63392.583627                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63392.583627                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63392.583627                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63392.583627                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          567                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          318                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    51.454545                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    51.545455                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    79.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
-system.cpu.dcache.writebacks::total                18                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1111                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         1111                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6643                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6643                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks           19                       # number of writebacks
+system.cpu.dcache.writebacks::total                19                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1130                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1130                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6651                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6651                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7754                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7754                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7754                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7754                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          778                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          778                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1078                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1078                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1856                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1856                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1856                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1856                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     52580511                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     52580511                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     73988748                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     73988748                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    126569259                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    126569259                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    126569259                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    126569259                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data         7781                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7781                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7781                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7781                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          777                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          777                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1080                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1080                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1857                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1857                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1857                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1857                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     52119013                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     52119013                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     75404498                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     75404498                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    127523511                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    127523511                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    127523511                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    127523511                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000087                       # mshr miss rate for WriteReq accesses
@@ -991,14 +1028,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000040
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67584.204370                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67584.204370                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68635.202226                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68635.202226                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68194.643858                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68194.643858                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68194.643858                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68194.643858                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67077.236808                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67077.236808                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69818.979630                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69818.979630                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68671.788368                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68671.788368                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68671.788368                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68671.788368                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 02bcdd9ff..af9e4b297 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.103107                       # Nu
 sim_ticks                                103106766000                       # Number of ticks simulated
 final_tick                               103106766000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1878588                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2056872                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1124059947                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262308                       # Number of bytes of host memory used
-host_seconds                                    91.73                       # Real time elapsed on the host
+host_inst_rate                                1728223                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1892237                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1034088491                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304984                       # Number of bytes of host memory used
+host_seconds                                    99.71                       # Real time elapsed on the host
 sim_insts                                   172317409                       # Number of instructions simulated
 sim_ops                                     188670891                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,5 +147,40 @@ system.cpu.num_busy_cycles                  206213533                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          40300311                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 144055422     76.35%     76.35% # Class of executed instruction
+system.cpu.op_class::IntMult                   908940      0.48%     76.83% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd               32754      0.02%     76.85% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     76.85% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp              154829      0.08%     76.93% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             437591      0.23%     77.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult             200806      0.11%     77.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.48% # Class of executed instruction
+system.cpu.op_class::MemRead                 29849484     15.82%     93.30% # Class of executed instruction
+system.cpu.op_class::MemWrite                12644635      6.70%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  188671292                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 013c20430..7e06925a9 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.232072                       # Nu
 sim_ticks                                232072304000                       # Number of ticks simulated
 final_tick                               232072304000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1152638                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1262262                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1556630640                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 271024                       # Number of bytes of host memory used
-host_seconds                                   149.09                       # Real time elapsed on the host
+host_inst_rate                                 924224                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1012125                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1248159761                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313696                       # Number of bytes of host memory used
+host_seconds                                   185.93                       # Real time elapsed on the host
 sim_insts                                   171842483                       # Number of instructions simulated
 sim_ops                                     188185920                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -153,6 +153,41 @@ system.cpu.num_busy_cycles                  464144608                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          40300311                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 144055422     76.35%     76.35% # Class of executed instruction
+system.cpu.op_class::IntMult                   908940      0.48%     76.83% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     76.83% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd               32754      0.02%     76.85% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     76.85% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp              154829      0.08%     76.93% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.06% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             437591      0.23%     77.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult             200806      0.11%     77.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.48% # Class of executed instruction
+system.cpu.op_class::MemRead                 29849484     15.82%     93.30% # Class of executed instruction
+system.cpu.op_class::MemWrite                12644635      6.70%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  188671292                       # Class of executed instruction
 system.cpu.icache.tags.replacements              1506                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1147.986161                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           189857001                       # Total number of references to valid blocks.
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 1f6381fd7..85aa0370c 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.096723                       # Nu
 sim_ticks                                 96722945000                       # Number of ticks simulated
 final_tick                                96722945000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2588672                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2588674                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1294344494                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233760                       # Number of bytes of host memory used
-host_seconds                                    74.73                       # Real time elapsed on the host
+host_inst_rate                                2358558                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2358560                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1179286883                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269756                       # Number of bytes of host memory used
+host_seconds                                    82.02                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -65,5 +65,40 @@ system.cpu.num_busy_cycles                  193445891                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          15132745                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              13329871      6.89%      6.89% # Class of executed instruction
+system.cpu.op_class::IntAlu                 102506896     52.99%     59.88% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     59.88% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     59.88% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  875036      0.45%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::MemRead                 57735103     29.85%     90.18% # Class of executed instruction
+system.cpu.op_class::MemWrite                18998867      9.82%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  193445773                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index dc02f2f3d..117dae8be 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.270563                       # Nu
 sim_ticks                                270563082000                       # Number of ticks simulated
 final_tick                               270563082000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1313314                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1313315                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1836878526                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242660                       # Number of bytes of host memory used
-host_seconds                                   147.30                       # Real time elapsed on the host
+host_inst_rate                                1069922                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1069924                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1496457293                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278484                       # Number of bytes of host memory used
+host_seconds                                   180.80                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -69,6 +69,41 @@ system.cpu.num_busy_cycles                  541126164                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          15132745                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              13329871      6.89%      6.89% # Class of executed instruction
+system.cpu.op_class::IntAlu                 102506896     52.99%     59.88% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     59.88% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     59.88% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  875036      0.45%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     60.33% # Class of executed instruction
+system.cpu.op_class::MemRead                 57735103     29.85%     90.18% # Class of executed instruction
+system.cpu.op_class::MemWrite                18998867      9.82%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  193445773                       # Class of executed instruction
 system.cpu.icache.tags.replacements             10362                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1591.579171                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           193433248                       # Total number of references to valid blocks.
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index cc1011ed3..b45ab6e1b 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.144377                       # Number of seconds simulated
-sim_ticks                                144377116000                       # Number of ticks simulated
-final_tick                               144377116000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.144620                       # Number of seconds simulated
+sim_ticks                                144620050000                       # Number of ticks simulated
+final_tick                               144620050000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66784                       # Simulator instruction rate (inst/s)
-host_op_rate                                   111936                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               73006862                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 319660                       # Number of bytes of host memory used
-host_seconds                                  1977.58                       # Real time elapsed on the host
+host_inst_rate                                  65513                       # Simulator instruction rate (inst/s)
+host_op_rate                                   109805                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               71737347                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319696                       # Number of bytes of host memory used
+host_seconds                                  2015.97                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            217984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               343040                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       217984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          217984                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3406                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1954                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5360                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1509824                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               866176                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2376000                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1509824                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1509824                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1509824                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              866176                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2376000                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5361                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            217216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            125440                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               342656                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       217216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          217216                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3394                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1960                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5354                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1501977                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               867376                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2369353                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1501977                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1501977                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1501977                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              867376                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2369353                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5356                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5361                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5356                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   343104                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   342784                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    343104                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    342784                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            150                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 281                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 346                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            131                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 288                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 358                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 449                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 351                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 335                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 356                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 330                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 328                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 398                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 381                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 343                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 292                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                228                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                284                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 400                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 378                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 340                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 277                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                231                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                276                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                208                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                469                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                386                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                282                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                466                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                385                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                286                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    144377080000                       # Total gap between requests
+system.physmem.totGap                    144620007000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5361                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5356                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4312                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       880                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       145                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4298                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       873                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       161                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        20                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -186,305 +186,307 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          327                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      508.672783                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     294.998238                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     425.682375                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             88     26.91%     26.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           53     16.21%     43.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           28      8.56%     51.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           16      4.89%     56.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            9      2.75%     59.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            6      1.83%     61.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      0.92%     62.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            3      0.92%     63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          121     37.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            327                       # Bytes accessed per row activation
-system.physmem.totQLat                       28551000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 139987250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26805000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    84631250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        5325.69                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15786.47                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples         1043                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      326.933845                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     193.223116                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.208962                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            368     35.28%     35.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          248     23.78%     59.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          102      9.78%     68.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           58      5.56%     74.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           42      4.03%     78.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           59      5.66%     84.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           17      1.63%     85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           23      2.21%     87.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          126     12.08%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1043                       # Bytes accessed per row activation
+system.physmem.totQLat                       35519000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 135944000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26780000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6631.63                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26112.15                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25381.63                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.37                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.37                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.13                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4274                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4304                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.72                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.36                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     26930997.95                       # Average gap between requests
-system.physmem.pageHitRate                      79.72                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.40                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      2375113                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                3828                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3825                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              150                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             150                       # Transaction distribution
+system.physmem.avgGap                     27001494.96                       # Average gap between requests
+system.physmem.pageHitRate                      80.36                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     138334279250                       # Time in different power states
+system.physmem.memoryStateTime::REF        4828980000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1451861250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      2368911                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                3823                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3820                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              131                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             131                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1533                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1533                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11019                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11019                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  11019                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       342912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total       342912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              342912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 342912                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10971                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        10971                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10971                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       342592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total       342592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              342592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 342592                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             6993500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             6960500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           50706850                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           50659869                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                18662333                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          18662333                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1490477                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11407057                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                10802916                       # Number of BTB hits
+system.cpu.branchPred.lookups                18663045                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          18663045                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1489785                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11444584                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                10797822                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.703796                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1319575                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              23217                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.348750                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1319901                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              22895                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        289035036                       # number of cpu cycles simulated
+system.cpu.numCycles                        289523031                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           23466628                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      206674196                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    18662333                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           12122491                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      54224578                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                15529649                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              177872737                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 1739                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          9780                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           23                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  22363082                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                227556                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          269352720                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.269654                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.757498                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           23473938                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      206858197                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    18663045                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           12117723                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      54247835                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                15552938                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              178336695                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 1340                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          7706                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           24                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22368694                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                223698                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          269869756                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.267902                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.756065                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                216567147     80.40%     80.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2849140      1.06%     81.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2312743      0.86%     82.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2640443      0.98%     83.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3223496      1.20%     84.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3388678      1.26%     85.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3828931      1.42%     87.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2559342      0.95%     88.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 31982800     11.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                217061517     80.43%     80.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2847740      1.06%     81.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2315002      0.86%     82.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2640494      0.98%     83.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3217056      1.19%     84.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3387561      1.26%     85.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3839682      1.42%     87.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2560696      0.95%     88.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 32000008     11.86%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            269352720                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.064568                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.715049                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 36872291                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             166882879                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  41583049                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              10237266                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               13777235                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              336030589                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               13777235                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 44927552                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               116592006                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          33482                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  42725844                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              51296601                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              329644603                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 10793                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               25973281                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              22738118                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           382392326                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             917644681                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        605892364                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           4122807                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            269869756                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.064461                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.714479                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 36939117                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             167279649                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  41594778                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              10253994                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               13802218                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              336245393                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               13802218                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 45020160                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               116775107                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          31642                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  42714880                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              51525749                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              329872428                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 11092                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               26167242                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              22759273                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           382595093                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             918331708                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        606342575                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           4133173                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                122962876                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               2119                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2126                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 104910685                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             84442386                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            30099715                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          58118082                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         18905602                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  322699954                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                4280                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 260615725                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            114961                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       100953398                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    209924725                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           3035                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     269352720                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.967563                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.344835                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                123165643                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2073                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2073                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 105277588                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             84554246                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            30134710                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          58533931                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         19035455                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  322937953                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4364                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 260608849                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            112553                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       101196304                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    210593531                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3119                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     269869756                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.965684                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.342187                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           143250903     53.18%     53.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            55370436     20.56%     73.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            34176648     12.69%     86.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            19094867      7.09%     93.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            10869897      4.04%     97.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4155062      1.54%     99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1825131      0.68%     99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              476500      0.18%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              133276      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           143519297     53.18%     53.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            55647203     20.62%     73.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            34229884     12.68%     86.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            19073202      7.07%     93.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            10874136      4.03%     97.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4113724      1.52%     99.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1802263      0.67%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              476846      0.18%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              133201      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       269352720                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       269869756                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  130941      4.84%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2275620     84.10%     88.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                299199     11.06%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  125646      4.63%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2288183     84.39%     89.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                297636     10.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1210799      0.46%      0.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             162097443     62.20%     62.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               790400      0.30%     62.97% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               7035783      2.70%     65.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1447528      0.56%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             65478586     25.12%     91.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            22555186      8.65%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1210826      0.46%      0.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             162119129     62.21%     62.67% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               788294      0.30%     62.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7035677      2.70%     65.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1444684      0.55%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             65441941     25.11%     91.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            22568298      8.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              260615725                       # Type of FU issued
-system.cpu.iq.rate                           0.901675                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2705760                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010382                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          788512519                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         420334227                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    255242293                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             4892372                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            3608187                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2352192                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              259648600                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2462086                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18920241                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              260608849                       # Type of FU issued
+system.cpu.iq.rate                           0.900132                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2711465                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010404                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          789025856                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         420800342                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    255248449                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             4885616                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            3622403                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2349194                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              259650836                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2458652                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18874838                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     27792799                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        26588                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       290410                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      9583998                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     27904659                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        26471                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       289699                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      9618993                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        49921                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        50123                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            17                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               13777235                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                85064772                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               5446513                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           322704234                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            135340                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              84442386                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             30099715                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               2049                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                2678194                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 12950                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         290410                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         639185                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       902051                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1541236                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             258833919                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              64703526                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1781806                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               13802218                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                85051562                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               5443180                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           322942317                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            133815                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              84554246                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             30134710                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               2043                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                2682047                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 14716                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         289699                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         640019                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       900364                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1540383                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             258834349                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              64663337                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1774500                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     87053484                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14272898                       # Number of branches executed
-system.cpu.iew.exec_stores                   22349958                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.895511                       # Inst execution rate
-system.cpu.iew.wb_sent                      258192676                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     257594485                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 206043233                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 369200904                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     87028906                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14271418                       # Number of branches executed
+system.cpu.iew.exec_stores                   22365569                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.894003                       # Inst execution rate
+system.cpu.iew.wb_sent                      258197839                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     257597643                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 206027195                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 369217293                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.891222                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.558079                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.889731                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.558011                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       101415579                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       101647922                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1491917                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    255575485                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.866137                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.656618                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1490935                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    256067538                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.864473                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.651889                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    156360594     61.18%     61.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     57109316     22.35%     83.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13985683      5.47%     89.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12037857      4.71%     93.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4182593      1.64%     95.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2963821      1.16%     96.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       909345      0.36%     96.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1046624      0.41%     97.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6979652      2.73%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    156617936     61.16%     61.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     57255270     22.36%     83.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     14082261      5.50%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12088609      4.72%     93.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4189643      1.64%     95.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2964480      1.16%     96.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       903129      0.35%     96.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1051661      0.41%     97.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6914549      2.70%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    255575485                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    256067538                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -495,240 +497,277 @@ system.cpu.commit.branches                   12326938                       # Nu
 system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 219019985                       # Number of committed integer instructions.
 system.cpu.commit.function_calls               797818                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6979652                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass      1176721      0.53%      0.53% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        133863962     60.47%     61.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          772953      0.35%     61.35% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv          7031501      3.18%     64.53% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd        1352943      0.61%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.14% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        56649587     25.59%     90.73% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20515717      9.27%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               6914549                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    571374796                       # The number of ROB reads
-system.cpu.rob.rob_writes                   659361249                       # The number of ROB writes
-system.cpu.timesIdled                         5927783                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        19682316                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    572164295                       # The number of ROB reads
+system.cpu.rob.rob_writes                   659850863                       # The number of ROB writes
+system.cpu.timesIdled                         5930649                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        19653275                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             132071192                       # Number of Instructions Simulated
-system.cpu.cpi                               2.188479                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.188479                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.456938                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.456938                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                451403378                       # number of integer regfile reads
-system.cpu.int_regfile_writes               234040975                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3219859                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2011879                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 102824885                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 59817361                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               133392985                       # number of misc regfile reads
+system.cpu.cpi                               2.192174                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.192174                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.456168                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.456168                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                451375343                       # number of integer regfile reads
+system.cpu.int_regfile_writes               234032598                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3213912                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2009037                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 102846049                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 59805449                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               133386978                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                 3846371                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq           7125                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          7121                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           15                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          150                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          150                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1541                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1541                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13184                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4308                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             17492                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       417024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       128640                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         545664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            545664                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus         9664                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        4430500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                 3852301                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           7156                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          7153                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           13                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          132                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          132                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1539                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1539                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13245                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4286                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             17531                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       419584                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       129024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         548608                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            548608                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus         8512                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        4433000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      10573999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      10626750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3437150                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3450631                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              4547                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1629.451963                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22354297                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6517                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3430.151450                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4592                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1628.049417                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22359876                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6557                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3410.077169                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1629.451963                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.795631                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.795631                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1970                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          187                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          757                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          125                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          807                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.961914                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          44732829                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         44732829                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22354297                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22354297                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22354297                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22354297                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22354297                       # number of overall hits
-system.cpu.icache.overall_hits::total        22354297                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8784                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8784                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8784                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8784                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8784                       # number of overall misses
-system.cpu.icache.overall_misses::total          8784                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    365846249                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    365846249                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    365846249                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    365846249                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    365846249                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    365846249                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22363081                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22363081                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22363081                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22363081                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22363081                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22363081                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000393                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000393                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000393                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000393                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000393                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000393                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41649.163138                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 41649.163138                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 41649.163138                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 41649.163138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 41649.163138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 41649.163138                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          800                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1628.049417                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.794946                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.794946                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1965                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          165                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          773                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          124                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          810                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.959473                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          44744077                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         44744077                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22359876                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22359876                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22359876                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22359876                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22359876                       # number of overall hits
+system.cpu.icache.overall_hits::total        22359876                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8818                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          8818                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         8818                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           8818                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         8818                       # number of overall misses
+system.cpu.icache.overall_misses::total          8818                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    365022750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    365022750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    365022750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    365022750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    365022750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    365022750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22368694                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22368694                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22368694                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22368694                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22368694                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22368694                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000394                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000394                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000394                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000394                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000394                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000394                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41395.185983                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 41395.185983                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 41395.185983                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 41395.185983                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 41395.185983                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 41395.185983                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          701                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    57.142857                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    46.733333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2116                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2116                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2116                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2116                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2116                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2116                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6668                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         6668                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         6668                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         6668                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         6668                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         6668                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    272166001                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    272166001                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    272166001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    272166001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    272166001                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    272166001                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000298                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000298                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000298                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000298                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000298                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000298                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40816.736803                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40816.736803                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40816.736803                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40816.736803                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40816.736803                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40816.736803                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2129                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2129                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2129                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2129                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2129                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2129                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6689                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         6689                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         6689                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         6689                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         6689                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         6689                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    269490250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    269490250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    269490250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    269490250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    269490250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    269490250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000299                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000299                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000299                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40288.570788                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40288.570788                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40288.570788                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40288.570788                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40288.570788                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40288.570788                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2545.733703                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               3149                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3831                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.821979                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2549.629926                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               3205                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3824                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.838128                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     1.666971                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2237.371026                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   306.695706                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000051                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.068279                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.009360                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.077690                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3831                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          881                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          143                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks     1.731773                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2236.346523                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   311.551630                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000053                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.068248                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.009508                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.077809                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3824                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          169                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          895                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          142                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2568                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.116913                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            74812                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           74812                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3110                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           36                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           3146                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks           15                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           15                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3110                       # number of demand (read+write) hits
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.116699                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            75020                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           75020                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         3162                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           38                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           3200                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           13                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           13                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            6                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            6                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3162                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           44                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            3154                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3110                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            3206                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3162                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           44                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           3154                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3407                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          421                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3828                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          150                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          150                       # number of UpgradeReq misses
+system.cpu.l2cache.overall_hits::total           3206                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3394                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          429                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3823                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          131                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          131                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1533                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1533                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3407                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1954                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5361                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3407                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1954                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5361                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    234241000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32796500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    267037500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    104661000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    104661000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    234241000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    137457500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    371698500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    234241000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    137457500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    371698500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         6517                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          457                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         6974                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks           15                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           15                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          150                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          150                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1541                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1541                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6517                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1998                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8515                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6517                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1998                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8515                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.522787                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.921225                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.548896                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994809                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.994809                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.522787                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.977978                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.629595                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.522787                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.977978                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.629595                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68752.861755                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77901.425178                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69759.012539                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68272.015656                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68272.015656                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68752.861755                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70346.724667                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69333.799664                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68752.861755                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70346.724667                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69333.799664                       # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst         3394                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1962                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5356                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3394                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1962                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5356                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    231042500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32071000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    263113500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    103820500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    103820500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    231042500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    135891500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    366934000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    231042500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    135891500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    366934000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         6556                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          467                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         7023                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           13                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           13                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          132                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          132                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1539                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1539                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6556                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2006                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8562                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6556                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2006                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8562                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.517694                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.918630                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.544354                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.992424                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.992424                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.996101                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.996101                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.517694                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.978066                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.625555                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.517694                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.978066                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.625555                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68073.806718                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74757.575758                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68823.829453                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67723.744292                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67723.744292                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68073.806718                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69261.722732                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68508.961912                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68073.806718                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69261.722732                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68508.961912                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -737,175 +776,175 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3407                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          421                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3828                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          150                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          150                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3394                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          429                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3823                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          131                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          131                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1533                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1533                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3407                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1954                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5361                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3407                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1954                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5361                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    191583500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     27592500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    219176000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1500150                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1500150                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     85063500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     85063500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    191583500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    112656000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    304239500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    191583500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    112656000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    304239500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.522787                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.921225                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.548896                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994809                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994809                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.522787                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.977978                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.629595                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.522787                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.977978                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.629595                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56232.315820                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65540.380048                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57256.008359                       # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3394                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1962                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5356                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3394                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1962                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5356                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    188477000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     26778500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    215255500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1310131                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1310131                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     84218500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     84218500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    188477000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    110997000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    299474000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    188477000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    110997000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    299474000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.517694                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.918630                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.544354                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.992424                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.992424                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.996101                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.996101                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.517694                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.978066                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.625555                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.517694                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.978066                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.625555                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55532.410136                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62420.745921                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56305.388438                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55488.258317                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55488.258317                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56232.315820                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57654.042989                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56750.512964                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56232.315820                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57654.042989                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56750.512964                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54937.051533                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54937.051533                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55532.410136                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56573.394495                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55913.741598                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55532.410136                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56573.394495                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55913.741598                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                57                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1432.023881                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            66143701                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1995                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          33154.737343                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements                59                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1435.036669                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            66148000                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2003                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          33024.463305                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1432.023881                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.349615                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.349615                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1938                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          427                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1393                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.473145                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         132294203                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        132294203                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     45629460                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        45629460                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20514040                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20514040                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      66143500                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         66143500                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     66143500                       # number of overall hits
-system.cpu.dcache.overall_hits::total        66143500                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          913                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           913                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1691                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1691                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2604                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2604                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2604                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2604                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     59632801                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     59632801                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    113805150                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    113805150                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    173437951                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    173437951                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    173437951                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    173437951                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     45630373                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     45630373                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data  1435.036669                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.350351                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.350351                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1944                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           35                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           71                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          430                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1390                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.474609                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         132302857                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        132302857                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     45633758                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        45633758                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20514059                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20514059                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      66147817                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         66147817                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     66147817                       # number of overall hits
+system.cpu.dcache.overall_hits::total        66147817                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          938                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           938                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1672                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1672                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2610                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2610                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2610                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2610                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     59941301                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     59941301                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    112492631                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    112492631                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    172433932                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    172433932                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    172433932                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    172433932                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     45634696                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     45634696                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     66146104                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     66146104                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     66146104                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     66146104                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000020                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000020                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000082                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000082                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     66150427                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     66150427                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     66150427                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     66150427                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000021                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000021                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000081                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000081                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000039                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000039                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65315.225630                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 65315.225630                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67300.502661                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 67300.502661                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 66604.435868                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66604.435868                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 66604.435868                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66604.435868                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          319                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63903.305970                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63903.305970                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67280.281699                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 67280.281699                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66066.640613                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66066.640613                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66066.640613                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66066.640613                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          322                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    79.750000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    80.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           15                       # number of writebacks
-system.cpu.dcache.writebacks::total                15                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          455                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          455                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data            1                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          456                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          456                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          456                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          456                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          458                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          458                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1690                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1690                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2148                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2148                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2148                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2148                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     33615250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     33615250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    109709600                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    109709600                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    143324850                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    143324850                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    143324850                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    143324850                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
+system.cpu.dcache.writebacks::total                13                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          470                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          470                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data            2                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          472                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          472                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          472                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          472                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          468                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          468                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1670                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1670                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2138                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2138                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     32985750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     32985750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    108417619                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    108417619                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    141403369                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    141403369                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    141403369                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    141403369                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000082                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000082                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000081                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000081                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73395.742358                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73395.742358                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64916.923077                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64916.923077                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66724.790503                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66724.790503                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66724.790503                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66724.790503                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70482.371795                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70482.371795                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64920.729940                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64920.729940                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66138.152011                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66138.152011                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66138.152011                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66138.152011                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 5a8c9de17..5240cde6c 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.131393                       # Nu
 sim_ticks                                131393279000                       # Number of ticks simulated
 final_tick                               131393279000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1414135                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2370219                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1406875667                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267896                       # Number of bytes of host memory used
-host_seconds                                    93.39                       # Real time elapsed on the host
+host_inst_rate                                1131336                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1896222                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1125528252                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303676                       # Number of bytes of host memory used
+host_seconds                                   116.74                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -66,5 +66,40 @@ system.cpu.num_busy_cycles                  262786559                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          12326938                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               1176721      0.53%      0.53% # Class of executed instruction
+system.cpu.op_class::IntAlu                 133863963     60.47%     61.00% # Class of executed instruction
+system.cpu.op_class::IntMult                   772953      0.35%     61.35% # Class of executed instruction
+system.cpu.op_class::IntDiv                   7031501      3.18%     64.53% # Class of executed instruction
+system.cpu.op_class::FloatAdd                 1352943      0.61%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::MemRead                 56649587     25.59%     90.73% # Class of executed instruction
+system.cpu.op_class::MemWrite                20515717      9.27%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  221363385                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index b4342fe40..9d2ef868e 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.250954                       # Nu
 sim_ticks                                250953957000                       # Number of ticks simulated
 final_tick                               250953957000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 770398                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1291257                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1463865173                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 276604                       # Number of bytes of host memory used
-host_seconds                                   171.43                       # Real time elapsed on the host
+host_inst_rate                                 652190                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1093130                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1239252699                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313428                       # Number of bytes of host memory used
+host_seconds                                   202.50                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -74,6 +74,41 @@ system.cpu.num_busy_cycles                  501907914                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          12326938                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               1176721      0.53%      0.53% # Class of executed instruction
+system.cpu.op_class::IntAlu                 133863963     60.47%     61.00% # Class of executed instruction
+system.cpu.op_class::IntMult                   772953      0.35%     61.35% # Class of executed instruction
+system.cpu.op_class::IntDiv                   7031501      3.18%     64.53% # Class of executed instruction
+system.cpu.op_class::FloatAdd                 1352943      0.61%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.14% # Class of executed instruction
+system.cpu.op_class::MemRead                 56649587     25.59%     90.73% # Class of executed instruction
+system.cpu.op_class::MemWrite                20515717      9.27%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  221363385                       # Class of executed instruction
 system.cpu.icache.tags.replacements              2836                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1455.296642                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           173489674                       # Total number of references to valid blocks.
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 349090c6e..44f9ef01c 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.870336                       # Nu
 sim_ticks                                1870335522500                       # Number of ticks simulated
 final_tick                               1870335522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3158607                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3158605                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            93543458564                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309852                       # Number of bytes of host memory used
-host_seconds                                    19.99                       # Real time elapsed on the host
+host_inst_rate                                2258331                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2258329                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            66881420828                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 346748                       # Number of bytes of host memory used
+host_seconds                                    27.97                       # Real time elapsed on the host
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_ops                                      63154034                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -307,6 +307,41 @@ system.cpu0.num_busy_cycles              57233845.415270                       #
 system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
 system.cpu0.Branches                          8650704                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              3102513      5.42%      5.42% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 37823162     66.09%     71.51% # Class of executed instruction
+system.cpu0.op_class::IntMult                   59490      0.10%     71.61% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     71.61% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  18488      0.03%     71.65% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   2221      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.65% # Class of executed instruction
+system.cpu0.op_class::MemRead                 9401052     16.43%     88.08% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5956984     10.41%     98.49% # Class of executed instruction
+system.cpu0.op_class::IprAccess                866222      1.51%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                  57230132                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    6283                       # number of quiesce instructions executed
 system.cpu0.kern.inst.hwrei                    197120                       # number of hwrei instructions executed
@@ -612,6 +647,41 @@ system.cpu1.num_busy_cycles              5936690.922345                       #
 system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.998413                       # Percentage of idle cycles
 system.cpu1.Branches                           836747                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               239814      4.04%      4.04% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  3533366     59.53%     63.57% # Class of executed instruction
+system.cpu1.op_class::IntMult                    9651      0.16%     63.73% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     63.73% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   7265      0.12%     63.85% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     63.85% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     63.85% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     63.85% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                   1421      0.02%     63.88% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.88% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1191429     20.07%     83.95% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 755540     12.73%     96.68% # Class of executed instruction
+system.cpu1.op_class::IprAccess                197280      3.32%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                   5935766                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                    2204                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                     39554                       # number of hwrei instructions executed
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index b2c0b7d09..d987ad3fa 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.829332                       # Nu
 sim_ticks                                1829332258000                       # Number of ticks simulated
 final_tick                               1829332258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3003513                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3003511                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            91515177007                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306744                       # Number of bytes of host memory used
-host_seconds                                    19.99                       # Real time elapsed on the host
+host_inst_rate                                2367650                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2367648                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            72140813877                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 343680                       # Number of bytes of host memory used
+host_seconds                                    25.36                       # Real time elapsed on the host
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -160,6 +160,41 @@ system.cpu.num_busy_cycles               60055430.608382                       #
 system.cpu.not_idle_fraction                 0.016415                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.983585                       # Percentage of idle cycles
 system.cpu.Branches                           9064385                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3199104      5.33%      5.33% # Class of executed instruction
+system.cpu.op_class::IntAlu                  39460699     65.71%     71.04% # Class of executed instruction
+system.cpu.op_class::IntMult                    60680      0.10%     71.14% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     71.14% # Class of executed instruction
+system.cpu.op_class::FloatAdd                   25609      0.04%     71.18% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     71.18% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     71.18% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     71.18% # Class of executed instruction
+system.cpu.op_class::FloatDiv                    3636      0.01%     71.19% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.19% # Class of executed instruction
+system.cpu.op_class::MemRead                  9975081     16.61%     87.80% # Class of executed instruction
+system.cpu.op_class::MemWrite                 6374117     10.61%     98.42% # Class of executed instruction
+system.cpu.op_class::IprAccess                 951217      1.58%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   60050143                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
 system.cpu.kern.inst.hwrei                     211319                       # number of hwrei instructions executed
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 85845c2fe..a1c48ce35 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,137 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.961814                       # Number of seconds simulated
-sim_ticks                                1961813569500                       # Number of ticks simulated
-final_tick                               1961813569500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.962822                       # Number of seconds simulated
+sim_ticks                                1962822184500                       # Number of ticks simulated
+final_tick                               1962822184500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1769979                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1769979                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            57024152249                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 311592                       # Number of bytes of host memory used
-host_seconds                                    34.40                       # Real time elapsed on the host
-sim_insts                                    60892925                       # Number of instructions simulated
-sim_ops                                      60892925                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 916137                       # Simulator instruction rate (inst/s)
+host_op_rate                                   916137                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            30287148246                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 346744                       # Number of bytes of host memory used
+host_seconds                                    64.81                       # Real time elapsed on the host
+sim_insts                                    59372170                       # Number of instructions simulated
+sim_ops                                      59372170                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           833088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24884096                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2650880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            31936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           337152                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28737152                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       833088                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        31936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          865024                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7735232                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7735232                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13017                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            388814                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41420                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               499                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              5268                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                449018                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          120863                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               120863                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              424652                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12684231                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1351240                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               16279                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              171857                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14648258                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         424652                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          16279                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             440931                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3942899                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3942899                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3942899                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             424652                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12684231                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1351240                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              16279                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             171857                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0.inst           724800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24150336                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2649344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           138496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1080640                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28743616                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       724800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       138496                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          863296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7747520                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7747520                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             11325                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            377349                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41396                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16885                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                449119                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          121055                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               121055                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              369264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12303884                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1349763                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               70560                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              550554                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14644024                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         369264                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          70560                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             439824                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3947133                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3947133                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3947133                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             369264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12303884                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1349763                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              70560                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             550554                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               18591157                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        449018                       # Number of read requests accepted
-system.physmem.writeReqs                       120863                       # Number of write requests accepted
-system.physmem.readBursts                      449018                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     120863                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28729600                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7552                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7733952                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28737152                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7735232                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      118                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.readReqs                        449119                       # Number of read requests accepted
+system.physmem.writeReqs                       121055                       # Number of write requests accepted
+system.physmem.readBursts                      449119                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     121055                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28736320                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7296                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7746176                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28743616                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7747520                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      114                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           6983                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28166                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28350                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28054                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               27500                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27615                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27605                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               28127                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               27851                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               28176                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27723                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27750                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              28018                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              28330                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28694                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28891                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28050                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7929                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7797                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7545                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7029                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7135                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7129                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7643                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7252                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7395                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7084                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7104                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7401                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7833                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8315                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8551                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7701                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           3360                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               28065                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               28141                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               27986                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               28553                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               28160                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               27775                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               27616                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               27528                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               27559                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               27974                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              27981                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              28021                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              28612                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              28738                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28459                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              27837                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7862                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7636                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7481                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8065                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7619                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7244                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7159                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6941                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6882                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7297                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7427                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7400                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8124                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8265                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8168                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7464                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1961806557500                       # Total gap between requests
+system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1962815073500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  449018                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  449119                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 120863                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    407987                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1708                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1544                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1052                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1160                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4326                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3779                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3770                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3964                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2524                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2058                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1914                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1871                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1569                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1543                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     1513                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1527                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                     1719                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                     1248                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       11                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 121055                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    407912                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1721                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2712                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1995                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4350                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3947                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3971                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      2533                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2190                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2091                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1633                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1613                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1890                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1879                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     2087                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                     1205                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      975                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      896                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -158,355 +158,356 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1864                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4659                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4719                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4812                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6368                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5860                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1090                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1047                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1508                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1614                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1832                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1868                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1782                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1877                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1717                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      437                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        48187                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      641.951066                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     418.430190                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     422.843508                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           8213     17.04%     17.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         7073     14.68%     31.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         2891      6.00%     37.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1720      3.57%     41.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1328      2.76%     44.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          906      1.88%     45.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          669      1.39%     47.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          536      1.11%     48.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24851     51.57%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          48187                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6896                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        65.095418                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2542.617511                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           6893     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6896                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6896                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.523637                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.253710                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.981541                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4466     64.76%     64.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                342      4.96%     69.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                377      5.47%     75.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1323     19.19%     94.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 32      0.46%     94.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 16      0.23%     95.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 12      0.17%     95.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 22      0.32%     95.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 43      0.62%     96.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 30      0.44%     96.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 27      0.39%     97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 32      0.46%     97.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 29      0.42%     97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 31      0.45%     98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  6      0.09%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  8      0.12%     98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                 10      0.15%     98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  3      0.04%     98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  4      0.06%     98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  4      0.06%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  3      0.04%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  3      0.04%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  5      0.07%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  3      0.04%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  2      0.03%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  2      0.03%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  3      0.04%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  3      0.04%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  6      0.09%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                 12      0.17%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  5      0.07%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  7      0.10%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  4      0.06%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  3      0.04%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  5      0.07%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  6      0.09%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55                  1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                  1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrQLenPdf::15                     1425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4875                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4931                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4933                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5467                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5762                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5938                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6015                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      923                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      961                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      965                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1240                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1637                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1890                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     2102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1888                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1710                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1638                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      806                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        68642                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      531.489409                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     323.678439                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     416.279001                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15609     22.74%     22.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11929     17.38%     40.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5150      7.50%     47.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3087      4.50%     52.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3390      4.94%     57.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1779      2.59%     59.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1473      2.15%     61.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1315      1.92%     63.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24910     36.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          68642                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7087                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        63.355581                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     1920.089024                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095           7082     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191            1      0.01%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-45055            1      0.01%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-61439            1      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::73728-77823            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::122880-126975            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            7087                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7087                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.078312                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.846071                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.814192                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               5314     74.98%     74.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                115      1.62%     76.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1264     17.84%     94.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 37      0.52%     94.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 12      0.17%     95.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 12      0.17%     95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 26      0.37%     95.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 96      1.35%     97.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 18      0.25%     97.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 39      0.55%     97.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 16      0.23%     98.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 10      0.14%     98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 12      0.17%     98.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  8      0.11%     98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  4      0.06%     98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 15      0.21%     98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  3      0.04%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  4      0.06%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  2      0.03%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  1      0.01%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  3      0.04%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  2      0.03%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                 10      0.14%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  6      0.08%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  6      0.08%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  2      0.03%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  2      0.03%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  2      0.03%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  4      0.06%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  1      0.01%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                 10      0.14%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  2      0.03%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  2      0.03%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55                  1      0.01%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  9      0.13%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57                 14      0.20%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::58                  3      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6896                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7845433250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16453873250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2244500000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  6363940000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       17477.02                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14176.74                       # Average bank access latency per DRAM burst
+system.physmem.wrPerTurnAround::total            7087                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7297703000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15716546750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2245025000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       16253.06                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  36653.76                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  35003.06                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          14.64                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.94                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       14.65                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.94                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.95                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       14.64                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.95                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.52                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     403422                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97436                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.87                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.62                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3442484.58                       # Average gap between requests
-system.physmem.pageHitRate                      87.91                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.55                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     18651494                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              292756                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292756                       # Transaction distribution
-system.membus.trans_dist::WriteReq              14067                       # Transaction distribution
-system.membus.trans_dist::WriteResp             14067                       # Transaction distribution
-system.membus.trans_dist::Writeback            120863                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            16150                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          11271                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            6986                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            164854                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           164030                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42532                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       930030                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       972562                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124666                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124666                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1097228                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        81954                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31164224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     31246178                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5308160                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5308160                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36554338                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36554338                       # Total data (bytes)
-system.membus.snoop_data_through_bus            36416                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            43154000                       # Layer occupancy (ticks)
+system.physmem.avgWrQLen                        25.12                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     403892                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97505                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.95                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.55                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3442484.35                       # Average gap between requests
+system.physmem.pageHitRate                      87.96                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1840580762750                       # Time in different power states
+system.physmem.memoryStateTime::REF       65542880000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       56696821000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     18645480                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              292657                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292657                       # Transaction distribution
+system.membus.trans_dist::WriteReq              12414                       # Transaction distribution
+system.membus.trans_dist::WriteResp             12414                       # Transaction distribution
+system.membus.trans_dist::Writeback            121055                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4555                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           1018                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            3360                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            164356                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           164254                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39228                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       904273                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       943501                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124647                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124647                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1068148                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        68738                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31184320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     31253058                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5306816                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      5306816                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            36559874                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               36559874                       # Total data (bytes)
+system.membus.snoop_data_through_bus            37888                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            39221000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1578633000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1574833000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3834132000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3826410374                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376702000                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          376647250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   342098                       # number of replacements
-system.l2c.tags.tagsinuse                65220.106735                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2445213                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   407285                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.003690                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               8658635750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   55273.758884                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4807.212496                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4935.163888                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      160.761256                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       43.210211                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.843411                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.073352                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.075305                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.002453                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000659                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995180                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65187                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          784                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5254                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7171                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        51861                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994675                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 25954090                       # Number of tag accesses
-system.l2c.tags.data_accesses                25954090                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             690864                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             668298                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             311515                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             104210                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1774887                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          792911                       # number of Writeback hits
-system.l2c.Writeback_hits::total               792911                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             184                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             529                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 713                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            40                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                64                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           130516                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            42247                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               172763                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              690864                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              798814                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              311515                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              146457                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1947650                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             690864                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             798814                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             311515                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             146457                       # number of overall hits
-system.l2c.overall_hits::total                1947650                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            13020                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           271630                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              507                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              237                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               285394                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2952                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1737                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4689                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          888                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          909                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1797                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         117936                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           5042                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             122978                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             13020                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            389566                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               507                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              5279                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                408372                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            13020                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           389566                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              507                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             5279                       # number of overall misses
-system.l2c.overall_misses::total               408372                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst    958908741                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  17698605243                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     37880750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     17386000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    18712780734                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      1103962                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      9942571                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     11046533                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       835964                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       161993                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       997957                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   8071982510                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    364247989                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   8436230499                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    958908741                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  25770587753                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     37880750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    381633989                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     27149011233                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    958908741                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  25770587753                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     37880750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    381633989                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    27149011233                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         703884                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         939928                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         312022                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         104447                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2060281                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       792911                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           792911                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3136                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         2266                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            5402                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          928                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          933                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1861                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       248452                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        47289                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           295741                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          703884                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1188380                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          312022                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          151736                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2356022                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         703884                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1188380                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         312022                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         151736                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2356022                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.018497                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.288990                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.001625                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.002269                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.138522                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.941327                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.766549                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.868012                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.956897                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.974277                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.965610                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.474683                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.106621                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.415830                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.018497                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.327813                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.001625                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.034791                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.173331                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.018497                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.327813                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.001625                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.034791                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.173331                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73648.904839                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 65157.034359                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74715.483235                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 73358.649789                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 65568.234560                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   373.970867                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5723.990213                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2355.839838                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   941.400901                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   178.210121                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total   555.346132                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68443.753476                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72242.758628                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 68599.509660                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 73648.904839                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 66152.045489                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 74715.483235                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 72292.856412                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 66481.079097                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 73648.904839                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 66152.045489                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 74715.483235                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 72292.856412                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 66481.079097                       # average overall miss latency
+system.l2c.tags.replacements                   342221                       # number of replacements
+system.l2c.tags.tagsinuse                65256.412579                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2544259                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   407367                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.245619                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               8652281750                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   55518.574788                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3744.543964                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4299.514442                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1171.756098                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      522.023286                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.847146                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.057137                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.065605                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.017880                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.007965                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995734                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65146                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          752                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5288                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7256                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        51736                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994049                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 26948745                       # Number of tag accesses
+system.l2c.tags.data_accesses                26948745                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             527962                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             377923                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             461443                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             449896                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1817224                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          850135                       # number of Writeback hits
+system.l2c.Writeback_hits::total               850135                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             136                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              70                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 206                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            24                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            20                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                44                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           113466                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            85009                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               198475                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              527962                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              491389                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              461443                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              534905                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2015699                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             527962                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             491389                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             461443                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             534905                       # number of overall hits
+system.l2c.overall_hits::total                2015699                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            11328                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           270740                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2172                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             1052                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               285292                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2603                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           468                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3071                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data           62                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data           80                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             142                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         107000                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          15849                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             122849                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             11328                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            377740                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2172                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             16901                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                408141                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            11328                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           377740                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2172                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            16901                       # number of overall misses
+system.l2c.overall_misses::total               408141                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst    833297996                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  17596590486                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    160787750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     79756250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    18670432482                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data       706471                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       350485                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      1056956                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       162493                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data        92496                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       254989                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   7343044869                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1158336734                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   8501381603                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    833297996                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  24939635355                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    160787750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1238092984                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     27171814085                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    833297996                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  24939635355                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    160787750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1238092984                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    27171814085                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         539290                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         648663                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         463615                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         450948                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2102516                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       850135                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           850135                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2739                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          538                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3277                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data           86                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          100                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           186                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       220466                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       100858                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           321324                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          539290                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          869129                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          463615                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          551806                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2423840                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         539290                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         869129                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         463615                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         551806                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2423840                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.021005                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.417382                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.004685                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.002333                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.135691                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.950347                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.869888                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.937138                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.720930                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.800000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.763441                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.485336                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.157142                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.382321                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.021005                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.434619                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004685                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.030629                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.168386                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.021005                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.434619                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004685                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.030629                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.168386                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73560.910664                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 64994.424488                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74027.509208                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 75813.925856                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 65443.238794                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   271.406454                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   748.899573                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   344.173233                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2620.854839                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1156.200000                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1795.697183                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68626.587561                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73085.793047                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 69201.878754                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 73560.910664                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 66023.284150                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 74027.509208                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 73255.605230                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 66574.576151                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 73560.910664                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 66023.284150                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 74027.509208                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 73255.605230                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 66574.576151                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -515,8 +516,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               79343                       # number of writebacks
-system.l2c.writebacks::total                    79343                       # number of writebacks
+system.l2c.writebacks::writebacks               79532                       # number of writebacks
+system.l2c.writebacks::total                    79532                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
@@ -526,111 +527,111 @@ system.l2c.demand_mshr_hits::total                 11                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        13017                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       271630                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst          499                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data          237                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          285383                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2952                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1737                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         4689                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          888                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          909                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1797                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       117936                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         5042                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        122978                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        13017                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       389566                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          499                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         5279                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           408361                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        13017                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       389566                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          499                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         5279                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          408361                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    793128009                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14302134757                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     30990750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     14431500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  15140685016                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     29678448                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     17371737                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     47050185                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      8880888                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      9090909                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     17971797                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6590771990                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    300610511                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   6891382501                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    793128009                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  20892906747                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     30990750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    315042011                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  22032067517                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    793128009                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  20892906747                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     30990750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    315042011                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  22032067517                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1373162000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17619500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1390781500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2149958500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    674822000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2824780500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3523120500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692441500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4215562000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018493                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.288990                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.001599                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002269                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.138517                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941327                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.766549                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.868012                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.956897                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.974277                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.965610                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.474683                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.106621                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.415830                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018493                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.327813                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001599                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.034791                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.173326                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018493                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.327813                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001599                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.034791                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.173326                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60930.168933                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52653.001351                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62105.711423                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 60892.405063                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 53053.913569                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.674797                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.161868                       # average UpgradeReq mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu0.inst        11325                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       270740                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         2164                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         1052                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          285281                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2603                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          468                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3071                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           62                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           80                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          142                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       107000                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        15849                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        122849                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        11325                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       377740                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2164                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        16901                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           408130                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        11325                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       377740                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2164                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        16901                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          408130                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    689008754                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14211795014                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    132703500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     66581750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  15100089018                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     26041101                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4800968                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     30842069                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       620062                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       800080                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      1420142                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5999010131                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    959576266                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   6958586397                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    689008754                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  20210805145                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    132703500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1026158016                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  22058675415                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    689008754                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  20210805145                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    132703500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1026158016                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  22058675415                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    941946500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    449028500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1390975000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1618779500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    858260500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2477040000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2560726000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1307289000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3868015000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.021000                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.417382                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004668                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002333                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.135686                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.950347                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.869888                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.937138                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.720930                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.763441                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.485336                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.157142                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.382321                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.021000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.434619                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004668                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.030629                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.168382                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.021000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.434619                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004668                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.030629                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.168382                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60839.625077                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.409744                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61323.243993                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63290.636882                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 52930.580789                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.264695                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10258.478632                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10043.005210                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55884.310050                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59621.283419                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 56037.522980                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60930.168933                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53631.237703                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62105.711423                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59678.350256                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 53952.428163                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60930.168933                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53631.237703                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62105.711423                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59678.350256                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 53952.428163                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56065.515243                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60544.909206                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56643.410992                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60839.625077                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53504.540544                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61323.243993                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60715.816579                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 54048.159692                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60839.625077                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53504.540544                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61323.243993                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60715.816579                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 54048.159692                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -641,44 +642,44 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                41694                       # number of replacements
-system.iocache.tags.tagsinuse                0.569649                       # Cycle average of tags in use
+system.iocache.tags.replacements                41699                       # number of replacements
+system.iocache.tags.tagsinuse                0.570023                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41710                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1755503918000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.569649                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.035603                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.035603                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1756486423000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.570023                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.035626                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.035626                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
-system.iocache.tags.data_accesses              375534                       # Number of data accesses
-system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               375552                       # Number of tag accesses
+system.iocache.tags.data_accesses              375552                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
-system.iocache.overall_misses::total            41726                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21248883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21248883                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  13129991411                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  13129991411                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  13151240294                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  13151240294                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  13151240294                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  13151240294                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
+system.iocache.overall_misses::total            41728                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21474883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21474883                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide  12370994210                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  12370994210                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide  12392469093                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  12392469093                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide  12392469093                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  12392469093                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
@@ -687,40 +688,40 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122120.017241                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122120.017241                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 315989.396684                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 315989.396684                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 315180.949384                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 315180.949384                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 315180.949384                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 315180.949384                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        388544                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122016.380682                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122016.380682                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 297723.195273                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 297723.195273                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 296982.100580                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 296982.100580                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 296982.100580                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 296982.100580                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        362942                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28481                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                28216                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.642218                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.862986                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           41523                       # number of writebacks
+system.iocache.writebacks::total                41523                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41726                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41726                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41726                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41726                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12199883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12199883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10966952411                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10966952411                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10979152294                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10979152294                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10979152294                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10979152294                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12321883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12321883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10208100710                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  10208100710                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide  10220422593                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  10220422593                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide  10220422593                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  10220422593                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -729,14 +730,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70114.270115                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70114.270115                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 263933.202036                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 263933.202036                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263124.965106                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 263124.965106                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263124.965106                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 263124.965106                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70010.698864                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70010.698864                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 245670.502262                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 245670.502262                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 244929.605852                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 244929.605852                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 244929.605852                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 244929.605852                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -754,22 +755,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7562587                       # DTB read hits
+system.cpu0.dtb.read_hits                     6067358                       # DTB read hits
 system.cpu0.dtb.read_misses                      7765                       # DTB read misses
 system.cpu0.dtb.read_acv                          210                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  524069                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5147352                       # DTB write hits
+system.cpu0.dtb.write_hits                    4265662                       # DTB write hits
 system.cpu0.dtb.write_misses                      910                       # DTB write misses
 system.cpu0.dtb.write_acv                         133                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 202595                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12709939                       # DTB hits
+system.cpu0.dtb.data_hits                    10333020                       # DTB hits
 system.cpu0.dtb.data_misses                      8675                       # DTB misses
 system.cpu0.dtb.data_acv                          343                       # DTB access violations
 system.cpu0.dtb.data_accesses                  726664                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3660806                       # ITB hits
+system.cpu0.itb.fetch_hits                    3354842                       # ITB hits
 system.cpu0.itb.fetch_misses                     3984                       # ITB misses
 system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3664790                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3358826                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -782,56 +783,91 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3923627139                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3925644369                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   48127942                       # Number of instructions committed
-system.cpu0.committedOps                     48127942                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             44644072                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                213646                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1209779                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      5646914                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    44644072                       # number of integer instructions
-system.cpu0.num_fp_insts                       213646                       # number of float instructions
-system.cpu0.num_int_register_reads           61387929                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          33243119                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              104403                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             106204                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12751056                       # number of memory refs
-system.cpu0.num_load_insts                    7590434                       # Number of load instructions
-system.cpu0.num_store_insts                   5160622                       # Number of store instructions
-system.cpu0.num_idle_cycles              3699531471.998114                       # Number of idle cycles
-system.cpu0.num_busy_cycles              224095667.001886                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.057114                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.942886                       # Percentage of idle cycles
-system.cpu0.Branches                          7246727                       # Number of branches fetched
+system.cpu0.committedInsts                   38276564                       # Number of instructions committed
+system.cpu0.committedOps                     38276564                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             35596868                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                153627                       # Number of float alu accesses
+system.cpu0.num_func_calls                     936507                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4464991                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    35596868                       # number of integer instructions
+system.cpu0.num_fp_insts                       153627                       # number of float instructions
+system.cpu0.num_int_register_reads           48919002                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          26532177                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               75066                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              75978                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     10366198                       # number of memory refs
+system.cpu0.num_load_insts                    6090760                       # Number of load instructions
+system.cpu0.num_store_insts                   4275438                       # Number of store instructions
+system.cpu0.num_idle_cycles              3742234246.498094                       # Number of idle cycles
+system.cpu0.num_busy_cycles              183410122.501907                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.046721                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.953279                       # Percentage of idle cycles
+system.cpu0.Branches                          5694814                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              2096369      5.48%      5.48% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 24995370     65.29%     70.76% # Class of executed instruction
+system.cpu0.op_class::IntMult                   39322      0.10%     70.86% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     70.86% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  12602      0.03%     70.90% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1883      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     70.90% # Class of executed instruction
+system.cpu0.op_class::MemRead                 6233117     16.28%     87.18% # Class of executed instruction
+system.cpu0.op_class::MemWrite                4280683     11.18%     98.36% # Class of executed instruction
+system.cpu0.op_class::IprAccess                626236      1.64%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                  38285582                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6803                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    166332                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   57240     40.25%     40.25% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.34% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1974      1.39%     41.73% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    424      0.30%     42.03% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  82451     57.97%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              142220                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    56707     49.09%     49.09% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.11%     49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1974      1.71%     50.91% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     424      0.37%     51.28% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   56283     48.72%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               115519                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1902164041000     96.96%     96.96% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               95225000      0.00%     96.96% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              767277500      0.04%     97.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              314374500      0.02%     97.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            58471894000      2.98%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1961812812000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.990688                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    4866                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    138364                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   44810     38.76%     38.76% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.11%     38.88% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1975      1.71%     40.58% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                     16      0.01%     40.60% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  68668     59.40%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              115600                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    44285     48.84%     48.84% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.14%     48.98% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1975      2.18%     51.16% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                      16      0.02%     51.18% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   44269     48.82%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total                90676                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1909704051500     97.29%     97.29% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               94854000      0.00%     97.30% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              764030500      0.04%     97.34% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               12585500      0.00%     97.34% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            52245891000      2.66%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1962821412500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.988284                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.682624                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.812256                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.644682                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.784394                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
 system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
@@ -863,37 +899,37 @@ system.cpu0.kern.syscall::144                       2      0.85%     99.15% # nu
 system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  506      0.34%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3107      2.06%      2.40% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.03%      2.44% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.44% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               135267     89.81%     92.25% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6701      4.45%     96.70% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.70% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     4      0.00%     96.70% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.71% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.71% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4423      2.94%     99.65% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 394      0.26%     99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb                     139      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                150615                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7022                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1372                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                   86      0.07%      0.07% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.07% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 2218      1.80%      1.88% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      51      0.04%      1.92% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.01%      1.92% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               109461     88.95%     90.88% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6662      5.41%     96.29% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.29% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     4      0.00%     96.29% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     96.30% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.30% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4016      3.26%     99.57% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 394      0.32%     99.89% # number of callpals executed
+system.cpu0.kern.callpal::imb                     139      0.11%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                123054                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             5726                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1371                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1371                      
-system.cpu0.kern.mode_good::user                 1372                      
+system.cpu0.kern.mode_good::kernel               1370                      
+system.cpu0.kern.mode_good::user                 1371                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.195244                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.239260                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.326781                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1958041026500     99.81%     99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3771781000      0.19%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.386220                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1959031016000     99.81%     99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3790392000      0.19%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3108                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    2219                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -925,48 +961,48 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   103965077                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2102306                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2102291                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             14067                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            14067                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           792911                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           16363                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         11335                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          27698                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           339143                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          297593                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1407788                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3134857                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       624045                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       452421                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5619111                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     45048576                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    120057312                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     19969408                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     16548674                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          201623970                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             201613666                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         2346432                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4795947858                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           724500                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   108070579                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2148343                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2148328                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             12414                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            12414                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           850135                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            4614                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          1062                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           5676                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           363639                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          322090                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1078600                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2181406                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       927231                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      1598323                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5785560                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     34514560                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     81611821                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     29671360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     63815893                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          209613634                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             209603138                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         2520192                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         5075991989                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy           738000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3170057255                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        5536383084                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy        1404201241                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2429088500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        4030648808                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy        2086694241                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         776393157                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                       1398487                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               55619                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              55619                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13922                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.respLayer3.occupancy        2646669064                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
+system.iobus.throughput                       1391043                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq                 7376                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7376                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               53966                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              53966                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10614                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          484                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
@@ -977,12 +1013,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        42532                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  125984                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        55688                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        39228                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83456                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83456                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  122684                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        42456                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1936                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
@@ -993,14 +1029,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        81954                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2743570                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2743570                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             13277000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total        68738                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661632                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661632                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              2730370                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2730370                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              9969000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               362000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1020,67 +1056,67 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           380082294                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           380139843                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            28465000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            26814000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43185000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            43231750                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           703274                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          508.380970                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           47433057                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           703786                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.396989                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      40278267250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.380970                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992932                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.992932                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           538677                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          508.393435                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           37746273                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           539189                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            70.005644                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      40276505250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.393435                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992956                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.992956                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          444                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          442                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         48840865                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        48840865                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     47433057                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       47433057                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     47433057                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        47433057                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     47433057                       # number of overall hits
-system.cpu0.icache.overall_hits::total       47433057                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       703904                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       703904                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       703904                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        703904                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       703904                       # number of overall misses
-system.cpu0.icache.overall_misses::total       703904                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10025783755                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10025783755                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10025783755                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10025783755                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10025783755                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10025783755                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     48136961                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     48136961                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     48136961                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     48136961                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     48136961                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     48136961                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014623                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014623                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014623                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014623                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014623                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014623                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14243.112349                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14243.112349                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14243.112349                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14243.112349                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14243.112349                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14243.112349                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         38824893                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        38824893                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     37746273                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       37746273                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     37746273                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        37746273                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     37746273                       # number of overall hits
+system.cpu0.icache.overall_hits::total       37746273                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       539310                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       539310                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       539310                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        539310                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       539310                       # number of overall misses
+system.cpu0.icache.overall_misses::total       539310                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7764312000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7764312000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7764312000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7764312000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7764312000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7764312000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     38285583                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     38285583                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     38285583                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     38285583                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     38285583                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     38285583                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014087                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014087                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014087                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014087                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014087                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014087                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14396.751405                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14396.751405                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14396.751405                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14396.751405                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14396.751405                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14396.751405                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1089,119 +1125,119 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       703904                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       703904                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       703904                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       703904                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       703904                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       703904                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8612997245                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   8612997245                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8612997245                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   8612997245                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8612997245                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   8612997245                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014623                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014623                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014623                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014623                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014623                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014623                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12236.039638                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12236.039638                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12236.039638                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12236.039638                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12236.039638                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12236.039638                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       539310                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       539310                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       539310                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       539310                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       539310                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       539310                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6681305000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6681305000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6681305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6681305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6681305000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6681305000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014087                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014087                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014087                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12388.616936                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12388.616936                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12388.616936                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12388.616936                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12388.616936                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12388.616936                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1191290                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.228160                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11513399                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1191802                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.660496                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        108508250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.228160                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986774                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.986774                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           871224                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          481.747613                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs            9466123                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           871736                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            10.858933                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        108210250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   481.747613                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.940913                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.940913                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         52084916                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        52084916                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6477391                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6477391                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4731575                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4731575                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       141550                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       141550                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149263                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       149263                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11208966                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11208966                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11208966                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11208966                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       942691                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       942691                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       258024                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       258024                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13717                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13717                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5452                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         5452                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1200715                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1200715                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1200715                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1200715                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  27259981257                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  27259981257                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10282729939                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10282729939                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    150891500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    150891500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     41989388                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     41989388                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  37542711196                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  37542711196                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  37542711196                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  37542711196                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7420082                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7420082                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4989599                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4989599                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       155267                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       155267                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       154715                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       154715                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12409681                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12409681                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12409681                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12409681                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127046                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.127046                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051712                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.051712                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088345                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088345                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.035239                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.035239                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.096756                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.096756                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.096756                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.096756                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28917.196894                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 28917.196894                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39851.835252                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 39851.835252                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11000.328060                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11000.328060                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7701.648569                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7701.648569                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31266.962765                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 31266.962765                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31266.962765                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 31266.962765                       # average overall miss latency
+system.cpu0.dcache.tags.tag_accesses         42234072                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        42234072                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5299987                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5299987                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3905819                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3905819                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       124795                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       124795                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       131586                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       131586                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9205806                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9205806                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9205806                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9205806                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       645326                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       645326                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       224198                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       224198                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7833                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         7833                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          495                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          495                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       869524                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        869524                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       869524                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       869524                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  23374169264                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  23374169264                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9262123232                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   9262123232                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    102899750                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    102899750                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      3567062                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      3567062                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  32636292496                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  32636292496                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  32636292496                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  32636292496                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5945313                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      5945313                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4130017                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4130017                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       132628                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       132628                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       132081                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       132081                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     10075330                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     10075330                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     10075330                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     10075330                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.108544                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.108544                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.054285                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.054285                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059060                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059060                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003748                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003748                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086302                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.086302                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086302                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.086302                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36220.715211                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 36220.715211                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41312.247353                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 41312.247353                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13136.697306                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13136.697306                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7206.185859                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7206.185859                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37533.515459                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 37533.515459                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37533.515459                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 37533.515459                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1210,62 +1246,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       686471                       # number of writebacks
-system.cpu0.dcache.writebacks::total           686471                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       942691                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       942691                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       258024                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       258024                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13717                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13717                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5452                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         5452                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1200715                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1200715                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1200715                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1200715                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25249299743                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25249299743                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9714288061                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9714288061                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    123443500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    123443500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     31083612                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     31083612                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34963587804                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  34963587804                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34963587804                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  34963587804                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1465602000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1465602000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2280051500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2280051500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3745653500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3745653500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127046                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127046                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051712                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051712                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088345                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088345                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.035239                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.035239                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096756                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.096756                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096756                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.096756                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26784.280048                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26784.280048                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37648.777094                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37648.777094                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8999.307429                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8999.307429                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5701.322817                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5701.322817                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29118.973115                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29118.973115                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29118.973115                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29118.973115                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       405192                       # number of writebacks
+system.cpu0.dcache.writebacks::total           405192                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       645326                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       645326                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       224198                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       224198                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         7833                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7833                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          495                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total          495                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       869524                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       869524                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       869524                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       869524                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  21958342736                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  21958342736                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8764766768                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8764766768                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     87220250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     87220250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      2576938                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2576938                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  30723109504                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  30723109504                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  30723109504                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  30723109504                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1004924500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1004924500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1718153000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1718153000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2723077500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2723077500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.108544                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.108544                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.054285                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.054285                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059060                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059060                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003748                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003748                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086302                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.086302                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086302                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.086302                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34026.744213                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34026.744213                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39093.866886                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39093.866886                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11134.973829                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11134.973829                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5205.935354                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5205.935354                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35333.250726                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35333.250726                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35333.250726                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35333.250726                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1277,22 +1313,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2348422                       # DTB read hits
+system.cpu1.dtb.read_hits                     3617105                       # DTB read hits
 system.cpu1.dtb.read_misses                      2620                       # DTB read misses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  205337                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1677006                       # DTB write hits
+system.cpu1.dtb.write_hits                    2433899                       # DTB write hits
 system.cpu1.dtb.write_misses                      235                       # DTB write misses
 system.cpu1.dtb.write_acv                          24                       # DTB write access violations
 system.cpu1.dtb.write_accesses                  89739                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4025428                       # DTB hits
+system.cpu1.dtb.data_hits                     6051004                       # DTB hits
 system.cpu1.dtb.data_misses                      2855                       # DTB misses
 system.cpu1.dtb.data_acv                           24                       # DTB access violations
 system.cpu1.dtb.data_accesses                  295076                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1801062                       # ITB hits
+system.cpu1.itb.fetch_hits                    1988116                       # ITB hits
 system.cpu1.itb.fetch_misses                     1064                       # ITB misses
 system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1802126                       # ITB accesses
+system.cpu1.itb.fetch_accesses                1989180                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1305,52 +1341,87 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3921881188                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3923841481                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   12764983                       # Number of instructions committed
-system.cpu1.committedOps                     12764983                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             11763372                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                170364                       # Number of float alu accesses
-system.cpu1.num_func_calls                     404056                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1265589                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    11763372                       # number of integer instructions
-system.cpu1.num_fp_insts                       170364                       # number of float instructions
-system.cpu1.num_int_register_reads           16177579                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           8656447                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               88600                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              90534                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4047975                       # number of memory refs
-system.cpu1.num_load_insts                    2361944                       # Number of load instructions
-system.cpu1.num_store_insts                   1686031                       # Number of store instructions
-system.cpu1.num_idle_cycles              3873256564.808130                       # Number of idle cycles
-system.cpu1.num_busy_cycles              48624623.191870                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.012398                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.987602                       # Percentage of idle cycles
-system.cpu1.Branches                          1821589                       # Number of branches fetched
+system.cpu1.committedInsts                   21095606                       # Number of instructions committed
+system.cpu1.committedOps                     21095606                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             19410796                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                175175                       # Number of float alu accesses
+system.cpu1.num_func_calls                     648522                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2286515                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    19410796                       # number of integer instructions
+system.cpu1.num_fp_insts                       175175                       # number of float instructions
+system.cpu1.num_int_register_reads           26519930                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          14289781                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               90745                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              92744                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      6073244                       # number of memory refs
+system.cpu1.num_load_insts                    3630952                       # Number of load instructions
+system.cpu1.num_store_insts                   2442292                       # Number of store instructions
+system.cpu1.num_idle_cycles              3837671905.347151                       # Number of idle cycles
+system.cpu1.num_busy_cycles              86169575.652849                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.021961                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.978039                       # Percentage of idle cycles
+system.cpu1.Branches                          3164985                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass              1250072      5.92%      5.92% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 13187049     62.50%     68.43% # Class of executed instruction
+system.cpu1.op_class::IntMult                   30193      0.14%     68.57% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     68.57% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                  13163      0.06%     68.63% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     68.63% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     68.63% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     68.63% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                   1759      0.01%     68.64% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.64% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3726131     17.66%     86.30% # Class of executed instruction
+system.cpu1.op_class::MemWrite                2443312     11.58%     97.88% # Class of executed instruction
+system.cpu1.op_class::IprAccess                446806      2.12%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                  21098485                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2741                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     77081                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   26132     38.19%     38.19% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1969      2.88%     41.07% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    506      0.74%     41.81% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  39821     58.19%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               68428                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    25288     48.13%     48.13% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1969      3.75%     51.87% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     506      0.96%     52.84% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   24782     47.16%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                52545                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1909614205500     97.38%     97.38% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              700881500      0.04%     97.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              353850000      0.02%     97.44% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            50271627000      2.56%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1960940564000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.967702                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    3863                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                    100735                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   37219     40.29%     40.29% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1970      2.13%     42.42% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                     86      0.09%     42.51% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  53109     57.49%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               92384                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    36367     48.68%     48.68% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1970      2.64%     51.32% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                      86      0.12%     51.43% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   36281     48.57%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                74704                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1906656399000     97.18%     97.18% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              706249000      0.04%     97.22% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               59367000      0.00%     97.22% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            54498695500      2.78%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1961920710500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.977108                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.622335                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.767887                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.683142                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.808625                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
 system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
@@ -1366,87 +1437,87 @@ system.cpu1.kern.syscall::74                        9      9.78%     96.74% # nu
 system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  424      0.60%      0.60% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.60% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.60% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1955      2.77%      3.37% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      3.38% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.39% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                62267     88.12%     91.51% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2146      3.04%     94.54% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.54% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     3      0.00%     94.55% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.55% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3685      5.22%     99.77% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 121      0.17%     99.94% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                   16      0.02%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 2020      2.13%      2.15% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.00%      2.16% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      2.16% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                87061     91.90%     94.06% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2187      2.31%     96.37% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     96.37% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     3      0.00%     96.38% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     96.38% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3266      3.45%     99.83% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 121      0.13%     99.95% # number of callpals executed
+system.cpu1.kern.callpal::imb                      42      0.04%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 70661                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1917                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                368                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2889                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                798                      
-system.cpu1.kern.mode_good::user                  368                      
-system.cpu1.kern.mode_good::idle                  430                      
-system.cpu1.kern.mode_switch_good::kernel     0.416275                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 94734                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             2415                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                366                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2037                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                414                      
+system.cpu1.kern.mode_good::user                  366                      
+system.cpu1.kern.mode_good::idle                   48                      
+system.cpu1.kern.mode_switch_good::kernel     0.171429                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.148840                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.308465                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       17543884000      0.90%      0.90% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1484004500      0.08%      0.97% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1941017048000     99.03%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1956                       # number of times the context was actually changed
-system.cpu1.icache.tags.replacements           311472                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          449.263709                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           12455839                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           311983                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.924736                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1960006992500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   449.263709                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.877468                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.877468                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           74                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3          437                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         13079885                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        13079885                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     12455839                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       12455839                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     12455839                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        12455839                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     12455839                       # number of overall hits
-system.cpu1.icache.overall_hits::total       12455839                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       312023                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       312023                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       312023                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        312023                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       312023                       # number of overall misses
-system.cpu1.icache.overall_misses::total       312023                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4106650741                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4106650741                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4106650741                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4106650741                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4106650741                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4106650741                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     12767862                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     12767862                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     12767862                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     12767862                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     12767862                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     12767862                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024438                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024438                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024438                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024438                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024438                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024438                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13161.371889                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13161.371889                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13161.371889                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13161.371889                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13161.371889                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13161.371889                       # average overall miss latency
+system.cpu1.kern.mode_switch_good::idle      0.023564                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.171856                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       65780447000      3.35%      3.35% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1486717000      0.08%      3.43% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1893764152500     96.57%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    2021                       # number of times the context was actually changed
+system.cpu1.icache.tags.replacements           463064                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          500.061225                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           20634869                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           463576                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            44.512376                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      97712638250                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   500.061225                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.976682                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.976682                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3          404                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses         21562101                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        21562101                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     20634869                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       20634869                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     20634869                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        20634869                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     20634869                       # number of overall hits
+system.cpu1.icache.overall_hits::total       20634869                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       463616                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       463616                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       463616                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        463616                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       463616                       # number of overall misses
+system.cpu1.icache.overall_misses::total       463616                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6201828741                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6201828741                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6201828741                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6201828741                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6201828741                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6201828741                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     21098485                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     21098485                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     21098485                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     21098485                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     21098485                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     21098485                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021974                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.021974                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021974                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.021974                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021974                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.021974                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13377.080905                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13377.080905                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13377.080905                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13377.080905                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13377.080905                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13377.080905                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1455,118 +1526,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       312023                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       312023                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       312023                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       312023                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       312023                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       312023                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3482409259                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3482409259                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3482409259                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3482409259                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3482409259                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3482409259                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024438                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024438                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024438                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024438                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024438                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024438                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11160.745391                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11160.745391                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11160.745391                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11160.745391                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11160.745391                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11160.745391                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       463616                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       463616                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       463616                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       463616                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       463616                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       463616                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5273752259                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5273752259                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5273752259                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5273752259                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5273752259                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5273752259                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.021974                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.021974                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.021974                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.021974                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.021974                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.021974                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11375.259394                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11375.259394                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11375.259394                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11375.259394                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11375.259394                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11375.259394                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           155135                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          486.308895                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            3855441                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           155464                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            24.799574                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     1048852146500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.308895                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.949822                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.949822                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          329                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3          297                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.642578                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         16322717                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        16322717                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2189668                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2189668                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1567568                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1567568                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        46969                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        46969                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        49480                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        49480                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3757236                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3757236                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3757236                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3757236                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       113735                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       113735                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        55930                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        55930                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8863                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         8863                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5883                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         5883                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       169665                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        169665                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       169665                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       169665                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1371834000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1371834000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1009197248                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   1009197248                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     80472000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     80472000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     43306909                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     43306909                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   2381031248                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   2381031248                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   2381031248                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   2381031248                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2303403                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2303403                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1623498                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1623498                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        55832                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        55832                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        55363                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        55363                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3926901                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3926901                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3926901                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3926901                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049377                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.049377                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034450                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.034450                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.158744                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.158744                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106262                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106262                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.043206                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.043206                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043206                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.043206                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.669671                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.669671                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18043.934347                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18043.934347                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9079.544172                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9079.544172                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7361.364780                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7361.364780                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14033.720850                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14033.720850                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14033.720850                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14033.720850                       # average overall miss latency
+system.cpu1.dcache.tags.replacements           581734                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          492.027113                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            5462976                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           582077                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs             9.385315                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      61159690250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   492.027113                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.960990                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.960990                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          343                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3          300                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.669922                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         24828652                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        24828652                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3080166                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3080166                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2260006                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2260006                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        60928                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        60928                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71558                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        71558                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5340172                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5340172                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5340172                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5340172                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       473210                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       473210                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       102503                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       102503                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11672                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11672                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          567                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          567                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       575713                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        575713                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       575713                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       575713                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   5938920500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   5938920500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2340100234                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2340100234                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    149905750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    149905750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      4163080                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total      4163080                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   8279020734                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   8279020734                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   8279020734                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   8279020734                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3553376                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3553376                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2362509                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2362509                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        72600                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        72600                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        72125                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        72125                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      5915885                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      5915885                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      5915885                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      5915885                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.133172                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.133172                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.043387                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.043387                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.160771                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.160771                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.007861                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.007861                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.097316                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.097316                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.097316                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.097316                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12550.285286                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12550.285286                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22829.578003                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22829.578003                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.193112                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.193112                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7342.292769                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7342.292769                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14380.465152                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14380.465152                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14380.465152                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14380.465152                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1575,62 +1646,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       106440                       # number of writebacks
-system.cpu1.dcache.writebacks::total           106440                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       113735                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       113735                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        55930                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        55930                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8863                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8863                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5883                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         5883                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       169665                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       169665                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       169665                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       169665                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1144290000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1144290000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    895105752                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total    895105752                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62746000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     62746000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31539091                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31539091                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2039395752                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2039395752                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2039395752                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2039395752                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18776500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18776500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    713537000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    713537000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    732313500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    732313500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049377                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049377                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034450                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034450                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.158744                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.158744                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106262                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106262                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043206                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.043206                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043206                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.043206                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.019035                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.019035                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16004.036331                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16004.036331                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7079.544172                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7079.544172                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5361.055754                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5361.055754                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12020.132331                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12020.132331                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12020.132331                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12020.132331                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       444943                       # number of writebacks
+system.cpu1.dcache.writebacks::total           444943                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       473210                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       473210                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       102503                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       102503                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11672                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11672                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          567                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total          567                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       575713                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       575713                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       575713                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       575713                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   4992146500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   4992146500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2128603766                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2128603766                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    126561250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    126561250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      3028920                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      3028920                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7120750266                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   7120750266                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7120750266                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   7120750266                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    479658500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    479658500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    907861000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    907861000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1387519500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1387519500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.133172                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.133172                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.043387                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.043387                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.160771                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.160771                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.007861                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.007861                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.097316                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.097316                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.097316                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.097316                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10549.537203                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10549.537203                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20766.258217                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20766.258217                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.150274                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.150274                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5342.010582                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5342.010582                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12368.576471                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12368.576471                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12368.576471                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12368.576471                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 5b0dc7b99..24f1d16b8 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,127 +1,127 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.920416                       # Number of seconds simulated
-sim_ticks                                1920416181000                       # Number of ticks simulated
-final_tick                               1920416181000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.919447                       # Number of seconds simulated
+sim_ticks                                1919446558000                       # Number of ticks simulated
+final_tick                               1919446558000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1752736                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1752735                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            59896862792                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308520                       # Number of bytes of host memory used
-host_seconds                                    32.06                       # Real time elapsed on the host
-sim_insts                                    56196255                       # Number of instructions simulated
-sim_ops                                      56196255                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 885398                       # Simulator instruction rate (inst/s)
+host_op_rate                                   885398                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            30291378157                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 344696                       # Number of bytes of host memory used
+host_seconds                                    63.37                       # Real time elapsed on the host
+sim_insts                                    56104177                       # Number of instructions simulated
+sim_ops                                      56104177                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            850752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24860224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24858240                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28363328                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28361344                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       850752                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          850752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7405888                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7405888                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      7404032                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7404032                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst              13293                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388441                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388410                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                443177                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115717                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115717                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               443004                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12945227                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1381134                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14769365                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          443004                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             443004                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3856397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3856397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3856397                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              443004                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12945227                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1381134                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18625763                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        443177                       # Number of read requests accepted
-system.physmem.writeReqs                       115717                       # Number of write requests accepted
-system.physmem.readBursts                      443177                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     115717                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28355584                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7744                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7404416                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28363328                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7405888                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      121                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                443146                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115688                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115688                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               443228                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12950733                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1381832                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14775792                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          443228                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             443228                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3857379                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3857379                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3857379                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              443228                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12950733                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1381832                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18633171                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        443146                       # Number of read requests accepted
+system.physmem.writeReqs                       115688                       # Number of write requests accepted
+system.physmem.readBursts                      443146                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     115688                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28353856                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7488                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7402304                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28361344                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7404032                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      117                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs            130                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               27851                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28132                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28319                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               28010                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27531                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27552                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               26732                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               26855                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27890                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27110                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27744                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              27465                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27482                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28199                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28116                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28068                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7630                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7636                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7854                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7535                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6994                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6317                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6319                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7309                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6529                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7110                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6915                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7060                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7819                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7860                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7680                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               27768                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               28019                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               28336                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               28020                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27518                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               27546                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               26737                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               26852                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               27860                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               27104                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              27841                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              27413                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              27378                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              28201                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28236                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              28200                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7550                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7529                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7869                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7540                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7115                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6983                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6321                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6313                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7293                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6538                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7205                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6861                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6964                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7821                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7979                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7780                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1920404309000                       # Total gap between requests
+system.physmem.totGap                    1919434637000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  443177                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  443146                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 115717                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402196                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1714                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1586                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1056                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3790                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3793                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3969                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2575                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2033                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1897                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1793                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1556                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1515                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     1524                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1560                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                     1710                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                     1268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 115688                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    401962                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1642                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2685                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1248                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1966                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4407                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3974                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3974                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      2507                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2187                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2134                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2102                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1622                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1616                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1907                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1876                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     2136                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                     1224                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      966                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      883                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -148,190 +148,191 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4492                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6087                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4874                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6417                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5555                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1092                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1517                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1561                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1709                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1718                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1911                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       29                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        46117                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      658.429646                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     435.074403                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     420.347464                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7559     16.39%     16.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         6338     13.74%     30.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         2663      5.77%     35.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1600      3.47%     39.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1319      2.86%     42.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          861      1.87%     44.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          594      1.29%     45.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          461      1.00%     46.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24722     53.61%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          46117                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6598                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        67.149288                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2598.278449                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           6595     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6598                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6598                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.534707                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.278859                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.820387                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4179     63.34%     63.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                322      4.88%     68.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                428      6.49%     74.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1303     19.75%     94.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 22      0.33%     94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 17      0.26%     95.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 11      0.17%     95.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 27      0.41%     95.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 43      0.65%     96.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 28      0.42%     96.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 21      0.32%     97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 25      0.38%     97.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 19      0.29%     97.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 43      0.65%     98.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.06%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 12      0.18%     98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                 10      0.15%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  1      0.02%     98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  5      0.08%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  4      0.06%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  4      0.06%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  5      0.08%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  2      0.03%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  9      0.14%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  4      0.06%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  4      0.06%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  1      0.02%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  2      0.03%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  3      0.05%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  1      0.02%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  6      0.09%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  8      0.12%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  5      0.08%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  6      0.09%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  3      0.05%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54                  4      0.06%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55                  2      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6598                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7790286250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16274878750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2215280000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  6269312500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       17583.07                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14150.16                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::15                     1354                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4579                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4592                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4608                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4699                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4858                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5448                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5621                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5715                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      861                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      945                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      959                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1033                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      949                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1390                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     2098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1909                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1878                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1629                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      418                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       18                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        66429                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      538.261302                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     328.855989                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.099114                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14887     22.41%     22.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11472     17.27%     39.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4684      7.05%     46.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3132      4.71%     51.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3072      4.62%     56.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1874      2.82%     58.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1342      2.02%     60.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1444      2.17%     63.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24522     36.91%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          66429                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6775                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        65.389077                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       16.529238                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2564.130292                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           6772     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6775                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6775                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.071734                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.848509                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.695111                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               5062     74.72%     74.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                127      1.87%     76.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1207     17.82%     94.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 25      0.37%     94.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 12      0.18%     94.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 16      0.24%     95.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 18      0.27%     95.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 98      1.45%     96.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 22      0.32%     97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 41      0.61%     97.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 20      0.30%     98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  8      0.12%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  7      0.10%     98.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  8      0.12%     98.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  7      0.10%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 15      0.22%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  9      0.13%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.01%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.01%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.01%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  1      0.01%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  1      0.01%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  4      0.06%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  9      0.13%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  8      0.12%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  2      0.03%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  2      0.03%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  2      0.03%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  1      0.01%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  1      0.01%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  8      0.12%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  7      0.10%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  1      0.01%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  2      0.03%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  2      0.03%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52                  1      0.01%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54                  1      0.01%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  7      0.10%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57                  9      0.13%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::59                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6775                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7315796250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15622590000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2215145000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       16513.13                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  36733.23                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  35263.13                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          14.77                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.86                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       14.77                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       14.78                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.86                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.59                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     398457                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94179                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.93                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.39                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3436079.67                       # Average gap between requests
-system.physmem.pageHitRate                      88.16                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.57                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     18667397                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              292363                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292363                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9650                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9650                       # Transaction distribution
-system.membus.trans_dist::Writeback            115717                       # Transaction distribution
+system.physmem.avgWrQLen                        23.40                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     398273                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93988                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.90                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.24                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3434713.42                       # Average gap between requests
+system.physmem.pageHitRate                      88.11                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1800016178000                       # Time in different power states
+system.physmem.memoryStateTime::REF       64094420000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       55332653250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     18674823                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              292356                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292356                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9649                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9649                       # Transaction distribution
+system.membus.trans_dist::Writeback            115688                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            158297                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           158297                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878206                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911366                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq            158273                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           158273                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33158                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878115                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911273                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124680                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1036046                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44564                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30460096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30504660                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1035953                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44556                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30456256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30500812                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            35813780                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               35813780                       # Total data (bytes)
+system.membus.tot_pkt_size::total            35809932                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               35809932                       # Total data (bytes)
 system.membus.snoop_data_through_bus            35392                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            32377500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            32376000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1492987250                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1491996000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3752965347                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3751677600                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376688000                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          376660500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.344147                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.344872                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1754500427000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.344147                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.084009                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.084009                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1753525004000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.344872                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.084054                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.084054                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -345,14 +346,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21134633                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21134633                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  13148459442                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  13148459442                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  13169594075                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  13169594075                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  13169594075                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  13169594075                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21253133                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21253133                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide  12447285431                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  12447285431                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide  12468538564                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  12468538564                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide  12468538564                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  12468538564                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -369,19 +370,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122165.508671                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 316433.852570                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 315628.378071                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 315628.378071                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        393896                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122850.479769                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 299559.237365                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 298826.568340                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 298826.568340                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        365803                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28296                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                28265                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.920554                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.941907                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -395,14 +396,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137633                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12137633                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10985430442                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10985430442                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10997568075                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10997568075                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10997568075                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10997568075                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12255133                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12255133                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10284312431                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  10284312431                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide  10296567564                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  10296567564                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide  10296567564                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  10296567564                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -411,14 +412,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 263572.632115                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 263572.632115                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 246772.140539                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 246772.140539                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -437,22 +438,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9066711                       # DTB read hits
-system.cpu.dtb.read_misses                      10324                       # DTB read misses
+system.cpu.dtb.read_hits                      9052923                       # DTB read hits
+system.cpu.dtb.read_misses                      10354                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
-system.cpu.dtb.write_hits                     6357503                       # DTB write hits
-system.cpu.dtb.write_misses                      1142                       # DTB write misses
+system.cpu.dtb.read_accesses                   728911                       # DTB read accesses
+system.cpu.dtb.write_hits                     6349403                       # DTB write hits
+system.cpu.dtb.write_misses                      1143                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     15424214                       # DTB hits
-system.cpu.dtb.data_misses                      11466                       # DTB misses
+system.cpu.dtb.write_accesses                  291932                       # DTB write accesses
+system.cpu.dtb.data_hits                     15402326                       # DTB hits
+system.cpu.dtb.data_misses                      11497                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020784                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974520                       # ITB hits
+system.cpu.dtb.data_accesses                  1020843                       # DTB accesses
+system.cpu.itb.fetch_hits                     4974965                       # ITB hits
 system.cpu.itb.fetch_misses                      5010                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979530                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4979975                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -465,52 +466,87 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3840832362                       # number of cpu cycles simulated
+system.cpu.numCycles                       3838893116                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56196255                       # Number of instructions committed
-system.cpu.committedOps                      56196255                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              52067788                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324393                       # Number of float alu accesses
-system.cpu.num_func_calls                     1483738                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6469789                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     52067788                       # number of integer instructions
-system.cpu.num_fp_insts                        324393                       # number of float instructions
-system.cpu.num_int_register_reads            71342399                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38531411                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163609                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166486                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15476821                       # number of memory refs
-system.cpu.num_load_insts                     9103557                       # Number of load instructions
-system.cpu.num_store_insts                    6373264                       # Number of store instructions
-system.cpu.num_idle_cycles               3589010980.998131                       # Number of idle cycles
-system.cpu.num_busy_cycles               251821381.001869                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.065564                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.934436                       # Percentage of idle cycles
-system.cpu.Branches                           8424076                       # Number of branches fetched
+system.cpu.committedInsts                    56104177                       # Number of instructions committed
+system.cpu.committedOps                      56104177                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              51979169                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324594                       # Number of float alu accesses
+system.cpu.num_func_calls                     1481286                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6461218                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     51979169                       # number of integer instructions
+system.cpu.num_fp_insts                        324594                       # number of float instructions
+system.cpu.num_int_register_reads            71209746                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38460532                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163708                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166588                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      15454993                       # number of memory refs
+system.cpu.num_load_insts                     9089820                       # Number of load instructions
+system.cpu.num_store_insts                    6365173                       # Number of store instructions
+system.cpu.num_idle_cycles               3587243859.498131                       # Number of idle cycles
+system.cpu.num_busy_cycles               251649256.501869                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.065553                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.934447                       # Percentage of idle cycles
+system.cpu.Branches                           8413035                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3197761      5.70%      5.70% # Class of executed instruction
+system.cpu.op_class::IntAlu                  36186344     64.48%     70.18% # Class of executed instruction
+system.cpu.op_class::IntMult                    61011      0.11%     70.29% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     70.29% # Class of executed instruction
+system.cpu.op_class::FloatAdd                   25613      0.05%     70.34% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::FloatDiv                    3636      0.01%     70.34% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.34% # Class of executed instruction
+system.cpu.op_class::MemRead                  9316905     16.60%     86.95% # Class of executed instruction
+system.cpu.op_class::MemWrite                 6371245     11.35%     98.30% # Class of executed instruction
+system.cpu.op_class::IprAccess                 953526      1.70%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   56116041                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     212001                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74899     40.89%     40.89% # number of times we switched to this ipl
+system.cpu.kern.inst.hwrei                     212017                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74895     40.89%     40.89% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1932      1.05%     42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106222     57.99%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183184                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73532     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1931      1.05%     42.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  106210     57.99%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183167                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73528     49.31%     49.31% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1932      1.30%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73532     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149127                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1858066400000     96.75%     96.75% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                91407000      0.00%     96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               737349500      0.04%     96.80% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             61520290500      3.20%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1920415447000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981749                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1931      1.29%     50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73528     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149118                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1857252195000     96.76%     96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                91387500      0.00%     96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               737178000      0.04%     96.80% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             61365063500      3.20%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1919445824000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981748                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692248                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814083                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.692289                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814110                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -546,33 +582,33 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4176      2.16%      2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4179      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175963     91.22%     93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6833      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175948     91.21%     93.41% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5157      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192909                       # number of callpals executed
+system.cpu.kern.callpal::total                 192895                       # number of callpals executed
 system.cpu.kern.mode_switch::kernel              5904                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1911                      
+system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1912                      
 system.cpu.kern.mode_good::user                  1741                      
-system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.323679                       # fraction of useful protection mode switches
+system.cpu.kern.mode_good::idle                   171                      
+system.cpu.kern.mode_switch_good::kernel     0.323848                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392402                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        46067941500      2.40%      2.40% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5182686000      0.27%      2.67% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1869164817500     97.33%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.392527                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        46108525500      2.40%      2.40% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5189217000      0.27%      2.67% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1868148079500     97.33%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4180                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -604,12 +640,12 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.throughput                       1409159                       # Throughput (bytes/s)
+system.iobus.throughput                       1409867                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51202                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51202                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5156                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51201                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51201                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5154                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -621,11 +657,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33160                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33158                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116610                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116608                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -637,12 +673,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        44564                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        44556                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2706172                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2706172                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              4767000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total              2706164                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2706164                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              4765000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -664,67 +700,67 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           380034075                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           380199064                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23510000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23509000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43162000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            43233500                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            928494                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.301721                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            55278924                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            929005                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             59.503365                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       39895254250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.301721                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.992777                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.992777                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            927875                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.303976                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            55187496                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            928386                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             59.444559                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       39855277250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.303976                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.992781                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.992781                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          436                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          57137254                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         57137254                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     55278924                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55278924                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55278924                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55278924                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55278924                       # number of overall hits
-system.cpu.icache.overall_hits::total        55278924                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       929165                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        929165                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       929165                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         929165                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       929165                       # number of overall misses
-system.cpu.icache.overall_misses::total        929165                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  12919006759                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  12919006759                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  12919006759                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  12919006759                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  12919006759                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  12919006759                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56208089                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56208089                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56208089                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56208089                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     56208089                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56208089                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016531                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016531                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016531                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016531                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016531                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016531                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.888716                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13903.888716                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.888716                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13903.888716                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.888716                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13903.888716                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          57044588                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         57044588                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     55187496                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55187496                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      55187496                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         55187496                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     55187496                       # number of overall hits
+system.cpu.icache.overall_hits::total        55187496                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       928546                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        928546                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       928546                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         928546                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       928546                       # number of overall misses
+system.cpu.icache.overall_misses::total        928546                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  12910342260                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  12910342260                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  12910342260                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  12910342260                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  12910342260                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  12910342260                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     56116042                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     56116042                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     56116042                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     56116042                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     56116042                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     56116042                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016547                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016547                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.016547                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016547                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.016547                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016547                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13903.826262                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13903.826262                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -733,135 +769,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929165                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       929165                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       929165                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       929165                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       929165                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       929165                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11055577241                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11055577241                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11055577241                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11055577241                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11055577241                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11055577241                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016531                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016531                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016531                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016531                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016531                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016531                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.400436                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.400436                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.400436                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.400436                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.400436                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.400436                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928546                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       928546                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       928546                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       928546                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       928546                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       928546                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11048086740                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11048086740                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11048086740                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11048086740                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11048086740                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11048086740                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016547                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016547                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016547                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.016547                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016547                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.016547                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.265396                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.265396                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.265396                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.265396                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.265396                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.265396                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           336265                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65295.577509                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2447728                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           401427                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.097567                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       6793166750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 55588.679267                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4757.001179                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4949.897063                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.848216                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072586                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.075529                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996331                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           336232                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65296.289611                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2446119                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           401393                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.094075                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       6784872750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 55555.447127                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4766.385283                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4974.457201                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.847709                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072729                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.075904                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996342                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65161                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1074                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4882                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3251                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55777                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         25952661                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        25952661                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       915852                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       814775                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1730627                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       835359                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       835359                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4875                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3257                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55778                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994278                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         25936539                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        25936539                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       915233                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       814520                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1729753                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       834591                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       834591                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187681                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187681                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       915852                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1002456                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1918308                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       915852                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1002456                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1918308                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187383                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187383                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       915233                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1001903                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1917136                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       915233                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1001903                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1917136                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst        13293                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       271967                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       285260                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       271960                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       285253                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116864                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116864                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       116840                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       116840                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst        13293                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       388831                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        402124                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       388800                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        402093                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst        13293                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       388831                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       402124                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    967872241                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17714808491                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  18682680732                       # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.data       388800                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       402093                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    967190740                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17699357246                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  18666547986                       # number of ReadReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       190498                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       190498                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8011039626                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8011039626                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    967872241                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  25725848117                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  26693720358                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    967872241                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  25725848117                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  26693720358                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       929145                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1086742                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2015887                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       835359                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       835359                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8068029125                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8068029125                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    967190740                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  25767386371                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  26734577111                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    967190740                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  25767386371                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  26734577111                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       928526                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1086480                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2015006                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       834591                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       834591                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304545                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304545                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       929145                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1391287                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2320432                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       929145                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1391287                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2320432                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014307                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250259                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.141506                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304223                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304223                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       928526                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1390703                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2319229                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       928526                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1390703                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2319229                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014316                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250313                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.141564                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383733                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383733                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014307                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.279476                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.173297                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014307                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.279476                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.173297                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72810.670353                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65135.874908                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 65493.517254                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384060                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.384060                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014316                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.279571                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.173374                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014316                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.279571                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.173374                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.402693                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65080.737042                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 65438.568520                       # average ReadReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68550.106329                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68550.106329                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72810.670353                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66162.029563                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66381.813465                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72810.670353                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66162.029563                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66381.813465                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69051.943898                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69051.943898                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.402693                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66274.141901                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66488.541484                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.402693                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66274.141901                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66488.541484                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -870,66 +906,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        74205                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74205                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        74176                       # number of writebacks
+system.cpu.l2cache.writebacks::total            74176                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13293                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271967                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       285260                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271960                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       285253                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116864                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116864                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116840                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       116840                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst        13293                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388831                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       402124                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       388800                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       402093                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst        13293                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388831                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       402124                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    801329759                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14314442009                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15115771768                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data       388800                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       402093                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    800656260                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14299493254                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15100149514                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       230011                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       230011                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6549827374                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6549827374                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    801329759                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20864269383                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  21665599142                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    801329759                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20864269383                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  21665599142                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334146000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334146000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895641500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895641500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229787500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229787500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014307                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250259                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141506                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6607242375                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6607242375                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    800656260                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20906735629                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  21707391889                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    800656260                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20906735629                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  21707391889                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334145500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334145500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895432500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895432500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229578000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229578000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014316                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250313                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141564                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383733                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383733                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014307                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279476                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.173297                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014307                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279476                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.173297                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60282.085233                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52633.010656                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52989.454421                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.384060                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.384060                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014316                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279571                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.173374                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014316                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279571                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.173374                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60231.419544                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52579.398640                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52935.988452                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56046.578707                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56046.578707                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60282.085233                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53658.965934                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53877.906173                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60282.085233                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53658.965934                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53877.906173                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56549.489687                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56549.489687                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -937,13 +973,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1390774                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.978892                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14051964                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1391286                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             10.099982                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         107796250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.978892                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements           1390190                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.978877                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            14030691                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1390702                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             10.088927                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         107775250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.978877                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999959                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999959                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -951,72 +987,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          187
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63164291                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63164291                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7816324                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7816324                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5853358                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5853358                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183027                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183027                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199238                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199238                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13669682                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13669682                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13669682                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13669682                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069509                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069509                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304562                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304562                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17233                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17233                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1374071                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1374071                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1374071                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1374071                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  29019471009                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  29019471009                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10854033885                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10854033885                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228736500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    228736500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39873504894                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39873504894                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39873504894                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39873504894                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8885833                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8885833                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6157920                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6157920                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200260                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200260                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199238                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199238                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15043753                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15043753                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15043753                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15043753                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120361                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120361                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049459                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049459                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086053                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086053                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091338                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091338                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091338                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091338                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27133.451901                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 27133.451901                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35638.175101                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35638.175101                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.167760                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.167760                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29018.518617                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29018.518617                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 29018.518617                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29018.518617                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63076279                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63076279                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7802806                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7802806                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5845593                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5845593                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183040                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183040                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199235                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199235                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13648399                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13648399                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13648399                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13648399                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069264                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069264                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304240                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304240                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17216                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17216                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1373504                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1373504                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1373504                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1373504                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  29001409504                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  29001409504                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10907701386                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10907701386                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228213250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    228213250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39909110890                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39909110890                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39909110890                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39909110890                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8872070                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8872070                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6149833                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6149833                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200256                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200256                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199235                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199235                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15021903                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15021903                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15021903                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15021903                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120520                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120520                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049471                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049471                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085970                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085970                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091433                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091433                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091433                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091433                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29056.421306                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29056.421306                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -1025,54 +1061,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       835359                       # number of writebacks
-system.cpu.dcache.writebacks::total            835359                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069509                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069509                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304562                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304562                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17233                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17233                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1374071                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1374071                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1374071                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1374071                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26755042991                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  26755042991                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10192844115                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10192844115                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    194257500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    194257500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36947887106                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  36947887106                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36947887106                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  36947887106                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424236000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424236000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011441500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011441500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435677500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435677500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120361                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120361                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049459                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049459                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086053                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086053                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091338                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091338                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091338                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091338                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       834591                       # number of writebacks
+system.cpu.dcache.writebacks::total            834591                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069264                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069264                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304240                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304240                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17216                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17216                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1373504                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1373504                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1373504                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1373504                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26737269496                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  26737269496                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10246531614                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10246531614                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    193767750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    193767750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36983801110                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  36983801110                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36983801110                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  36983801110                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424235500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424235500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011220500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011220500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435456000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435456000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120520                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120520                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049471                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049471                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085970                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085970                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091433                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091433                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091433                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091433                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1080,31 +1116,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               105199341                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2023010                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2022993                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9650                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9650                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       835359                       # Transaction distribution
+system.cpu.toL2Bus.throughput               105186760                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2022129                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2022112                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9649                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9649                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       834591                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       346097                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304546                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1858310                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3651284                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5509594                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59465280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142559956                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      202025236                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         202015188                       # Total data (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq       345775                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304224                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1857072                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3649346                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5506418                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59425664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142473420                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      201899084                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         201889036                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus        11328                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2426388000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy     2424633500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1396297259                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1395400760                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2187438394                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2186975140                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 49e1054f0..547f88656 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,33 +4,15 @@ sim_seconds                                  0.912098                       # Nu
 sim_ticks                                912098398000                       # Number of ticks simulated
 final_tick                               912098398000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1169212                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1505339                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            17301899059                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 421332                       # Number of bytes of host memory used
-host_seconds                                    52.72                       # Real time elapsed on the host
+host_inst_rate                                1024713                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1319299                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15163617701                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 465872                       # Number of bytes of host memory used
+host_seconds                                    60.15                       # Real time elapsed on the host
 sim_insts                                    61636937                       # Number of instructions simulated
 sim_ops                                      79356422                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           22                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           53                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               75                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           22                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           53                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           75                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           22                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           53                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              75                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
@@ -86,6 +68,24 @@ system.physmem.bw_total::cpu1.dtb.walker          211                       # To
 system.physmem.bw_total::cpu1.inst             235277                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.data            6989035                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               62341647                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           22                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           53                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               75                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           22                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           53                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           75                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           22                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           53                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              75                       # Total bandwidth to/from this memory (bytes/s)
 system.membus.throughput                     64987015                       # Throughput (bytes/s)
 system.membus.data_through_bus               59274552                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
@@ -397,6 +397,41 @@ system.cpu0.num_busy_cycles              39676799.500046                       #
 system.cpu0.not_idle_fraction                0.021757                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.978243                       # Percentage of idle cycles
 system.cpu0.Branches                          5492144                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                16326      0.04%      0.04% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 24520115     62.53%     62.57% # Class of executed instruction
+system.cpu0.op_class::IntMult                   45259      0.12%     62.69% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              1421      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     62.69% # Class of executed instruction
+system.cpu0.op_class::MemRead                 8359235     21.32%     84.01% # Class of executed instruction
+system.cpu0.op_class::MemWrite                6270624     15.99%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                  39212980                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   50449                       # number of quiesce instructions executed
 system.cpu0.icache.tags.replacements           428546                       # number of replacements
@@ -627,6 +662,41 @@ system.cpu1.num_busy_cycles              40793919.244318                       #
 system.cpu1.not_idle_fraction                0.022363                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.977637                       # Percentage of idle cycles
 system.cpu1.Branches                          5037975                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                12508      0.03%      0.03% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 26844895     66.65%     66.68% # Class of executed instruction
+system.cpu1.op_class::IntMult                   49628      0.12%     66.80% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc               737      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     66.80% # Class of executed instruction
+system.cpu1.op_class::MemRead                 7642991     18.98%     85.78% # Class of executed instruction
+system.cpu1.op_class::MemWrite                5728160     14.22%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                  40278919                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                   40450                       # number of quiesce instructions executed
 system.cpu1.icache.tags.replacements           433942                       # number of replacements
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 101d25ddf..04261a831 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.332812                       # Nu
 sim_ticks                                2332811899500                       # Number of ticks simulated
 final_tick                               2332811899500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1065837                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1370594                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            41157671581                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 420236                       # Number of bytes of host memory used
-host_seconds                                    56.68                       # Real time elapsed on the host
+host_inst_rate                                 975328                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1254205                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            37662621026                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 462792                       # Number of bytes of host memory used
+host_seconds                                    61.94                       # Real time elapsed on the host
 sim_insts                                    60411489                       # Number of instructions simulated
 sim_ops                                      77685090                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -182,6 +182,41 @@ system.cpu.num_busy_cycles               78801726.992856                       #
 system.cpu.not_idle_fraction                 0.016890                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.983110                       # Percentage of idle cycles
 system.cpu.Branches                          10299261                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                 28518      0.04%      0.04% # Class of executed instruction
+system.cpu.op_class::IntAlu                  50337551     64.69%     64.72% # Class of executed instruction
+system.cpu.op_class::IntMult                    87780      0.11%     64.84% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               2117      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::MemRead                 15640088     20.10%     84.94% # Class of executed instruction
+system.cpu.op_class::MemWrite                11722333     15.06%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   77818387                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    82795                       # number of quiesce instructions executed
 system.cpu.icache.tags.replacements            850590                       # number of replacements
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 789d25c60..8e4b444a3 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,170 +1,156 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.196225                       # Number of seconds simulated
-sim_ticks                                1196225147500                       # Number of ticks simulated
-final_tick                               1196225147500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.195945                       # Number of seconds simulated
+sim_ticks                                1195945260000                       # Number of ticks simulated
+final_tick                               1195945260000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 669591                       # Simulator instruction rate (inst/s)
-host_op_rate                                   853186                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            13029857543                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 426076                       # Number of bytes of host memory used
-host_seconds                                    91.81                       # Real time elapsed on the host
-sim_insts                                    61472758                       # Number of instructions simulated
-sim_ops                                      78327958                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 424891                       # Simulator instruction rate (inst/s)
+host_op_rate                                   541366                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8267957779                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 468940                       # Number of bytes of host memory used
+host_seconds                                   144.65                       # Real time elapsed on the host
+sim_insts                                    61459750                       # Number of instructions simulated
+sim_ops                                      78307634                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           40                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               57                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           57                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           378508                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4532924                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           393612                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4714684                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           337988                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4964984                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             62119428                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       378508                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       337988                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          716496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4092288                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           324676                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4804472                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             62142468                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       393612                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       324676                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          718288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4110592                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7119632                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7137936                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             12142                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             70901                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             12378                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73741                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5372                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             77606                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6654093                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           63942                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             75098                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6654453                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           64228                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               820778                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43390253                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               821064                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43400408                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker            54                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           161                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              316419                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             3789357                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           107                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              329122                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             3942224                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker           214                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              282545                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             4150543                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51929545                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         316419                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         282545                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             598964                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3421001                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data              14211                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            2516536                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                5951749                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3421001                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43390253                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            54                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              271481                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             4017301                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51960963                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         329122                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         271481                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             600603                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3437107                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              14215                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            2517125                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5968447                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3437107                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43400408                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          161                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             316419                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3803568                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          107                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             329122                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3956439                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker          214                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             282545                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            6667079                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               57881294                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       6654093                       # Number of read requests accepted
-system.physmem.writeReqs                       820778                       # Number of write requests accepted
-system.physmem.readBursts                     6654093                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     820778                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                425823936                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     38016                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7142848                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  62119428                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7119632                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      594                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  709146                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          11979                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              415258                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              415304                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              415298                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              415715                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              422332                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              415542                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              415821                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              415579                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              415943                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              415582                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             415396                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             414885                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             414891                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             415396                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             415532                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             415025                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6797                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6838                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6874                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7108                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7245                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7088                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7332                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7150                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7392                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7114                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7008                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6578                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6732                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6801                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7004                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6546                       # Per bank write bursts
+system.physmem.bw_total::cpu1.itb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             271481                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            6534426                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               57929411                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       6654453                       # Number of read requests accepted
+system.physmem.writeReqs                       821064                       # Number of write requests accepted
+system.physmem.readBursts                     6654453                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     821064                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                425841472                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     43520                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7149184                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  62142468                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7137936                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      680                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  709327                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          12098                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              415328                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              415212                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              415403                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              415611                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              422397                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              415577                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              415747                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              415496                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              416027                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              415632                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             415426                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             414842                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             414820                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             415557                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             415554                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             415144                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6840                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6732                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6969                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7025                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7326                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7107                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7317                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7078                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7464                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7155                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7023                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6543                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6616                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6901                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6977                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6633                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1196220625500                       # Total gap between requests
+system.physmem.totGap                    1195940759000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    6849                       # Read request sizes (log2)
 system.physmem.readPktSize::3                 6488064                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  159180                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  159540                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  63942                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    568386                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    406756                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    406740                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    413202                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    408903                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    410926                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   1188562                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   1189774                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   1562236                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     22558                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    14685                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    15166                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    13714                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    12546                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     9828                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     9386                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       12                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  64228                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    572493                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    410656                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    412880                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    461685                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    417933                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    446395                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   1149366                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   1113988                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   1438120                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     64577                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    50343                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    45843                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    44044                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     8771                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     8319                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     8183                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -194,45 +180,45 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2719                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5231                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1090                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1087                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1087                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1070                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3947                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4027                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6452                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6485                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6483                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6487                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6500                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6488                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6485                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
@@ -243,370 +229,393 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       427748                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      996.884371                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     962.233746                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     147.681447                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           5003      1.17%      1.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         3928      0.92%      2.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         2092      0.49%      2.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1312      0.31%      2.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1079      0.25%      3.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          787      0.18%      3.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          742      0.17%      3.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          447      0.10%      3.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       412358     96.40%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         427748                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5121                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      1299.254638                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    29808.283067                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535          5114     99.86%     99.86% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143            3      0.06%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.57286e+06-1.6384e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5121                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5121                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.793986                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.383938                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        9.006526                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2131     41.61%     41.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                296      5.78%     47.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                286      5.58%     52.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1314     25.66%     78.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 15      0.29%     78.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  5      0.10%     79.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  2      0.04%     79.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  2      0.04%     79.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.02%     79.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  3      0.06%     79.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.02%     79.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.02%     79.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                953     18.61%     97.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                 61      1.19%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                 17      0.33%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                 33      0.64%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5121                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   249828830750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              297299498250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  33267495000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 14203172500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       37548.49                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     2134.69                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples       473596                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      914.261641                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     784.047795                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     289.306705                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          25239      5.33%      5.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        21585      4.56%      9.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5945      1.26%     11.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2453      0.52%     11.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2290      0.48%     12.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1636      0.35%     12.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4075      0.86%     13.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          899      0.19%     13.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       409474     86.46%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         473596                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6482                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      1026.497532                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    34346.134147                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-131071         6476     99.91%     99.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::131072-262143            3      0.05%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-655359            1      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-917503            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.49037e+06-2.62144e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6482                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6482                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.233261                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.205432                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.970583                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2453     37.84%     37.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 80      1.23%     39.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3936     60.72%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 11      0.17%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6482                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   171035006500                       # Total ticks spent queuing
+system.physmem.totMemAccLat              295793250250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  33268865000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25704.97                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44683.18                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         355.97                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           5.97                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.93                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        5.95                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44454.97                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         356.07                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           5.98                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.96                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        5.97                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.83                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.78                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         4.56                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        29.44                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    6202256                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93908                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.22                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  84.12                       # Row buffer hit rate for writes
-system.physmem.avgGap                       160032.28                       # Average gap between requests
-system.physmem.pageHitRate                      93.07                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               6.14                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     59898120                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             7703395                       # Transaction distribution
-system.membus.trans_dist::ReadResp            7703395                       # Transaction distribution
-system.membus.trans_dist::WriteReq             767585                       # Transaction distribution
-system.membus.trans_dist::WriteResp            767585                       # Transaction distribution
-system.membus.trans_dist::Writeback             63942                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            31730                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          17317                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           11979                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137317                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           136921                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382690                       # Packet count per connected master and slave (bytes)
+system.physmem.avgRdQLen                         4.89                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        27.45                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    6199461                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     92422                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.17                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  82.71                       # Row buffer hit rate for writes
+system.physmem.avgGap                       159981.01                       # Average gap between requests
+system.physmem.pageHitRate                      93.00                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     947634468500                       # Time in different power states
+system.physmem.memoryStateTime::REF       39935220000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      208375212750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           40                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               57                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           57                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     59946686                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             7703403                       # Transaction distribution
+system.membus.trans_dist::ReadResp            7703403                       # Transaction distribution
+system.membus.trans_dist::WriteReq             767582                       # Transaction distribution
+system.membus.trans_dist::WriteResp            767582                       # Transaction distribution
+system.membus.trans_dist::Writeback             64228                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            31700                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          17261                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           12098                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137709                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137266                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382666                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10302                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10310                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          914                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1971094                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4365038                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          910                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1972180                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4366104                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12976128                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     12976128                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               17341166                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390070                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               17342232                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390035                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        20604                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        20620                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1828                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17334548                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     19747126                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1820                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17375892                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     19788443                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     51904512                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            71651638                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               71651638                       # Total data (bytes)
+system.membus.tot_pkt_size::total            71692955                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               71692955                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1224825500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1224801000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             9234000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             9242500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy              786000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy              784500                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy          9208108500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy          9211274000                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         5075173558                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         5078680829                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        16181474500                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        16046108250                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    69062                       # number of replacements
-system.l2c.tags.tagsinuse                52959.899517                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1674433                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   134270                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    12.470641                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    69421                       # number of replacements
+system.l2c.tags.tagsinuse                53012.823108                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1672128                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   134609                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    12.422111                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   40142.433744                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   40185.217534                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000410                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.003238                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3707.808501                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4231.213775                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.742447                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2816.465022                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2059.232379                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.612525                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001544                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3710.755623                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4242.358437                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.742287                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.001689                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2808.724549                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2063.021033                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.613178                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.056577                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.064563                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.056622                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.064733                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000042                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.042976                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.031421                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.808104                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.042858                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.031479                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.808911                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65203                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65183                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1924                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7908                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55276                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1920                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         8039                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55163                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994919                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 17240213                       # Number of tag accesses
-system.l2c.tags.data_accesses                17240213                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         2997                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         1656                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             349452                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             169925                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         6371                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1905                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             535287                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             180837                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1248430                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          572475                       # number of Writeback hits
-system.l2c.Writeback_hits::total               572475                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            1043                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             587                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1630                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           220                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            84                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               304                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            47236                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            62412                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               109648                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          2997                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          1656                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              349452                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              217161                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6371                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1905                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              535287                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              243249                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1358078                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         2997                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         1656                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             349452                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             217161                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6371                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1905                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             535287                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             243249                       # number of overall hits
-system.l2c.overall_hits::total                1358078                       # number of overall hits
+system.l2c.tags.occ_task_id_percent::1024     0.994614                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 17207703                       # Number of tag accesses
+system.l2c.tags.data_accesses                17207703                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         3810                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         1739                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             419090                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             205762                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         5504                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1909                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             464812                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             143326                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1245952                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          570869                       # number of Writeback hits
+system.l2c.Writeback_hits::total               570869                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1175                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             561                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1736                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           218                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           106                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               324                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            56320                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            52713                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               109033                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          3810                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          1739                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              419090                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              262082                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          5504                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          1909                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              464812                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              196039                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1354985                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         3810                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         1739                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             419090                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             262082                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         5504                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         1909                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             464812                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             196039                       # number of overall hits
+system.l2c.overall_hits::total                1354985                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             5500                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             7825                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             5736                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             7851                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             5275                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             3652                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22260                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          3753                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4772                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              8525                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          571                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          460                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1031                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          63889                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          75455                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             139344                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             5067                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             3613                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                22275                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          4950                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          3658                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              8608                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          565                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          478                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1043                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          67127                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          72586                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             139713                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              5500                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             71714                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              5736                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             74978                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              5275                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             79107                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                161604                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              5067                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             76199                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                161988                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             5500                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            71714                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             5736                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            74978                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             5275                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            79107                       # number of overall misses
-system.l2c.overall_misses::total               161604                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             5067                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            76199                       # number of overall misses
+system.l2c.overall_misses::total               161988                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        32000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker       224500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    385138750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    587705249                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    404696000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    578862249                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       334500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    381420250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    283658250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1638513499                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     11041523                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     13954898                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     24996421                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1841422                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2322900                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      4164322                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   4291032858                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   5578462720                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9869495578                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker        74500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    361943250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    276382250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1622474249                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     13480917                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     12005984                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     25486901                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1698427                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2508392                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      4206819                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   4495992931                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   5253472119                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   9749465050                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu0.dtb.walker        32000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       224500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    385138750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   4878738107                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    404696000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   5074855180                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.dtb.walker       334500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    381420250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   5862120970                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     11508009077                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker        74500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    361943250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   5529854369                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     11371939299                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu0.dtb.walker        32000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       224500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    385138750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   4878738107                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    404696000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   5074855180                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker       334500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    381420250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   5862120970                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    11508009077                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         2998                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         1659                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         354952                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         177750                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         6375                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1905                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         540562                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         184489                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1270690                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       572475                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           572475                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         4796                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5359                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           10155                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          791                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          544                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1335                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       111125                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       137867                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           248992                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         2998                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         1659                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          354952                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          288875                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         6375                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1905                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          540562                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          322356                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1519682                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         2998                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         1659                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         354952                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         288875                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         6375                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1905                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         540562                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         322356                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1519682                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000334                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001808                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.015495                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.044023                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000627                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.009758                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.019795                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.017518                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.782527                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.890465                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.839488                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.721871                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.845588                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.772285                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.574929                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.547303                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.559632                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000334                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.001808                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015495                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.248253                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000627                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.009758                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.245403                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.106341                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000334                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.001808                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015495                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.248253                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000627                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.009758                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.245403                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.106341                       # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    361943250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   5529854369                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    11371939299                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         3811                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         1741                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         424826                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         213613                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         5508                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1910                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         469879                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         146939                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1268227                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       570869                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           570869                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         6125                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4219                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           10344                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          783                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          584                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1367                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       123447                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       125299                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           248746                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         3811                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         1741                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          424826                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          337060                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         5508                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1910                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          469879                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          272238                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1516973                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         3811                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         1741                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         424826                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         337060                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         5508                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1910                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         469879                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         272238                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1516973                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001149                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.013502                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.036753                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000524                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.010784                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.024588                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.017564                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.808163                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.867030                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.832173                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.721584                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.818493                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.762985                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.543772                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.579302                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.561669                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.001149                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.013502                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.222447                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.000524                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.010784                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.279898                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.106784                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.001149                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.013502                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.222447                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.000524                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.010784                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.279898                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.106784                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        32000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74833.333333                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70025.227273                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 75106.102109                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70553.695955                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 73731.021399                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        83625                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72307.156398                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77672.029025                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 73607.973899                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2942.052491                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2924.329003                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2932.131496                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3224.907180                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5049.782609                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  4039.109602                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67163.875753                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73930.988271                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 70828.278060                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71431.468324                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76496.609466                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 72838.350123                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2723.417576                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3282.117004                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2960.838871                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3006.065487                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5247.682008                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4033.383509                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66977.414915                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72375.831689                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 69782.089355                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74833.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 70025.227273                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 68030.483685                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 70553.695955                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 67684.589880                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        83625                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72307.156398                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 74103.694616                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 71211.164804                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 71431.468324                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 72571.219688                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 70202.356341                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74833.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 70025.227273                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 68030.483685                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 70553.695955                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 67684.589880                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        83625                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72307.156398                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 74103.694616                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 71211.164804                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 71431.468324                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 72571.219688                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 70202.356341                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -615,8 +624,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               63942                       # number of writebacks
-system.l2c.writebacks::total                    63942                       # number of writebacks
+system.l2c.writebacks::writebacks               64228                       # number of writebacks
+system.l2c.writebacks::total                    64228                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
@@ -624,150 +633,162 @@ system.l2c.demand_mshr_hits::total                  1                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         5499                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         7825                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         5735                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         7851                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         5275                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         3652                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           22259                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         3753                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4772                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         8525                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          571                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          460                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1031                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        63889                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        75455                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        139344                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         5067                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         3613                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           22274                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         4950                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         3658                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         8608                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          565                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          478                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1043                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        67127                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        72586                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        139713                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         5499                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        71714                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         5735                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        74978                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         5275                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        79107                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           161603                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         5067                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        76199                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           161987                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         5499                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        71714                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         5735                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        74978                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         5275                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        79107                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          161603                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         5067                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        76199                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          161987                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       187500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    315394500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    490118749                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    331983250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    480926749                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       284500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    314655750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    238278250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1358939249                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     37548751                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     47763765                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     85312516                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      5717068                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4604958                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     10322026                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3469064140                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4618288780                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8087352920                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    297779250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    231458250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1342639499                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     49534942                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     36634151                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     86169093                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      5652063                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4782976                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     10435039                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3631997561                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4330425379                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   7962422940                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       187500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    315394500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   3959182889                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    331983250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4112924310                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       284500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    314655750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   4856567030                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   9446292169                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    297779250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   4561883629                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   9305062439                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       187500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    315394500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   3959182889                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    331983250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4112924310                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       284500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    314655750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   4856567030                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   9446292169                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    352326000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  11221595994                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5508250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155529668246                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167109098490                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1041121994                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  15728911223                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  16770033217                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    352326000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  12262717988                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5508250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171258579469                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 183879131707                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000334                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001808                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015492                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.044023                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000627                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009758                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.019795                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.017517                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.782527                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.890465                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.839488                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.721871                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.845588                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.772285                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.574929                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.547303                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.559632                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000334                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001808                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015492                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.248253                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000627                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009758                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.245403                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.106340                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000334                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001808                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015492                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.248253                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000627                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009758                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.245403                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.106340                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    297779250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   4561883629                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   9305062439                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    350574750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12456402492                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5624750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154292832747                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167105434739                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1046881494                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  15722205337                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  16769086831                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    350574750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13503283986                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5624750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170015038084                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183874521570                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000262                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001149                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013500                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036753                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000726                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000524                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010784                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024588                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.017563                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.808163                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.867030                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.832173                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.721584                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.818493                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.762985                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.543772                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.579302                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.561669                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000262                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001149                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013500                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.222447                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000726                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000524                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010784                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.279898                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.106783                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000262                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001149                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013500                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.222447                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000726                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000524                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010784                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.279898                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.106783                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57354.882706                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62634.983898                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57887.227550                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61256.750605                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59650.379147                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65245.961117                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 61051.226425                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.996270                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.171207                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10007.333255                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.378284                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.778261                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.664403                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54298.300803                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61205.868133                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 58038.759616                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58768.354056                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64062.621091                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 60278.328949                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10007.058990                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.803445                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10010.350023                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.651327                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.225941                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10004.831256                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54106.359006                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59659.237029                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56991.281699                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57354.882706                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55207.949480                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57887.227550                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54855.081624                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59650.379147                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61392.380320                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 58453.693118                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58768.354056                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59868.024895                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57443.266676                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57354.882706                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55207.949480                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57887.227550                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54855.081624                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59650.379147                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61392.380320                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 58453.693118                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58768.354056                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59868.024895                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57443.266676                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -788,67 +809,67 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                   119642613                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2536412                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2536412                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            767585                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           767585                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           572475                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           30937                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         17621                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          48558                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           260776                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          260776                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       723469                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1059051                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         4339                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side         7907                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1082141                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4772543                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7929                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        20256                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7677635                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     22743520                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35146882                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6636                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        11992                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     34596404                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     46050592                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7620                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        25500                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          138589146                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             138589146                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         4530356                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4766758175                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   119513329                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2535217                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2535217                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            767582                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           767582                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           570869                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           30989                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         17585                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          48574                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           260651                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          260651                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       863496                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1226215                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6137                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        12691                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       940498                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4601530                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         6236                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        15421                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7672224                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27215456                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     41348685                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6964                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        15244                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     30072692                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     39622266                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7640                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        22032                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          138310979                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             138310979                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4620420                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4758868690                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1607753214                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1517597206                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1923485226                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        1752589322                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           2680000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           4396000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy           4909499                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy           8880000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy        2437223968                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy        2117887474                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy        3163938724                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy           6024000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy        2927028338                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer8.occupancy           4326000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy          13881500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer9.occupancy           9913999                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      45388263                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq              7671442                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             7671442                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                7967                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               7967                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30566                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8070                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                      45398856                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq              7671434                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             7671434                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                7963                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               7963                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30550                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8060                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          742                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          494                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          496                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -865,17 +886,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382690                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2382666                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12976128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     12976128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                15358818                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40335                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16140                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                15358794                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40319                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1484                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          271                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          272                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -892,14 +913,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390070                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390035                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     51904512                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total             54294582                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                54294582                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             21430000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total             54294547                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                54294547                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy             21418000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4041000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              4036000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -909,7 +930,7 @@ system.iobus.reqLayer4.occupancy                27000                       # La
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy               297000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy               298000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
@@ -945,9 +966,9 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy          6488064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374723000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374703000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         16195242500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         16368811750                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -972,25 +993,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     5879584                       # DTB read hits
-system.cpu0.dtb.read_misses                      2138                       # DTB read misses
-system.cpu0.dtb.write_hits                    4838515                       # DTB write hits
-system.cpu0.dtb.write_misses                      406                       # DTB write misses
+system.cpu0.dtb.read_hits                     7064335                       # DTB read hits
+system.cpu0.dtb.read_misses                      3758                       # DTB read misses
+system.cpu0.dtb.write_hits                    5649339                       # DTB write hits
+system.cpu0.dtb.write_misses                      802                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1387                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    1711                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                    88                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   143                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      203                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 5881722                       # DTB read accesses
-system.cpu0.dtb.write_accesses                4838921                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 7068093                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5650141                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         10718099                       # DTB hits
-system.cpu0.dtb.misses                           2544                       # DTB misses
-system.cpu0.dtb.accesses                     10720643                       # DTB accesses
+system.cpu0.dtb.hits                         12713674                       # DTB hits
+system.cpu0.dtb.misses                           4560                       # DTB misses
+system.cpu0.dtb.accesses                     12718234                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1012,8 +1033,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    24773464                       # ITB inst hits
-system.cpu0.itb.inst_misses                      1350                       # ITB inst misses
+system.cpu0.itb.inst_hits                    29562995                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -1022,94 +1043,130 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                     963                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1181                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                24774814                       # ITB inst accesses
-system.cpu0.itb.hits                         24773464                       # DTB hits
-system.cpu0.itb.misses                           1350                       # DTB misses
-system.cpu0.itb.accesses                     24774814                       # DTB accesses
-system.cpu0.numCycles                      2391604989                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                29565200                       # ITB inst accesses
+system.cpu0.itb.hits                         29562995                       # DTB hits
+system.cpu0.itb.misses                           2205                       # DTB misses
+system.cpu0.itb.accesses                     29565200                       # DTB accesses
+system.cpu0.numCycles                      2391890520                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   24375312                       # Number of instructions committed
-system.cpu0.committedOps                     31460856                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             28085533                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4364                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1070699                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      3751745                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    28085533                       # number of integer instructions
-system.cpu0.num_fp_insts                         4364                       # number of float instructions
-system.cpu0.num_int_register_reads          162520351                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          30535592                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3980                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                384                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     11309766                       # number of memory refs
-system.cpu0.num_load_insts                    6158982                       # Number of load instructions
-system.cpu0.num_store_insts                   5150784                       # Number of store instructions
-system.cpu0.num_idle_cycles              2265857607.135565                       # Number of idle cycles
-system.cpu0.num_busy_cycles              125747381.864435                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.052579                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.947421                       # Percentage of idle cycles
-system.cpu0.Branches                          4778581                       # Number of branches fetched
+system.cpu0.committedInsts                   28864889                       # Number of instructions committed
+system.cpu0.committedOps                     37190899                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             33115613                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1241798                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4372441                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    33115613                       # number of integer instructions
+system.cpu0.num_fp_insts                         3860                       # number of float instructions
+system.cpu0.num_int_register_reads          192173380                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          36248506                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     13380838                       # number of memory refs
+system.cpu0.num_load_insts                    7401595                       # Number of load instructions
+system.cpu0.num_store_insts                   5979243                       # Number of store instructions
+system.cpu0.num_idle_cycles              2246179687.500122                       # Number of idle cycles
+system.cpu0.num_busy_cycles              145710832.499878                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.060919                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.939081                       # Percentage of idle cycles
+system.cpu0.Branches                          5600259                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                14567      0.04%      0.04% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 24478507     64.56%     64.59% # Class of executed instruction
+system.cpu0.op_class::IntMult                   43773      0.12%     64.71% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc               694      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.71% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7401595     19.52%     84.23% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5979243     15.77%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                  37918379                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   39137                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           354708                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.352361                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           24418226                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           355220                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            68.741135                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      76254991000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.352361                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994829                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.994829                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   46956                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements           424861                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.353809                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           29137604                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           425373                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            68.498950                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      76246574000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.353809                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994832                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.994832                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          464                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           47                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         25128668                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        25128668                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     24418226                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       24418226                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     24418226                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        24418226                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     24418226                       # number of overall hits
-system.cpu0.icache.overall_hits::total       24418226                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       355221                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       355221                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       355221                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        355221                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       355221                       # number of overall misses
-system.cpu0.icache.overall_misses::total       355221                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   4963623214                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   4963623214                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   4963623214                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   4963623214                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   4963623214                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   4963623214                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     24773447                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     24773447                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     24773447                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     24773447                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     24773447                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     24773447                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014339                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014339                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014339                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014339                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014339                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014339                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13973.338327                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13973.338327                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13973.338327                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13973.338327                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13973.338327                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13973.338327                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         29988352                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        29988352                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29137604                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       29137604                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29137604                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        29137604                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29137604                       # number of overall hits
+system.cpu0.icache.overall_hits::total       29137604                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       425374                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       425374                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       425374                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        425374                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       425374                       # number of overall misses
+system.cpu0.icache.overall_misses::total       425374                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5893447476                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   5893447476                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   5893447476                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   5893447476                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   5893447476                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   5893447476                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     29562978                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     29562978                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     29562978                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     29562978                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     29562978                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     29562978                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014389                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014389                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014389                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014389                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014389                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014389                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13854.743064                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13854.743064                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13854.743064                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13854.743064                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13854.743064                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13854.743064                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1118,126 +1175,128 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       355221                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       355221                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       355221                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       355221                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       355221                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       355221                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4251043786                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   4251043786                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4251043786                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   4251043786                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4251043786                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   4251043786                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    443885000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    443885000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    443885000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    443885000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014339                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014339                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014339                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014339                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014339                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014339                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.321149                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11967.321149                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.321149                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11967.321149                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.321149                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11967.321149                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       425374                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       425374                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       425374                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       425374                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       425374                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       425374                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5040497524                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5040497524                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5040497524                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5040497524                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5040497524                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5040497524                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    442131250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    442131250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    442131250                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    442131250                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014389                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014389                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014389                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014389                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014389                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014389                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11849.566556                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11849.566556                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11849.566556                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11849.566556                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11849.566556                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11849.566556                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           278858                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          453.142717                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10319958                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           279247                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            36.956379                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        673996250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   453.142717                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.885044                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.885044                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          389                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          379                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.759766                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         42855830                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        42855830                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5473702                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5473702                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4567964                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4567964                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       129389                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       129389                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       130155                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       130155                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10041666                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10041666                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10041666                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10041666                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       191503                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       191503                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       126416                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       126416                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8708                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         8708                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7742                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7742                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       317919                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        317919                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       317919                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       317919                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2845005745                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   2845005745                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5278408391                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   5278408391                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     82648500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     82648500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     45599070                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     45599070                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8123414136                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total   8123414136                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8123414136                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total   8123414136                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5665205                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      5665205                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4694380                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4694380                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       138097                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       138097                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       137897                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       137897                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     10359585                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     10359585                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     10359585                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     10359585                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033803                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.033803                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.026929                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.026929                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.063057                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.063057                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056143                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056143                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.030688                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.030688                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.030688                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.030688                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.194133                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.194133                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41754.274704                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 41754.274704                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9491.100138                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9491.100138                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5889.830793                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5889.830793                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25551.835958                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 25551.835958                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25551.835958                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 25551.835958                       # average overall miss latency
+system.cpu0.dcache.tags.replacements           329701                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          455.940244                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           12258862                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           330213                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            37.124105                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        671876250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   455.940244                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.890508                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.890508                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         50852546                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        50852546                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6594319                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6594319                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5344510                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5344510                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       148000                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       148000                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149609                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       149609                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11938829                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11938829                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11938829                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11938829                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       227548                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       227548                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       141421                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       141421                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9358                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9358                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7517                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7517                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       368969                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        368969                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       368969                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       368969                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3297192496                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   3297192496                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5650617511                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   5650617511                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92814250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     92814250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44512065                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     44512065                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8947810007                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   8947810007                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8947810007                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   8947810007                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6821867                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6821867                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5485931                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5485931                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157358                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       157358                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157126                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       157126                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12307798                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12307798                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12307798                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12307798                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033356                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.033356                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025779                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.025779                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059469                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059469                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047841                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047841                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029978                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.029978                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029978                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029978                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.096577                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.096577                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39956.000247                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 39956.000247                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9918.171618                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9918.171618                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5921.519888                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5921.519888                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24250.844941                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 24250.844941                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24250.844941                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 24250.844941                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1246,62 +1305,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       257140                       # number of writebacks
-system.cpu0.dcache.writebacks::total           257140                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       191503                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       191503                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       126416                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       126416                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8708                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8708                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7738                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7738                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       317919                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       317919                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       317919                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       317919                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2460118255                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2460118255                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4997663609                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4997663609                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     65185500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     65185500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     30121930                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     30121930                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7457781864                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   7457781864                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7457781864                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   7457781864                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  12214482000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  12214482000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1164635000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1164635000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  13379117000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  13379117000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033803                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033803                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.026929                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.026929                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.063057                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.063057                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056114                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056114                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.030688                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.030688                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.030688                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.030688                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12846.369274                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12846.369274                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39533.473682                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39533.473682                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7485.702802                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7485.702802                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3892.728095                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3892.728095                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23458.119408                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23458.119408                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23458.119408                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23458.119408                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       305583                       # number of writebacks
+system.cpu0.dcache.writebacks::total           305583                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       227548                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       227548                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141421                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       141421                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9358                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9358                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7515                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7515                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       368969                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       368969                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       368969                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       368969                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2840145504                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2840145504                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5338354489                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5338354489                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     74046750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     74046750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29480935                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29480935                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8178499993                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   8178499993                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8178499993                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   8178499993                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13564071000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13564071000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1170919500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1170919500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14734990500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14734990500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033356                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033356                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025779                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025779                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059469                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059469                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047828                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047828                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029978                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.029978                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029978                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.029978                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12481.522597                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12481.522597                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37747.961682                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37747.961682                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7912.668305                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7912.668305                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3922.945442                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3922.945442                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22165.818790                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22165.818790                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22165.818790                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22165.818790                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1332,25 +1391,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     9507781                       # DTB read hits
-system.cpu1.dtb.read_misses                      5255                       # DTB read misses
-system.cpu1.dtb.write_hits                    6647969                       # DTB write hits
-system.cpu1.dtb.write_misses                     1834                       # DTB write misses
+system.cpu1.dtb.read_hits                     8317790                       # DTB read hits
+system.cpu1.dtb.read_misses                      3645                       # DTB read misses
+system.cpu1.dtb.write_hits                    5833574                       # DTB write hits
+system.cpu1.dtb.write_misses                     1433                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2187                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1863                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   188                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   144                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      249                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 9513036                       # DTB read accesses
-system.cpu1.dtb.write_accesses                6649803                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 8321435                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5835007                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         16155750                       # DTB hits
-system.cpu1.dtb.misses                           7089                       # DTB misses
-system.cpu1.dtb.accesses                     16162839                       # DTB accesses
+system.cpu1.dtb.hits                         14151364                       # DTB hits
+system.cpu1.dtb.misses                           5078                       # DTB misses
+system.cpu1.dtb.accesses                     14156442                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1372,8 +1431,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    38008437                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3017                       # ITB inst misses
+system.cpu1.itb.inst_hits                    33205963                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1382,95 +1441,129 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1485                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1276                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                38011454                       # ITB inst accesses
-system.cpu1.itb.hits                         38008437                       # DTB hits
-system.cpu1.itb.misses                           3017                       # DTB misses
-system.cpu1.itb.accesses                     38011454                       # DTB accesses
-system.cpu1.numCycles                      2392450295                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                33208134                       # ITB inst accesses
+system.cpu1.itb.hits                         33205963                       # DTB hits
+system.cpu1.itb.misses                           2171                       # DTB misses
+system.cpu1.itb.accesses                     33208134                       # DTB accesses
+system.cpu1.numCycles                      2390414629                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   37097446                       # Number of instructions committed
-system.cpu1.committedOps                     46867102                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             42687988                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5457                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1134316                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      4357000                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    42687988                       # number of integer instructions
-system.cpu1.num_fp_insts                         5457                       # number of float instructions
-system.cpu1.num_int_register_reads          248074220                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          45509439                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3577                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1884                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     16770062                       # number of memory refs
-system.cpu1.num_load_insts                    9887948                       # Number of load instructions
-system.cpu1.num_store_insts                   6882114                       # Number of store instructions
-system.cpu1.num_idle_cycles              1855714829.552449                       # Number of idle cycles
-system.cpu1.num_busy_cycles              536735465.447551                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.224346                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.775654                       # Percentage of idle cycles
-system.cpu1.Branches                          5771094                       # Number of branches fetched
+system.cpu1.committedInsts                   32594861                       # Number of instructions committed
+system.cpu1.committedOps                     41116735                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             37639270                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
+system.cpu1.num_func_calls                     962738                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3734786                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    37639270                       # number of integer instructions
+system.cpu1.num_fp_insts                         6793                       # number of float instructions
+system.cpu1.num_int_register_reads          218315433                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          39777331                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                     14690124                       # number of memory refs
+system.cpu1.num_load_insts                    8639728                       # Number of load instructions
+system.cpu1.num_store_insts                   6050396                       # Number of store instructions
+system.cpu1.num_idle_cycles              1874297798.309079                       # Number of idle cycles
+system.cpu1.num_busy_cycles              516116830.690921                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.215911                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.784089                       # Percentage of idle cycles
+system.cpu1.Branches                          4947313                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                14267      0.03%      0.03% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 26968126     64.63%     64.67% # Class of executed instruction
+system.cpu1.op_class::IntMult                   50231      0.12%     64.79% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              1470      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::MemRead                 8639728     20.71%     85.50% # Class of executed instruction
+system.cpu1.op_class::MemWrite                6050396     14.50%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                  41724218                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   52097                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements           540849                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          478.554171                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           37467072                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           541361                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            69.209034                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      94011084500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   478.554171                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.934676                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.934676                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                   44363                       # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements           469889                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          478.549875                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           32735558                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           470401                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            69.590749                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      93998064500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   478.549875                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.934668                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.934668                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          244                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          203                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          448                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         38549794                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        38549794                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     37467072                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       37467072                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     37467072                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        37467072                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     37467072                       # number of overall hits
-system.cpu1.icache.overall_hits::total       37467072                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       541361                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       541361                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       541361                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        541361                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       541361                       # number of overall misses
-system.cpu1.icache.overall_misses::total       541361                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7383473218                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   7383473218                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   7383473218                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   7383473218                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   7383473218                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   7383473218                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     38008433                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     38008433                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     38008433                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     38008433                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     38008433                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     38008433                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014243                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.014243                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014243                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.014243                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014243                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.014243                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13638.723916                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13638.723916                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13638.723916                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13638.723916                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13638.723916                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13638.723916                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         33676360                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        33676360                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     32735558                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       32735558                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     32735558                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        32735558                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     32735558                       # number of overall hits
+system.cpu1.icache.overall_hits::total       32735558                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       470401                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       470401                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       470401                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        470401                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       470401                       # number of overall misses
+system.cpu1.icache.overall_misses::total       470401                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6443025224                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6443025224                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6443025224                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6443025224                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6443025224                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6443025224                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     33205959                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     33205959                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     33205959                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     33205959                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     33205959                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     33205959                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014166                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014166                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014166                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014166                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014166                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014166                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13696.878246                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13696.878246                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13696.878246                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13696.878246                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13696.878246                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13696.878246                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1479,127 +1572,126 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       541361                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       541361                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       541361                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       541361                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       541361                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       541361                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6298814782                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   6298814782                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6298814782                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   6298814782                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6298814782                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   6298814782                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6977250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6977250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6977250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      6977250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014243                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014243                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014243                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.014243                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014243                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.014243                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11635.146939                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11635.146939                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11635.146939                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11635.146939                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11635.146939                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11635.146939                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       470401                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       470401                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       470401                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       470401                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       470401                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       470401                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5500320776                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5500320776                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5500320776                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5500320776                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5500320776                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5500320776                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7094750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      7094750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      7094750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      7094750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014166                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014166                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014166                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.014166                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014166                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.014166                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11692.833935                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11692.833935                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11692.833935                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11692.833935                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11692.833935                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11692.833935                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           343803                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          472.607785                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           13921652                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           344315                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            40.432894                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      85311468250                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.607785                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.923062                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.923062                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         57519242                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        57519242                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      8078143                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        8078143                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      5612875                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       5612875                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       100617                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total       100617                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data       102310                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total       102310                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     13691018                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        13691018                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     13691018                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       13691018                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       207066                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       207066                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       165297                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       165297                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11987                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11987                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         9884                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         9884                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       372363                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        372363                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       372363                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       372363                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2696827750                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2696827750                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6860807042                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   6860807042                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    107474000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    107474000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     50841959                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     50841959                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   9557634792                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   9557634792                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   9557634792                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   9557634792                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      8285209                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      8285209                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      5778172                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      5778172                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       112604                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       112604                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       112194                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       112194                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     14063381                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     14063381                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     14063381                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     14063381                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.024992                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.024992                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028607                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.028607                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.106453                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.106453                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.088097                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.088097                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026477                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.026477                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026477                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.026477                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13024.000802                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13024.000802                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41505.938051                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 41505.938051                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8965.879703                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8965.879703                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5143.864731                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5143.864731                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25667.520113                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 25667.520113                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25667.520113                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 25667.520113                       # average overall miss latency
+system.cpu1.dcache.tags.replacements           292396                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          471.340913                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           11973732                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           292744                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            40.901716                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      85301409250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.340913                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.920588                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.920588                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          333                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           15                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.679688                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         49486795                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        49486795                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      6952689                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        6952689                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4832965                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4832965                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        82012                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        82012                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82761                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        82761                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     11785654                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        11785654                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     11785654                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       11785654                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       170655                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       170655                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       150219                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       150219                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11301                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11301                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10073                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10073                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       320874                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        320874                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       320874                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       320874                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2212742497                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2212742497                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6365695527                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   6365695527                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     97206750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     97206750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     52182477                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     52182477                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   8578438024                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   8578438024                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   8578438024                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   8578438024                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      7123344                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      7123344                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4983184                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4983184                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        93313                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        93313                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92834                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        92834                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     12106528                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     12106528                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     12106528                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     12106528                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023957                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.023957                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030145                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030145                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.121109                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.121109                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108506                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108506                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026504                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.026504                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026504                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.026504                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12966.174428                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12966.174428                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42376.101072                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 42376.101072                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8601.606053                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8601.606053                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5180.430557                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5180.430557                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26734.599949                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 26734.599949                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26734.599949                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 26734.599949                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1608,62 +1700,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       315335                       # number of writebacks
-system.cpu1.dcache.writebacks::total           315335                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       207066                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       207066                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       165297                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       165297                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11987                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11987                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         9883                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         9883                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       372363                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       372363                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       372363                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       372363                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2282040250                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2282040250                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6506824958                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6506824958                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     83489000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     83489000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31075041                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31075041                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8788865208                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   8788865208                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8788865208                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   8788865208                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169960243250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169960243250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25194386277                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25194386277                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195154629527                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195154629527                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.024992                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.024992                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028607                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028607                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.106453                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.106453                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.088088                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.088088                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026477                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026477                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026477                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026477                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11020.835144                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11020.835144                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39364.446772                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39364.446772                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6964.962042                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6964.962042                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3144.292320                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3144.292320                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23602.949831                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23602.949831                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23602.949831                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23602.949831                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       265286                       # number of writebacks
+system.cpu1.dcache.writebacks::total           265286                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170655                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       170655                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150219                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       150219                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11301                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11301                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10070                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10070                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       320874                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       320874                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       320874                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       320874                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1870737503                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1870737503                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6042583473                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6042583473                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     74594250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     74594250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32041523                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32041523                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7913320976                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   7913320976                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7913320976                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   7913320976                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608523750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608523750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25187494163                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25187494163                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193796017913                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193796017913                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023957                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023957                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030145                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030145                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.121109                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.121109                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108473                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108473                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026504                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026504                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026504                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026504                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10962.101919                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10962.101919                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40225.161085                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40225.161085                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6600.676931                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6600.676931                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3181.879146                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3181.879146                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24661.770589                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24661.770589                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24661.770589                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24661.770589                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1687,10 +1779,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 746722879500                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 746722879500                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 746722879500                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 746722879500                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745373562750                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 745373562750                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745373562750                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 745373562750                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 823848f29..41f066b07 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,134 +1,146 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.616536                       # Number of seconds simulated
-sim_ticks                                2616536215000                       # Number of ticks simulated
-final_tick                               2616536215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.616230                       # Number of seconds simulated
+sim_ticks                                2616229847000                       # Number of ticks simulated
+final_tick                               2616229847000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 594955                       # Simulator instruction rate (inst/s)
-host_op_rate                                   757104                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25859148121                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 420956                       # Number of bytes of host memory used
-host_seconds                                   101.18                       # Real time elapsed on the host
-sim_insts                                    60200059                       # Number of instructions simulated
-sim_ops                                      76606878                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 375445                       # Simulator instruction rate (inst/s)
+host_op_rate                                   477768                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            16316419265                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 464828                       # Number of bytes of host memory used
+host_seconds                                   160.34                       # Real time elapsed on the host
+sim_insts                                    60200042                       # Number of instructions simulated
+sim_ops                                      76606857                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            703944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9089816                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132477600                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       703944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          703944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3706240                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            703560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9089944                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            132477344                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       703560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          703560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3706304                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6722312                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6722376                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17211                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142064                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15494706                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57910                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17205                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142066                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15494702                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57911                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811928                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46887710                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               811929                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        46893201                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.dtb.walker            122                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               269037                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3473988                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50630906                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          269037                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             269037                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1416468                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1152696                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2569165                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1416468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46887710                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               268921                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3474444                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50636737                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          268921                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             268921                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1416658                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1152831                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2569490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1416658                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       46893201                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           122                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              269037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4626685                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53200071                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15494706                       # Number of read requests accepted
-system.physmem.writeReqs                       811928                       # Number of write requests accepted
-system.physmem.readBursts                    15494706                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     811928                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                991531648                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    129536                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6740736                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 132477600                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6722312                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2024                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706583                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4515                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              967775                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              268921                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4627275                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53206227                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15494702                       # Number of read requests accepted
+system.physmem.writeReqs                       811929                       # Number of write requests accepted
+system.physmem.readBursts                    15494702                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     811929                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                991533248                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    127680                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6729728                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 132477344                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6722376                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1995                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706751                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4516                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              967982                       # Per bank write bursts
 system.physmem.perBankRdBursts::1              967715                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              967672                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              967748                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              974561                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              968173                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              967769                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              967703                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              968545                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              967669                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              967754                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              974564                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              968184                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              967779                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              967692                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              968544                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              968137                       # Per bank write bursts
 system.physmem.perBankRdBursts::10             967949                       # Per bank write bursts
 system.physmem.perBankRdBursts::11             967746                       # Per bank write bursts
 system.physmem.perBankRdBursts::12             967851                       # Per bank write bursts
 system.physmem.perBankRdBursts::13             967741                       # Per bank write bursts
 system.physmem.perBankRdBursts::14             967800                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             967797                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6510                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6313                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6323                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6241                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6804                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6995                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6800                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6791                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7084                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6747                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6568                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6457                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6495                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6295                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6428                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6473                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             967600                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6503                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6305                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6309                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6231                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6800                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6982                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6786                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6777                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6733                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6548                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6441                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6486                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6281                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6425                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6465                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2616531854000                       # Total gap between requests
+system.physmem.totGap                    2616225486000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    6664                       # Read request sizes (log2)
 system.physmem.readPktSize::3                15335424                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  152618                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  152614                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  57910                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1116573                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    960474                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    961347                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    975907                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    963056                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    965451                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2812276                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2805674                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3709925                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     42008                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    34639                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    36264                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    33338                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    31474                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    22310                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    21858                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      108                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  57911                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1126567                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    970563                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    976518                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1090618                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    986596                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1051326                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2724005                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2632042                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3421723                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    136210                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   113171                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   104737                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                   101252                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19730                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18895                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18668                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       86                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -159,45 +171,45 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2541                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4792                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4793                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4839                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5804                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4869                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4793                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1078                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1070                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3835                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6081                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6096                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6096                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6094                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6094                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
@@ -208,140 +220,122 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       977394                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     1014.625651                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1002.644045                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev      87.222028                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           3543      0.36%      0.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         3286      0.34%      0.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1787      0.18%      0.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1165      0.12%      1.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          902      0.09%      1.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          711      0.07%      1.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          580      0.06%      1.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          432      0.04%      1.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       964988     98.73%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         977394                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4784                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      3238.435619                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    134294.504205                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         4779     99.90%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06            3      0.06%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8.9129e+06-9.43718e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4784                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4784                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.015886                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.524536                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        9.242033                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2224     46.49%     46.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 36      0.75%     47.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                227      4.74%     51.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1224     25.59%     77.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  8      0.17%     77.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  4      0.08%     77.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.02%     77.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  1      0.02%     77.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.02%     77.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                945     19.75%     97.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                 67      1.40%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                 15      0.31%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                 31      0.65%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4784                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   588095657500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              694960871250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  77463410000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 29401803750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       37959.58                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1897.79                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples      1027354                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      971.683544                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     905.447521                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     204.224200                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22943      2.23%      2.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22460      2.19%      4.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8461      0.82%      5.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2563      0.25%      5.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2504      0.24%      5.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1783      0.17%      5.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8706      0.85%      6.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          969      0.09%      6.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       956965     93.15%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1027354                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6094                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2542.286675                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    118884.715097                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         6090     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6094                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6094                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.255005                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.227328                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.967528                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2261     37.10%     37.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 29      0.48%     37.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3794     62.26%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  9      0.15%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6094                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   400062590250                       # Total ticks spent queuing
+system.physmem.totMemAccLat              690550846500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  77463535000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25822.64                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44857.36                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         378.95                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.58                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       50.63                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44572.64                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         378.99                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.57                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       50.64                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.57                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.98                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.96                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         7.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        29.46                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14490606                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     90101                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.53                       # Row buffer hit rate for writes
-system.physmem.avgGap                       160458.12                       # Average gap between requests
-system.physmem.pageHitRate                      93.48                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               3.85                       # Percentage of time for which DRAM has all the banks in precharge state
-system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54116651                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16546597                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16546597                       # Transaction distribution
+system.physmem.avgRdQLen                         6.59                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.10                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14482119                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     88386                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  84.03                       # Row buffer hit rate for writes
+system.physmem.avgGap                       160439.36                       # Average gap between requests
+system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2245273695250                       # Time in different power states
+system.physmem.memoryStateTime::REF       87361560000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      283591722250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     54122917                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16546592                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16546592                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763385                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763385                       # Transaction distribution
-system.membus.trans_dist::Writeback             57910                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4515                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4515                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            132217                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           132217                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383088                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::Writeback             57911                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4516                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4516                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            132219                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           132219                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383090                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3850                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893540                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280490                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893535                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280487                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30670848                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30670848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34951338                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390542                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               34951335                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390546                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7700                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16516520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     18914786                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16516328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     18914598                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    122683392                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           141598178                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              141598178                       # Total data (bytes)
+system.membus.tot_pkt_size::total           141597990                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              141597990                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1206225000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1206224000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3615000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3616500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17911294000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17911182500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4951349139                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4951111812                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        38238689000                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        37928474750                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      47801339                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16518785                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16518785                       # Transaction distribution
+system.iobus.throughput                      47806938                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16518786                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16518786                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8183                       # Transaction distribution
 system.iobus.trans_dist::WriteResp               8183                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7946                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          534                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1042                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
@@ -363,12 +357,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2383088                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2383090                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30670848                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     30670848                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                33053936                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                33053938                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15892                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1068                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2084                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
@@ -390,14 +384,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390542                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390546                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    122683392                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            125073934                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               125073934                       # Total data (bytes)
+system.iobus.tot_pkt_size::total            125073938                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               125073938                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3977000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              3978000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy               534000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -443,9 +437,9 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         15335424000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374905000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374907000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         38265059000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         38686102250                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -471,25 +465,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14996179                       # DTB read hits
-system.cpu.dtb.read_misses                       7337                       # DTB read misses
-system.cpu.dtb.write_hits                    11230334                       # DTB write hits
-system.cpu.dtb.write_misses                      2213                       # DTB write misses
+system.cpu.dtb.read_hits                     14996190                       # DTB read hits
+system.cpu.dtb.read_misses                       7339                       # DTB read misses
+system.cpu.dtb.write_hits                    11230344                       # DTB write hits
+system.cpu.dtb.write_misses                      2214                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3411                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     3405                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    194                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                    192                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 15003516                       # DTB read accesses
-system.cpu.dtb.write_accesses                11232547                       # DTB write accesses
+system.cpu.dtb.read_accesses                 15003529                       # DTB read accesses
+system.cpu.dtb.write_accesses                11232558                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26226513                       # DTB hits
-system.cpu.dtb.misses                            9550                       # DTB misses
-system.cpu.dtb.accesses                      26236063                       # DTB accesses
+system.cpu.dtb.hits                          26226534                       # DTB hits
+system.cpu.dtb.misses                            9553                       # DTB misses
+system.cpu.dtb.accesses                      26236087                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -511,7 +505,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     61493932                       # ITB inst hits
+system.cpu.itb.inst_hits                     61493913                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -528,88 +522,123 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61498403                       # ITB inst accesses
-system.cpu.itb.hits                          61493932                       # DTB hits
+system.cpu.itb.inst_accesses                 61498384                       # ITB inst accesses
+system.cpu.itb.hits                          61493913                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61498403                       # DTB accesses
-system.cpu.numCycles                       5233072430                       # number of cpu cycles simulated
+system.cpu.itb.accesses                      61498384                       # DTB accesses
+system.cpu.numCycles                       5232459694                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60200059                       # Number of instructions committed
-system.cpu.committedOps                      76606878                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              69208659                       # Number of integer alu accesses
+system.cpu.committedInsts                    60200042                       # Number of instructions committed
+system.cpu.committedOps                      76606857                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              69208585                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
 system.cpu.num_func_calls                     2140468                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7948676                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     69208659                       # number of integer instructions
+system.cpu.num_conditional_control_insts      7948679                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     69208585                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           401368432                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           74518953                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           401368270                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           74518872                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27394027                       # number of memory refs
-system.cpu.num_load_insts                    15660244                       # Number of load instructions
-system.cpu.num_store_insts                   11733783                       # Number of store instructions
-system.cpu.num_idle_cycles               4581664281.608249                       # Number of idle cycles
-system.cpu.num_busy_cycles               651408148.391751                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.124479                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.875521                       # Percentage of idle cycles
-system.cpu.Branches                          10308791                       # Number of branches fetched
+system.cpu.num_mem_refs                      27394017                       # number of memory refs
+system.cpu.num_load_insts                    15660224                       # Number of load instructions
+system.cpu.num_store_insts                   11733793                       # Number of store instructions
+system.cpu.num_idle_cycles               4581582300.610249                       # Number of idle cycles
+system.cpu.num_busy_cycles               650877393.389751                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.124392                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.875608                       # Percentage of idle cycles
+system.cpu.Branches                          10308802                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                 28518      0.04%      0.04% # Class of executed instruction
+system.cpu.op_class::IntAlu                  50389316     64.68%     64.72% # Class of executed instruction
+system.cpu.op_class::IntMult                    87585      0.11%     64.83% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.83% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               2109      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.84% # Class of executed instruction
+system.cpu.op_class::MemRead                 15660224     20.10%     84.94% # Class of executed instruction
+system.cpu.op_class::MemWrite                11733793     15.06%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                   77901545                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    83016                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            856277                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.865256                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            60637143                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            856789                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.772551                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       20019652250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.865256                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997784                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997784                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    83017                       # number of quiesce instructions executed
+system.cpu.icache.tags.replacements            856351                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.866135                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            60637050                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            856863                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             70.766330                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       20005377250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.866135                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997785                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997785                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          267                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          193                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          269                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          62350721                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         62350721                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     60637143                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        60637143                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      60637143                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         60637143                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     60637143                       # number of overall hits
-system.cpu.icache.overall_hits::total        60637143                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       856789                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        856789                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       856789                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         856789                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       856789                       # number of overall misses
-system.cpu.icache.overall_misses::total        856789                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11768796500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11768796500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11768796500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11768796500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11768796500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11768796500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     61493932                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     61493932                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     61493932                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     61493932                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     61493932                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     61493932                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013933                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013933                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013933                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013933                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013933                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013933                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.933234                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13735.933234                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.933234                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13735.933234                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.933234                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13735.933234                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          62350776                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         62350776                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     60637050                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        60637050                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      60637050                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         60637050                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     60637050                       # number of overall hits
+system.cpu.icache.overall_hits::total        60637050                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       856863                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        856863                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       856863                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         856863                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       856863                       # number of overall misses
+system.cpu.icache.overall_misses::total        856863                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11766560750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11766560750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11766560750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11766560750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11766560750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11766560750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     61493913                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     61493913                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     61493913                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     61493913                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     61493913                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     61493913                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013934                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.013934                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.013934                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.013934                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.013934                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.013934                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13732.137751                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13732.137751                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13732.137751                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13732.137751                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13732.137751                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13732.137751                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -618,186 +647,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856789                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       856789                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       856789                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       856789                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       856789                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       856789                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10051259500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  10051259500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10051259500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  10051259500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10051259500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  10051259500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    442799750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    442799750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    442799750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    442799750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013933                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013933                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013933                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.312494                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.312494                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.312494                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.312494                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.312494                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.312494                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856863                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       856863                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       856863                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       856863                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       856863                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       856863                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10048829250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  10048829250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10048829250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  10048829250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10048829250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  10048829250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    441046000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    441046000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    441046000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    441046000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013934                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013934                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013934                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.013934                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013934                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.013934                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11727.463142                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11727.463142                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11727.463142                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11727.463142                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11727.463142                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11727.463142                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            62510                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        50754.341814                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1682268                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           127892                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            13.153817                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2565667436000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37718.224228                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884316                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements            62506                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        50753.322403                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1682121                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           127886                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            13.153285                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2565374310000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37717.253716                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884318                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000703                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6993.295627                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6038.936941                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.575534                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6993.225103                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6038.958564                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.575520                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000059                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.106709                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.106708                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.092147                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.774450                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.774434                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65378                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65376                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6903                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56263                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2163                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6647                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56517                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997589                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         17138143                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        17138143                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         8709                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3533                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       844568                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       369661                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1226471                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       595273                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       595273                       # number of Writeback hits
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997559                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         17140869                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        17140869                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         8713                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3537                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       844650                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       369794                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1226694                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       595396                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       595396                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       113398                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       113398                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         8709                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         3533                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       844568                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       483059                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1339869                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         8709                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         3533                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       844568                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       483059                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1339869                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       113396                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       113396                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         8713                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         3537                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       844650                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       483190                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1340090                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         8713                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         3537                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       844650                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       483190                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1340090                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        10585                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        10579                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data         9809                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        20401                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2905                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2905                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133827                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133827                       # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::total        20395                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2902                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2902                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133833                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133833                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        10585                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143636                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        10579                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       143642                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total        154228                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            5                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        10585                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143636                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        10579                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       143642                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       154228                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       397250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       305250                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       150000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    747154500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    739313250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1487015000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    743832250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    729584000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1473871500                       # number of ReadReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       469980                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       469980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9526600640                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9526600640                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       397250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9271605886                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9271605886                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       305250                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       150000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    747154500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10265913890                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11013615640                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       397250                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    743832250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10001189886                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10745477386                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       305250                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       150000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    747154500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10265913890                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11013615640                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         8714                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3535                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       855153                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       379470                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1246872                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       595273                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       595273                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2931                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2931                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       247225                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       247225                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         8714                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         3535                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       855153                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       626695                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1494097                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         8714                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         3535                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       855153                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       626695                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1494097                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_miss_latency::cpu.inst    743832250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10001189886                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10745477386                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         8718                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3539                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       855229                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       379603                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1247089                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       595396                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       595396                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2928                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2928                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       247229                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       247229                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         8718                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         3539                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       855229                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       626832                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1494318                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         8718                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         3539                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       855229                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       626832                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1494318                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000574                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000566                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012378                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025849                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016362                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991129                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991129                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541317                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.541317                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000565                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012370                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025840                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.016354                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991120                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991120                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541332                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.541332                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000574                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000566                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012378                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.229196                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.103225                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000565                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012370                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.229155                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.103210                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000574                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000566                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012378                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.229196                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.103225                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        79450                       # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000565                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012370                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.229155                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.103210                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        61050                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        75000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70586.159660                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75370.909369                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72889.319151                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   161.783133                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   161.783133                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71185.938861                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71185.938861                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        79450                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70312.151432                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74379.039657                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72266.315273                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   161.950379                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   161.950379                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69277.426987                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69277.426987                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        61050                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        75000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70586.159660                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71471.733340                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71411.258915                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        79450                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70312.151432                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69625.805029                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69672.675429                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        61050                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        75000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70586.159660                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71471.733340                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71411.258915                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70312.151432                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69625.805029                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69672.675429                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -806,92 +835,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        57910                       # number of writebacks
-system.cpu.l2cache.writebacks::total            57910                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        57911                       # number of writebacks
+system.cpu.l2cache.writebacks::total            57911                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10585                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10579                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         9809                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        20401                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2905                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2905                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133827                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133827                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        20395                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2902                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2902                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133833                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133833                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10585                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143636                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        10579                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143642                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total       154228                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10585                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143636                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        10579                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143642                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       154228                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       335750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       242750                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    614626500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    616437250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1231524500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29056905                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29056905                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7852026860                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7852026860                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       335750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    611350250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    606711500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1218429500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29025902                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29025902                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7597036114                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7597036114                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       242750                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    614626500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8468464110                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9083551360                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       335750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    611350250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8203747614                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8815465614                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       242750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    614626500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8468464110                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9083551360                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    351469750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664489250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167015959000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16706272596                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16706272596                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    351469750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370761846                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183722231596                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    611350250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8203747614                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8815465614                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    349718500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664427750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014146250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16706100672                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16706100672                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    349718500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370528422                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720246922                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000566                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012378                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025849                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016362                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991129                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991129                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541317                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541317                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012370                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025840                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016354                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991120                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991120                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541332                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541332                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000566                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012378                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229196                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.103225                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012370                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229155                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.103210                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000566                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012378                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229196                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.103225                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        67150                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012370                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229155                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.103210                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58065.800661                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62844.046284                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60365.888927                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.376936                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.376936                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.964798                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.964798                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        67150                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57789.039607                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61852.533388                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59741.578818                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.033770                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.033770                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56765.043853                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56765.043853                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58065.800661                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58957.810786                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58896.901730                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        67150                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57789.039607                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57112.457457                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57158.658700                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58065.800661                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58957.810786                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58896.901730                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57789.039607                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57112.457457                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57158.658700                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -901,87 +930,87 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            626183                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.875243                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            23656065                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            626695                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.747333                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         671680250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.875243                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999756                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999756                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            626320                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.875633                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            23655948                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            626832                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.738897                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         669376250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.875633                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999757                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999757                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          105                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          97757735                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         97757735                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13196205                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13196205                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9972754                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9972754                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236397                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236397                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247778                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247778                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23168959                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23168959                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23168959                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23168959                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       368088                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        368088                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250156                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250156                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11382                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11382                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       618244                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         618244                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       618244                       # number of overall misses
-system.cpu.dcache.overall_misses::total        618244                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5418733500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5418733500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11526229765                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11526229765                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    157891250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    157891250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  16944963265                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  16944963265                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  16944963265                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  16944963265                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13564293                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13564293                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222910                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222910                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247779                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247779                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247778                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247778                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23787203                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23787203                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23787203                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23787203                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027137                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.027137                       # miss rate for ReadReq accesses
+system.cpu.dcache.tags.tag_accesses          97757952                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         97757952                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13196101                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13196101                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9972757                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9972757                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236378                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236378                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247784                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247784                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      23168858                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         23168858                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     23168858                       # number of overall hits
+system.cpu.dcache.overall_hits::total        23168858                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       368196                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        368196                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       250157                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       250157                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11407                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        11407                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       618353                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         618353                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       618353                       # number of overall misses
+system.cpu.dcache.overall_misses::total        618353                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5410361250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5410361250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11271639016                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11271639016                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    158326750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    158326750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  16682000266                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  16682000266                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  16682000266                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  16682000266                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13564297                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13564297                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10222914                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222914                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247785                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       247785                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247784                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247784                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     23787211                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     23787211                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23787211                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     23787211                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027144                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.027144                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024470                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.024470                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045936                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045936                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025991                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025991                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025991                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025991                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14721.298983                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14721.298983                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46076.167531                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46076.167531                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13872.012827                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13872.012827                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 27408.213044                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 27408.213044                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27408.213044                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27408.213044                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046036                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046036                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.025995                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.025995                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.025995                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.025995                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14694.242333                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14694.242333                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45058.259477                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45058.259477                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13879.788726                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13879.788726                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26978.118107                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26978.118107                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26978.118107                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26978.118107                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -990,54 +1019,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       595273                       # number of writebacks
-system.cpu.dcache.writebacks::total            595273                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368088                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       368088                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250156                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250156                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11382                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        11382                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       618244                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       618244                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       618244                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       618244                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4680319500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4680319500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10976351235                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10976351235                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    135073750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    135073750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15656670735                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15656670735                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15656670735                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15656670735                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058625250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058625250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26242395404                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26242395404                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301020654                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301020654                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027137                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027137                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       595396                       # number of writebacks
+system.cpu.dcache.writebacks::total            595396                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368196                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       368196                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250157                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       250157                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11407                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        11407                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       618353                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       618353                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       618353                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       618353                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4671668750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4671668750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10721268984                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10721268984                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    135458250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    135458250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15392937734                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15392937734                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15392937734                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15392937734                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058578250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058578250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26242925328                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26242925328                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301503578                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301503578                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027144                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027144                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024470                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024470                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.045936                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.045936                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025991                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025991                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025991                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025991                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12715.218915                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12715.218915                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43878.025052                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43878.025052                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11867.312423                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11867.312423                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25324.420027                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25324.420027                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25324.420027                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25324.420027                       # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046036                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046036                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025995                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025995                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025995                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025995                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12687.994302                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12687.994302                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42858.161011                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42858.161011                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11875.010958                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11875.010958                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24893.447164                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24893.447164                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24893.447164                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24893.447164                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1045,37 +1074,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                52967752                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2454681                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2454681                       # Transaction distribution
+system.cpu.toL2Bus.throughput                52982138                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2454896                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2454896                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq        763385                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp       763385                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       595273                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2931                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2931                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       247225                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       247225                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1725204                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5749577                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12461                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27438                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7514680                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54756316                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83620422                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14140                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        34856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      138425734                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         138425734                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       166308                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3008713250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback       595396                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2928                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2928                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       247229                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       247229                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1725354                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5749970                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12465                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27449                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7515238                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54761180                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83637066                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14156                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        34872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      138447274                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         138447274                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       166176                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3009006000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1295332250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1295477750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2533285861                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2533767938                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer2.occupancy       8926000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      18724250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      18731500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
@@ -1093,10 +1122,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1763840630000                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1763840630000                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1763840630000                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1763840630000                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759698189250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1759698189250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759698189250                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1759698189250                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index e35c391b5..203fb6e65 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -4,103 +4,103 @@ sim_seconds                                  2.332812                       # Nu
 sim_ticks                                2332811899500                       # Number of ticks simulated
 final_tick                               2332811899500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1003640                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1290613                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            38755909714                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 421296                       # Number of bytes of host memory used
-host_seconds                                    60.19                       # Real time elapsed on the host
+host_inst_rate                                 860450                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1106481                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            33226597982                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 465868                       # Number of bytes of host memory used
+host_seconds                                    70.21                       # Real time elapsed on the host
 sim_insts                                    60411489                       # Number of instructions simulated
 sim_ops                                      77685090                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            9                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker          128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.inst           492808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6490328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          6490264                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst           212352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2581740                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            121450892                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2581696                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            121450784                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst       492808                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu1.inst       212352                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          705160                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3703232                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      3703360                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data       1405780                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1610064                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6719076                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1610036                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6719176                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker            2                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.inst             13912                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            101447                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            101446                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.inst              3318                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             40350                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14118200                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57863                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.data             40339                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14118188                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57865                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data           351445                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           402516                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811824                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           402509                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811819                       # Number of write requests responded to by this memory
 system.physmem.bw_read::realview.clcd        47870702                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker            55                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            82                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.inst              211251                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             2782191                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             2782163                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.inst               91028                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1106707                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52062017                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1106688                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52061970                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu0.inst         211251                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu1.inst          91028                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             302279                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1587454                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1587509                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data             602612                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             690182                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2880248                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1587454                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             690170                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2880291                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1587509                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.clcd       47870702                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           55                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           82                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.inst             211251                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3384803                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3384775                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.inst              91028                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1796889                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54942264                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            9                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     55969745                       # Throughput (bytes/s)
-system.membus.data_through_bus              130566887                       # Total data (bytes)
+system.physmem.bw_total::cpu1.data            1796858                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54942261                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     55969742                       # Throughput (bytes/s)
+system.membus.data_through_bus              130566879                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    62244                       # number of replacements
-system.l2c.tags.tagsinuse                50006.487761                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1678458                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   127629                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.151071                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    62245                       # number of replacements
+system.l2c.tags.tagsinuse                50006.493098                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1678467                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   127630                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    13.151038                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle             2316903124500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36900.766383                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   36901.760029                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.993822                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.993931                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.inst     4918.263908                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3149.549186                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3148.560878                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.inst     2096.452041                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.data     2939.468488                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.563061                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::writebacks      0.563076                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000015                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000015                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.075047                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.048058                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.048043                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.inst       0.031989                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.044853                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.763038                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.763039                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            2                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_blocks::1024        65383                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
@@ -111,19 +111,19 @@ system.l2c.tags.age_task_id_blocks_1024::3         9187                       #
 system.l2c.tags.age_task_id_blocks_1024::4        52391                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000031                       # Percentage of cache occupancy per task id
 system.l2c.tags.occ_task_id_percent::1024     0.997665                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 17104555                       # Number of tag accesses
-system.l2c.tags.data_accesses                17104555                       # Number of data accesses
+system.l2c.tags.tag_accesses                 17104618                       # Number of tag accesses
+system.l2c.tags.data_accesses                17104618                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker         9008                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         3279                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.inst             473060                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             196973                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             196974                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.dtb.walker         4855                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.itb.walker         2031                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst             365811                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             169795                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1224812                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          592687                       # number of Writeback hits
-system.l2c.Writeback_hits::total               592687                       # number of Writeback hits
+system.l2c.ReadReq_hits::cpu1.data             169798                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1224816                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          592692                       # number of Writeback hits
+system.l2c.Writeback_hits::total               592692                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data              12                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data              14                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
@@ -133,28 +133,28 @@ system.l2c.ReadExReq_hits::total               113738                       # nu
 system.l2c.demand_hits::cpu0.dtb.walker          9008                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.itb.walker          3279                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.inst              473060                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              260317                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              260318                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.dtb.walker          4855                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.itb.walker          2031                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.inst              365811                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              220189                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1338550                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              220192                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1338554                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.dtb.walker         9008                       # number of overall hits
 system.l2c.overall_hits::cpu0.itb.walker         3279                       # number of overall hits
 system.l2c.overall_hits::cpu0.inst             473060                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             260317                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             260318                       # number of overall hits
 system.l2c.overall_hits::cpu1.dtb.walker         4855                       # number of overall hits
 system.l2c.overall_hits::cpu1.itb.walker         2031                       # number of overall hits
 system.l2c.overall_hits::cpu1.inst             365811                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             220189                       # number of overall hits
-system.l2c.overall_hits::total                1338550                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             220192                       # number of overall hits
+system.l2c.overall_hits::total                1338554                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            2                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.inst             7286                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             5804                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             5803                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.inst             3318                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data             4068                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20481                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                20480                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu0.data          1525                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu1.data          1394                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              2919                       # number of UpgradeReq misses
@@ -164,17 +164,17 @@ system.l2c.ReadExReq_misses::total             133474                       # nu
 system.l2c.demand_misses::cpu0.dtb.walker            2                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.inst              7286                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            102226                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            102225                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.inst              3318                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.data             41120                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153955                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                153954                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            2                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
 system.l2c.overall_misses::cpu0.inst             7286                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           102226                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           102225                       # number of overall misses
 system.l2c.overall_misses::cpu1.inst             3318                       # number of overall misses
 system.l2c.overall_misses::cpu1.data            41120                       # number of overall misses
-system.l2c.overall_misses::total               153955                       # number of overall misses
+system.l2c.overall_misses::total               153954                       # number of overall misses
 system.l2c.ReadReq_accesses::cpu0.dtb.walker         9010                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.itb.walker         3282                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.inst         480346                       # number of ReadReq accesses(hits+misses)
@@ -182,10 +182,10 @@ system.l2c.ReadReq_accesses::cpu0.data         202777                       # nu
 system.l2c.ReadReq_accesses::cpu1.dtb.walker         4855                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.itb.walker         2031                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.inst         369129                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         173863                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1245293                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       592687                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           592687                       # number of Writeback accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         173866                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1245296                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       592692                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           592692                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data         1537                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data         1408                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            2945                       # number of UpgradeReq accesses(hits+misses)
@@ -199,8 +199,8 @@ system.l2c.demand_accesses::cpu0.data          362543                       # nu
 system.l2c.demand_accesses::cpu1.dtb.walker         4855                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.itb.walker         2031                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst          369129                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          261309                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1492505                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          261312                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1492508                       # number of demand (read+write) accesses
 system.l2c.overall_accesses::cpu0.dtb.walker         9010                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.itb.walker         3282                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.inst         480346                       # number of overall (read+write) accesses
@@ -208,15 +208,15 @@ system.l2c.overall_accesses::cpu0.data         362543                       # nu
 system.l2c.overall_accesses::cpu1.dtb.walker         4855                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.itb.walker         2031                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.inst         369129                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         261309                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1492505                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         261312                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1492508                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000222                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000914                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.inst      0.015168                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.028623                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.028618                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.008989                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.023398                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016447                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.023397                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016446                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992193                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.990057                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       0.991171                       # miss rate for UpgradeReq accesses
@@ -226,17 +226,17 @@ system.l2c.ReadExReq_miss_rate::total        0.539917                       # mi
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000222                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.000914                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.015168                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.281969                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.281967                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.008989                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.157362                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.103152                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.157360                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.103151                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000222                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.000914                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.015168                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.281969                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.281967                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.008989                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.157362                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.103152                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.157360                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.103151                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -245,8 +245,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57863                       # number of writebacks
-system.l2c.writebacks::total                    57863                       # number of writebacks
+system.l2c.writebacks::writebacks               57865                       # number of writebacks
+system.l2c.writebacks::total                    57865                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -254,8 +254,8 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    59119535                       # Throughput (bytes/s)
-system.toL2Bus.data_through_bus             137914755                       # Total data (bytes)
+system.toL2Bus.throughput                    59119724                       # Throughput (bytes/s)
+system.toL2Bus.data_through_bus             137915195                       # Total data (bytes)
 system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
 system.iobus.throughput                      48895283                       # Throughput (bytes/s)
 system.iobus.data_through_bus               114063499                       # Total data (bytes)
@@ -366,6 +366,41 @@ system.cpu0.num_busy_cycles              75843061.764530                       #
 system.cpu0.not_idle_fraction                0.016397                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.983603                       # Percentage of idle cycles
 system.cpu0.Branches                          5613326                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                16463      0.04%      0.04% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 26898614     64.08%     64.12% # Class of executed instruction
+system.cpu0.op_class::IntMult                   45874      0.11%     64.23% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.23% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              1340      0.00%     64.24% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.24% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.24% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.24% # Class of executed instruction
+system.cpu0.op_class::MemRead                 8305325     19.79%     84.02% # Class of executed instruction
+system.cpu0.op_class::MemWrite                6706507     15.98%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                  41974123                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   82795                       # number of quiesce instructions executed
 system.cpu0.icache.tags.replacements           850590                       # number of replacements
@@ -432,14 +467,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           623340                       # number of replacements
+system.cpu0.dcache.tags.replacements           623343                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997030                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           23628946                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           623852                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            37.875884                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           23628961                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           623855                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            37.875726                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         21768000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   451.291431                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    60.705599                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   451.291422                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    60.705608                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.881429                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::cpu1.data     0.118566                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
@@ -448,59 +483,59 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0          278
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         97635044                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        97635044                       # Number of data accesses
+system.cpu0.dcache.tags.tag_accesses         97635119                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        97635119                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      6996051                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      6184470                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13180521                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      6184476                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13180527                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data      5775160                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      4187066                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       9962226                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      4187070                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       9962230                       # number of WriteReq hits
 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139339                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        96697                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       236036                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        96699                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       236038                       # number of LoadLockedReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu0.data       145986                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       101232                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247218                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       101235                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247221                       # number of StoreCondReq hits
 system.cpu0.dcache.demand_hits::cpu0.data     12771211                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     10371536                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        23142747                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     10371546                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        23142757                       # number of demand (read+write) hits
 system.cpu0.dcache.overall_hits::cpu0.data     12771211                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     10371536                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       23142747                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     10371546                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       23142757                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data       196129                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       169328                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       365457                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       169330                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       365459                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data       161303                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::cpu1.data        88854                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total       250157                       # number of WriteReq misses
 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6648                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         4535                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        11183                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         4536                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11184                       # number of LoadLockedReq misses
 system.cpu0.dcache.demand_misses::cpu0.data       357432                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       258182                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        615614                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       258184                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        615616                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data       357432                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       258182                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       615614                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       258184                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       615616                       # number of overall misses
 system.cpu0.dcache.ReadReq_accesses::cpu0.data      7192180                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      6353798                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13545978                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      6353806                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13545986                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data      5936463                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      4275920                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10212383                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      4275924                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10212387                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       145987                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       101232                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       247219                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       101235                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       247222                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       145986                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       101232                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247218                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       101235                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247221                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.demand_accesses::cpu0.data     13128643                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     10629718                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     23758361                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     10629730                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     23758373                       # number of demand (read+write) accesses
 system.cpu0.dcache.overall_accesses::cpu0.data     13128643                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     10629718                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     23758361                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     10629730                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     23758373                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027270                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.026650                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.026979                       # miss rate for ReadReq accesses
@@ -508,14 +543,14 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027172
 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.020780                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.045538                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044798                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.045235                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044807                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.045239                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027225                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024289                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.025911                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027225                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::cpu1.data     0.024289                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.025911                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -524,8 +559,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       592687                       # number of writebacks
-system.cpu0.dcache.writebacks::total           592687                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       592692                       # number of writebacks
+system.cpu0.dcache.writebacks::total           592692                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -634,6 +669,41 @@ system.cpu1.num_busy_cycles              69683264.930565                       #
 system.cpu1.not_idle_fraction                0.016273                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.983727                       # Percentage of idle cycles
 system.cpu1.Branches                          4685935                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                12055      0.03%      0.03% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 23438937     65.39%     65.42% # Class of executed instruction
+system.cpu1.op_class::IntMult                   41906      0.12%     65.54% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc               777      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.54% # Class of executed instruction
+system.cpu1.op_class::MemRead                 7334763     20.46%     86.01% # Class of executed instruction
+system.cpu1.op_class::MemWrite                5015826     13.99%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                  35844264                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.iocache.tags.replacements                    0                       # number of replacements
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 291aa5d2a..07ebe167c 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.112126                       # Nu
 sim_ticks                                5112126264500                       # Number of ticks simulated
 final_tick                               5112126264500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1019778                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2087932                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            26075321841                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 640200                       # Number of bytes of host memory used
-host_seconds                                   196.05                       # Real time elapsed on the host
+host_inst_rate                                1285356                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2631685                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            32866027497                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 626676                       # Number of bytes of host memory used
+host_seconds                                   155.54                       # Real time elapsed on the host
 sim_insts                                   199929810                       # Number of instructions simulated
 sim_ops                                     409343850                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -141,6 +141,41 @@ system.cpu.num_busy_cycles               453735690.308166
 system.cpu.not_idle_fraction                 0.044378                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.955622                       # Percentage of idle cycles
 system.cpu.Branches                          43125514                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                175310      0.04%      0.04% # Class of executed instruction
+system.cpu.op_class::IntAlu                 373241321     91.18%     91.22% # Class of executed instruction
+system.cpu.op_class::IntMult                   144368      0.04%     91.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                    122968      0.03%     91.29% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.29% # Class of executed instruction
+system.cpu.op_class::MemRead                 27238816      6.65%     97.94% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8422097      2.06%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  409344880                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
 system.cpu.icache.tags.replacements            790558                       # number of replacements
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 03f4934d5..60b3a8779 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,135 +1,135 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.200402                       # Number of seconds simulated
-sim_ticks                                5200402495000                       # Number of ticks simulated
-final_tick                               5200402495000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.200396                       # Number of seconds simulated
+sim_ticks                                5200396150000                       # Number of ticks simulated
+final_tick                               5200396150000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1256922                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2423033                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            50949381192                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 591984                       # Number of bytes of host memory used
-host_seconds                                   102.07                       # Real time elapsed on the host
-sim_insts                                   128294014                       # Number of instructions simulated
-sim_ops                                     247318948                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 778841                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1501355                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31560622919                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 627712                       # Number of bytes of host memory used
+host_seconds                                   164.77                       # Real time elapsed on the host
+sim_insts                                   128333376                       # Number of instructions simulated
+sim_ops                                     247385531                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2869888                       # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide      2886336                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            826752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8970624                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12667648                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       826752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          826752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8094016                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8094016                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        44842                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst            825216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8967296                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             12679232                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       825216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          825216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8106560                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8106560                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        45099                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12918                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             140166                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                197932                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          126469                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               126469                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       551859                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst              12894                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             140114                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                198113                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126665                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               126665                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       555022                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               158978                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1724986                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2435898                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          158978                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             158978                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1556421                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1556421                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1556421                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       551859                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               158683                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1724349                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2438128                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          158683                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             158683                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1558835                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1558835                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1558835                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       555022                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              158978                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1724986                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3992319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        197932                       # Number of read requests accepted
-system.physmem.writeReqs                       126469                       # Number of write requests accepted
-system.physmem.readBursts                      197932                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     126469                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12654528                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     13120                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8092032                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12667648                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8094016                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      205                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst              158683                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1724349                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3996963                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        198113                       # Number of read requests accepted
+system.physmem.writeReqs                       126665                       # Number of write requests accepted
+system.physmem.readBursts                      198113                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     126665                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12670976                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8256                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8105536                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12679232                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8106560                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      129                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1622                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12706                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12058                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12568                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12134                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12521                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12218                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12048                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12245                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12013                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12113                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12409                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              12495                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12992                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12976                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12442                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11789                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8349                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7660                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8054                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7772                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8164                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7804                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7601                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7742                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7412                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7677                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8006                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7919                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8539                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8375                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8051                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7313                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           1623                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12177                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12548                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               13053                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12620                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12592                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12288                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11961                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12236                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11972                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11957                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              12338                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              12177                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12807                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12813                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12433                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              12012                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7757                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8145                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8603                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8164                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8201                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7973                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7511                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7789                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7356                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7874                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7684                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8313                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8300                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7968                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7488                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5200402431500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5200396086500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  197932                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  198113                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 126469                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    153822                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2802                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2836                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      2322                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2661                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5083                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4526                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4292                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3878                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2499                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2187                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1998                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1775                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1085                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1035                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      994                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      939                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      873                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      635                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       30                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 126665                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    153621                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2695                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      4322                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      2990                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      3543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4544                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4208                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3990                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3280                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2652                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2195                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1870                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1376                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1254                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1028                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     1144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      834                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      668                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      612                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       25                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -156,116 +156,112 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1931                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4818                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5027                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6982                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5886                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7068                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1812                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5075                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5335                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5794                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5985                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6999                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7801                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7468                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1858                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2408                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     2636                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     2551                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                     2242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     2142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     2178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1001                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      780                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      690                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        6                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        36378                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      449.321238                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     264.022911                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     400.116091                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           9783     26.89%     26.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         7520     20.67%     47.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3398      9.34%     56.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1958      5.38%     62.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1470      4.04%     66.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          950      2.61%     68.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          669      1.84%     70.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          516      1.42%     72.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        10114     27.80%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          36378                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6806                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.049956                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      579.203336                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6805     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::39                     1885                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        59433                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      349.577642                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     202.117781                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     357.932182                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          20505     34.50%     34.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        13774     23.18%     57.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5765      9.70%     67.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3461      5.82%     73.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2240      3.77%     76.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1591      2.68%     79.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1115      1.88%     81.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          921      1.55%     83.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10061     16.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          59433                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6976                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.380447                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      572.057676                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6975     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6806                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6806                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.577432                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.979234                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.072144                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            4358     64.03%     64.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            1673     24.58%     88.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              85      1.25%     89.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              45      0.66%     90.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              78      1.15%     91.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27             127      1.87%     93.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29              53      0.78%     94.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31              38      0.56%     94.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33              25      0.37%     95.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35              74      1.09%     96.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37              52      0.76%     97.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39              16      0.24%     97.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41              72      1.06%     98.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43              19      0.28%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45              28      0.41%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47              13      0.19%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               8      0.12%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               5      0.07%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               7      0.10%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               5      0.07%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               2      0.03%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59               2      0.03%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61               1      0.01%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63               5      0.07%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-65              13      0.19%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-69               1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::74-75               1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6806                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5807464000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9465482750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    988635000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  2669383750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       29371.12                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13500.35                       # Average bank access latency per DRAM burst
+system.physmem.rdPerTurnAround::total            6976                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6976                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.154960                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.623474                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        5.583584                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            4785     68.59%     68.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            1454     20.84%     89.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              33      0.47%     89.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23             125      1.79%     91.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              57      0.82%     92.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              47      0.67%     93.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              75      1.08%     94.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31              59      0.85%     95.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33              41      0.59%     95.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35              19      0.27%     95.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37              30      0.43%     96.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39              56      0.80%     97.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41             145      2.08%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43              17      0.24%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               4      0.06%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47              11      0.16%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               3      0.04%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               3      0.04%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               2      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               2      0.03%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59               1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62-63               3      0.04%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-69               1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6976                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5514862500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9227062500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    989920000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27855.09                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47871.47                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.43                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46605.09                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.44                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.44                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
@@ -273,99 +269,103 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.17                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     167067                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     99118                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.49                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.37                       # Row buffer hit rate for writes
-system.physmem.avgGap                     16030784.22                       # Average gap between requests
-system.physmem.pageHitRate                      82.11                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.28                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      4355532                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              623246                       # Transaction distribution
-system.membus.trans_dist::ReadResp             623246                       # Transaction distribution
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.98                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     166366                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     98833                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.03                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.03                       # Row buffer hit rate for writes
+system.physmem.avgGap                     16012156.26                       # Average gap between requests
+system.physmem.pageHitRate                      81.69                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4979189621500                       # Time in different power states
+system.physmem.memoryStateTime::REF      173652440000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       47553973500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      4356964                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              623381                       # Transaction distribution
+system.membus.trans_dist::ReadResp             623381                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13777                       # Transaction distribution
 system.membus.trans_dist::WriteResp             13777                       # Transaction distribution
-system.membus.trans_dist::Writeback            126469                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2149                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1640                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            159500                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           159500                       # Transaction distribution
+system.membus.trans_dist::Writeback            126665                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2155                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1641                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            159285                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           159285                       # Transaction distribution
 system.membus.trans_dist::MessageReq             1656                       # Transaction distribution
 system.membus.trans_dist::MessageResp            1656                       # Transaction distribution
 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3312                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.apicbridge.master::total         3312                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       480328                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710118                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       390403                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1580849                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       139069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       139069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1723230                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       390454                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1580900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       139322                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       139322                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1723534                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.apicbridge.master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       246444                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420233                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14905088                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     16571765                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5856576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5856576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            22434965                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               22434965                       # Total data (bytes)
-system.membus.snoop_data_through_bus           215552                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           256796000                       # Layer occupancy (ticks)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14912768                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     16579445                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5873024                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      5873024                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            22459093                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               22459093                       # Total data (bytes)
+system.membus.snoop_data_through_bus           198848                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           256797000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           359324000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           359321500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy             3312000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1349763000                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1351243000                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer0.occupancy            1656000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2610332746                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2609486505                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy          429200500                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy          429020250                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47505                       # number of replacements
-system.iocache.tags.tagsinuse                0.134382                       # Cycle average of tags in use
+system.iocache.tags.replacements                47501                       # number of replacements
+system.iocache.tags.tagsinuse                0.128246                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47521                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47517                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5049788540000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.134382                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008399                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.008399                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5049779388000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.128246                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008015                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.008015                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428040                       # Number of tag accesses
-system.iocache.tags.data_accesses              428040                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          840                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              840                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428004                       # Number of tag accesses
+system.iocache.tags.data_accesses              428004                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          836                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              836                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47560                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47560                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47560                       # number of overall misses
-system.iocache.overall_misses::total            47560                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    142383686                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    142383686                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  12484793248                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12484793248                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide  12627176934                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12627176934                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide  12627176934                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12627176934                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          840                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            840                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47556                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47556                       # number of overall misses
+system.iocache.overall_misses::total            47556                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    140309686                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    140309686                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  12229393602                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  12229393602                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide  12369703288                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  12369703288                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide  12369703288                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  12369703288                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          836                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            836                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47560                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47560                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47560                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47560                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47556                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47556                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47556                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47556                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -374,40 +374,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169504.388095                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 169504.388095                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267225.882877                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 267225.882877                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265499.935534                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 265499.935534                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265499.935534                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 265499.935534                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        224342                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167834.552632                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167834.552632                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 261759.280865                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 261759.280865                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 260108.152242                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 260108.152242                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 260108.152242                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 260108.152242                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        207651                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                18183                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                17427                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.338008                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.915476                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          840                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          840                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          836                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          836                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47560                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47560                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47560                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47560                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     98678186                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     98678186                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide  10053057748                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10053057748                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide  10151735934                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10151735934                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide  10151735934                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10151735934                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47556                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47556                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47556                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96812686                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     96812686                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   9797946102                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   9797946102                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   9894758788                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9894758788                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   9894758788                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9894758788                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -416,14 +416,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117474.030952                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 117474.030952                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215176.749743                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 215176.749743                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 213451.134020                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 213451.134020                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115804.648325                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115804.648325                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 209716.312115                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 209716.312115                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 208065.413155                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 208065.413155                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -437,9 +437,9 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.throughput                        630784                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq               230145                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              230145                       # Transaction distribution
+system.iobus.throughput                        630779                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               230141                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              230141                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57579                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              57579                       # Transaction distribution
 system.iobus.trans_dist::MessageReq              1656                       # Transaction distribution
@@ -463,11 +463,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       480328                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95120                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95112                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95112                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3312                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3312                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  578760                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  578752                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
@@ -487,13 +487,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::total       246444                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027264                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027264                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6624                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              3280332                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 3280332                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              3953400                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total              3280300                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 3280300                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              3954900                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -529,98 +529,133 @@ system.iobus.reqLayer16.occupancy                9000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           425604434                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           424640038                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy           469469000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            53343500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            53686750                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer2.occupancy             1656000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10400804990                       # number of cpu cycles simulated
+system.cpu.numCycles                      10400792300                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   128294014                       # Number of instructions committed
-system.cpu.committedOps                     247318948                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             231911784                       # Number of integer alu accesses
+system.cpu.committedInsts                   128333376                       # Number of instructions committed
+system.cpu.committedOps                     247385531                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             231978349                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                     2299833                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     23159249                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    231911784                       # number of integer instructions
+system.cpu.num_func_calls                     2299991                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     23168967                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    231978349                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           434400113                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          197801183                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           434511356                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          197852349                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            132752064                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            95494911                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      22235692                       # number of memory refs
-system.cpu.num_load_insts                    13875118                       # Number of load instructions
-system.cpu.num_store_insts                    8360574                       # Number of store instructions
-system.cpu.num_idle_cycles               9794078774.998117                       # Number of idle cycles
-system.cpu.num_busy_cycles               606726215.001883                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.058335                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.941665                       # Percentage of idle cycles
-system.cpu.Branches                          26297154                       # Number of branches fetched
+system.cpu.num_cc_register_reads            132811982                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            95533715                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      22244872                       # number of memory refs
+system.cpu.num_load_insts                    13879055                       # Number of load instructions
+system.cpu.num_store_insts                    8365817                       # Number of store instructions
+system.cpu.num_idle_cycles               9793794512.998117                       # Number of idle cycles
+system.cpu.num_busy_cycles               606997787.001883                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.058361                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.941639                       # Percentage of idle cycles
+system.cpu.Branches                          26307123                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                174810      0.07%      0.07% # Class of executed instruction
+system.cpu.op_class::IntAlu                 224704553     90.83%     90.90% # Class of executed instruction
+system.cpu.op_class::IntMult                   139755      0.06%     90.96% # Class of executed instruction
+system.cpu.op_class::IntDiv                    123089      0.05%     91.01% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.01% # Class of executed instruction
+system.cpu.op_class::MemRead                 13879055      5.61%     96.62% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8365817      3.38%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  247387079                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            791422                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.352385                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           144521518                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            791934                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            182.491872                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      161455178250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.352385                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996782                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996782                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            791030                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.352813                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           144579864                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            791542                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            182.655960                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      161437750250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.352813                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996783                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996783                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          298                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146105400                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146105400                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    144521518                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       144521518                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     144521518                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        144521518                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    144521518                       # number of overall hits
-system.cpu.icache.overall_hits::total       144521518                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       791941                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        791941                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       791941                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         791941                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       791941                       # number of overall misses
-system.cpu.icache.overall_misses::total        791941                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11119349759                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11119349759                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11119349759                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11119349759                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11119349759                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11119349759                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    145313459                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    145313459                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    145313459                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    145313459                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    145313459                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    145313459                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005450                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.005450                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.005450                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.005450                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.005450                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.005450                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14040.628985                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14040.628985                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14040.628985                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14040.628985                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14040.628985                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14040.628985                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         146162962                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146162962                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    144579864                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       144579864                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     144579864                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        144579864                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    144579864                       # number of overall hits
+system.cpu.icache.overall_hits::total       144579864                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       791549                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        791549                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       791549                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         791549                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       791549                       # number of overall misses
+system.cpu.icache.overall_misses::total        791549                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11108553755                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11108553755                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11108553755                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11108553755                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11108553755                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11108553755                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    145371413                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    145371413                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    145371413                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    145371413                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    145371413                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    145371413                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005445                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.005445                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.005445                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.005445                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.005445                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.005445                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14033.943262                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14033.943262                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14033.943262                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14033.943262                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14033.943262                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14033.943262                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -629,88 +664,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791941                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       791941                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       791941                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       791941                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       791941                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       791941                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9530763241                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   9530763241                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9530763241                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   9530763241                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9530763241                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   9530763241                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005450                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005450                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005450                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.005450                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005450                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.005450                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12034.688494                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12034.688494                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12034.688494                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12034.688494                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12034.688494                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12034.688494                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791549                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       791549                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       791549                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       791549                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       791549                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       791549                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9520697745                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9520697745                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9520697745                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9520697745                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9520697745                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9520697745                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005445                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005445                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005445                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.005445                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005445                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.005445                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.932251                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.932251                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.932251                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.932251                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.932251                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.932251                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements         3448                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.074851                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs         7916                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs         3460                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     2.287861                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5178780288000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.074851                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.192178                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.192178                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.replacements         3407                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     3.079507                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs         7935                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs         3418                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     2.321533                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5169623666000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.079507                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.192469                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.192469                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           11                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        28763                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        28763                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7916                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         7916                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        28718                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        28718                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7937                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total         7937                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7918                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         7918                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7918                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         7918                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4309                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4309                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4309                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4309                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4309                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4309                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     42842750                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total     42842750                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     42842750                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total     42842750                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     42842750                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total     42842750                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12225                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12225                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7939                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total         7939                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7939                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total         7939                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4280                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         4280                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4280                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         4280                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4280                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         4280                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     42457500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     42457500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     42457500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     42457500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     42457500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     42457500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12217                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        12217                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12227                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12227                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12227                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12227                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.352474                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.352474                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.352417                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.352417                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.352417                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.352417                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9942.620097                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9942.620097                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9942.620097                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9942.620097                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9942.620097                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9942.620097                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12219                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        12219                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12219                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        12219                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.350332                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.350332                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.350274                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.350274                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.350274                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.350274                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9919.976636                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9919.976636                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9919.976636                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9919.976636                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9919.976636                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9919.976636                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -719,86 +754,86 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          776                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          776                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4309                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4309                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4309                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         4309                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4309                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         4309                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     34223750                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     34223750                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     34223750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     34223750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     34223750                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     34223750                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.352474                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.352474                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.352417                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.352417                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.352417                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.352417                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7942.388025                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7942.388025                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7942.388025                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7942.388025                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7942.388025                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7942.388025                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks          704                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          704                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4280                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4280                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4280                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         4280                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4280                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         4280                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     33895500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     33895500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     33895500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     33895500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     33895500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     33895500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.350332                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.350332                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.350274                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.350274                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.350274                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.350274                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7919.509346                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7919.509346                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7919.509346                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7919.509346                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7919.509346                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7919.509346                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements         8116                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.061830                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        12619                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs         8130                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.552153                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5165732872000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.061830                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.316364                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.316364                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements         7502                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.061351                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        13282                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs         7516                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.767163                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5167976228000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.061351                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.316334                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.316334                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        53134                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        53134                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12626                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12626                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12626                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12626                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12626                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12626                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9294                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         9294                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9294                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         9294                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9294                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         9294                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     98603000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     98603000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     98603000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total     98603000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     98603000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total     98603000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21920                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21920                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21920                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21920                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21920                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21920                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.423996                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.423996                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.423996                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.423996                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.423996                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.423996                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10609.317839                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10609.317839                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10609.317839                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10609.317839                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10609.317839                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10609.317839                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses        52668                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        52668                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13284                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        13284                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13284                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        13284                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13284                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        13284                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8700                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         8700                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8700                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         8700                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8700                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         8700                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     92345000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     92345000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     92345000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total     92345000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     92345000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total     92345000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21984                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        21984                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21984                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        21984                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21984                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        21984                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.395742                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.395742                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.395742                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.395742                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.395742                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.395742                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10614.367816                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10614.367816                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10614.367816                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10614.367816                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10614.367816                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10614.367816                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -807,98 +842,98 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         3085                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         3085                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         9294                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         9294                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         9294                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total         9294                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         9294                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total         9294                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     80015000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     80015000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     80015000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     80015000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     80015000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     80015000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.423996                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.423996                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.423996                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.423996                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.423996                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.423996                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8609.317839                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8609.317839                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8609.317839                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8609.317839                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8609.317839                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8609.317839                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks         3054                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         3054                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8700                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8700                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8700                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         8700                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8700                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         8700                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     74944500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     74944500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     74944500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     74944500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     74944500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     74944500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.395742                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.395742                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.395742                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.395742                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.395742                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.395742                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8614.310345                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8614.310345                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8614.310345                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8614.310345                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8614.310345                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8614.310345                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1620672                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997242                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20026945                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1621184                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.353283                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          51279250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997242                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1620643                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997078                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            20036158                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1621155                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.359187                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          51171250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997078                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88213750                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88213750                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     11989262                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11989262                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8035472                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8035472                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      20024734                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20024734                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20024734                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20024734                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1308613                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1308613                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       314792                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       314792                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1623405                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1623405                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1623405                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1623405                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18824282553                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18824282553                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10745506942                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10745506942                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  29569789495                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  29569789495                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  29569789495                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  29569789495                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13297875                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13297875                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8350264                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8350264                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21648139                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21648139                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21648139                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21648139                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098408                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098408                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037698                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037698                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074991                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074991                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074991                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074991                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14384.911775                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14384.911775                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34135.260559                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34135.260559                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18214.671936                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18214.671936                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18214.671936                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18214.671936                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          88250512                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88250512                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11993410                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11993410                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8040535                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8040535                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      20033945                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20033945                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20033945                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20033945                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1308416                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1308416                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       314973                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       314973                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1623389                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1623389                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1623389                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1623389                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  18840132304                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  18840132304                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10814294936                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10814294936                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  29654427240                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  29654427240                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  29654427240                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  29654427240                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13301826                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13301826                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8355508                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8355508                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21657334                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21657334                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21657334                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21657334                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098364                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098364                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037696                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037696                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074958                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074958                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074958                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074958                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.191315                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.191315                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.037952                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.037952                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18266.987912                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18266.987912                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18266.987912                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18266.987912                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -907,46 +942,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1537729                       # number of writebacks
-system.cpu.dcache.writebacks::total           1537729                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308613                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1308613                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       314792                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       314792                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1623405                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1623405                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1623405                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1623405                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  16198393447                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  16198393447                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10064156058                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10064156058                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26262549505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26262549505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26262549505                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26262549505                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      1537613                       # number of writebacks
+system.cpu.dcache.writebacks::total           1537613                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308416                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1308416                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       314973                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       314973                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1623389                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1623389                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1623389                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1623389                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  16214330696                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  16214330696                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10132215064                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10132215064                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26346545760                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26346545760                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26346545760                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26346545760                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94214672500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94214672500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2537739500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2537739500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96752412000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  96752412000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098408                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098408                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037698                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037698                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074991                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.074991                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074991                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.074991                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12378.291708                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12378.291708                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31970.812657                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31970.812657                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16177.447713                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16177.447713                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16177.447713                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16177.447713                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2537738000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2537738000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96752410500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  96752410500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098364                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098364                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037696                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037696                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074958                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.074958                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074958                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074958                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12392.335997                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12392.335997                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32168.519410                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32168.519410                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16229.348456                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16229.348456                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16229.348456                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16229.348456                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -954,184 +989,184 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                49161645                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2696443                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2695917                       # Transaction distribution
+system.cpu.toL2Bus.throughput                49146383                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2695227                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2694701                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         13777                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        13777                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1541590                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2211                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2211                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       359301                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       312590                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1583869                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5973994                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         7897                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        19197                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7584957                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50683392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203806901                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       229632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       633792                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      255353717                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         255333045                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       327296                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3831359500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback      1541371                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2213                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2213                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       359480                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       312780                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1583085                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5973901                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         7764                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18139                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7582889                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50658304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203802165                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       222976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       604096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      255287541                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         255266421                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       314240                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3830515500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       484500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       495000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1190263759                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1189702505                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3051445995                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3051756740                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy       6464000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy       6421000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      13941000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      13050250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements            86417                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64729.830083                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3490254                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           151212                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.081859                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            86651                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64733.611120                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3487942                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           151340                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            23.047060                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50287.594494                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.027550                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141486                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3384.035479                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11058.031076                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.767328                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50209.763854                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.027833                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141473                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3434.458363                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11089.219598                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.766140                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.051636                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.168732                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.987699                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64795                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          115                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2818                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4824                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56981                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.988693                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         32189031                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        32189031                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6817                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2807                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       779009                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1279777                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2068410                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1541590                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1541590                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          307                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          307                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       199552                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       199552                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         6817                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         2807                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       779009                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1479329                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2267962                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         6817                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         2807                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       779009                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1479329                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2267962                       # number of overall hits
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052406                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.169208                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.987757                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64689                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2880                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4787                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56896                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987076                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         32180689                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        32180689                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6384                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2775                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       778641                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1279470                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2067270                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1541371                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1541371                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          305                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          305                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       199944                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       199944                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         6384                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         2775                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       778641                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1479414                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2267214                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         6384                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         2775                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       778641                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1479414                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2267214                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12919                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        28035                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        40960                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1395                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1395                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       113025                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       113025                       # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        12895                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        28198                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        41099                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1394                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1394                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       112812                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       112812                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12919                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       141060                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        153985                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        12895                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       141010                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        153911                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12919                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       141060                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       153985                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker        75000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       347500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    948719241                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2091207947                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3040349688                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16786842                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     16786842                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7717314435                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7717314435                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker        75000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       347500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    948719241                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   9808522382                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10757664123                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker        75000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       347500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    948719241                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   9808522382                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10757664123                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6818                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2812                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       791928                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1307812                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2109370                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1541590                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1541590                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1702                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1702                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       312577                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       312577                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6818                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         2812                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       791928                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1620389                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2421947                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6818                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         2812                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       791928                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1620389                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2421947                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000147                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001778                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016313                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021437                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.019418                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.819624                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.819624                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.361591                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.361591                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000147                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001778                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016313                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.087053                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.063579                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000147                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001778                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016313                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.087053                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.063579                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        75000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        69500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73435.965709                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74592.757161                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74227.287305                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12033.578495                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12033.578495                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68279.711878                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68279.711878                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        75000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        69500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73435.965709                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69534.399419                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69861.766555                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        75000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        69500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73435.965709                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69534.399419                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69861.766555                       # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.inst        12895                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       141010                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       153911                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker        89250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       365000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    942725495                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2110465196                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   3053644941                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16120870                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     16120870                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7781341940                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7781341940                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker        89250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       365000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    942725495                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   9891807136                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10834986881                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker        89250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       365000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    942725495                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   9891807136                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10834986881                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6385                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2780                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       791536                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1307668                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2108369                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1541371                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1541371                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1699                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1699                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       312756                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       312756                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6385                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         2780                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       791536                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1620424                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2421125                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6385                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         2780                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       791536                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1620424                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2421125                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000157                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001799                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016291                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021564                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.019493                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.820483                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.820483                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.360703                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.360703                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000157                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001799                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016291                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.087020                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.063570                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000157                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001799                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016291                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.087020                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.063570                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        89250                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        73000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73107.832105                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74844.499468                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74299.738217                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11564.469154                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11564.469154                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68976.189944                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68976.189944                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        89250                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        73000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73107.832105                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70149.685384                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70397.742078                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        89250                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        73000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73107.832105                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70149.685384                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70397.742078                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1140,90 +1175,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        79802                       # number of writebacks
-system.cpu.l2cache.writebacks::total            79802                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        79998                       # number of writebacks
+system.cpu.l2cache.writebacks::total            79998                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            1                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12919                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28035                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        40960                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1395                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1395                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113025                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       113025                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12895                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28198                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        41099                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1394                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1394                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       112812                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       112812                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12919                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       141060                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       153985                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        12895                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       141010                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       153911                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            1                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12919                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       141060                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       153985                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       285000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    786875759                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1740299053                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2527522312                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14883877                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14883877                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6303896565                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6303896565                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    786875759                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8044195618                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8831418877                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker        62500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       285000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    786875759                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8044195618                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8831418877                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12895                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       141010                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       153911                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker        76250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       301500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    781175005                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1757280304                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2538833059                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14868876                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14868876                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6370597060                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6370597060                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       301500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    781175005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8127877364                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8909430119                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker        76250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       301500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    781175005                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8127877364                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8909430119                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86655869000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86655869000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2371074000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2371074000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89026943000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89026943000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000147                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001778                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016313                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021437                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019418                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.819624                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.819624                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.361591                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.361591                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000147                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001778                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016313                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087053                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.063579                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000147                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001778                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016313                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087053                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.063579                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60908.410790                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62075.942679                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61707.087695                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10669.445878                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10669.445878                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55774.355806                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55774.355806                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60908.410790                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57026.766043                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57352.462103                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60908.410790                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57026.766043                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57352.462103                       # average overall mshr miss latency
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2371075000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2371075000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89026944000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89026944000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000157                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001799                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016291                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021564                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019493                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.820483                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.820483                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.360703                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.360703                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000157                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001799                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016291                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087020                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.063570                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000157                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001799                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016291                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087020                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.063570                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.682435                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62319.324207                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61773.596900                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10666.338594                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10666.338594                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56470.916746                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56470.916746                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.682435                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57640.432338                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57886.896447                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.682435                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57640.432338                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57886.896447                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 813f51271..8539a1890 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.200409                       # Nu
 sim_ticks                                200409284500                       # Number of ticks simulated
 final_tick                               4321214250500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                               22333008                       # Simulator instruction rate (inst/s)
-host_op_rate                                 22332995                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8544906534                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 473604                       # Number of bytes of host memory used
-host_seconds                                    23.45                       # Real time elapsed on the host
+host_inst_rate                               14275836                       # Simulator instruction rate (inst/s)
+host_op_rate                                 14275831                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5462126987                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 513712                       # Number of bytes of host memory used
+host_seconds                                    36.69                       # Real time elapsed on the host
 sim_insts                                   523790075                       # Number of instructions simulated
 sim_ops                                     523790075                       # Number of ops (including micro ops) simulated
 testsys.voltage_domain.voltage                      1                       # Voltage in Volts
@@ -113,6 +113,41 @@ testsys.cpu.num_busy_cycles              20262547.637842                       #
 testsys.cpu.not_idle_fraction                0.050555                       # Percentage of non-idle cycles
 testsys.cpu.idle_fraction                    0.949445                       # Percentage of idle cycles
 testsys.cpu.Branches                          2929848                       # Number of branches fetched
+testsys.cpu.op_class::No_OpClass               712819      3.52%      3.52% # Class of executed instruction
+testsys.cpu.op_class::IntAlu                 12147340     59.95%     63.47% # Class of executed instruction
+testsys.cpu.op_class::IntMult                   21654      0.11%     63.58% # Class of executed instruction
+testsys.cpu.op_class::IntDiv                        0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatAdd                   4653      0.02%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatCmp                      1      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatCvt                      0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatMult                     0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatDiv                    922      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatSqrt                     0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdAdd                       0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdAddAcc                    0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdAlu                       0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdCmp                       0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdCvt                       0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdMisc                      0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdMult                      0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdMultAcc                   0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdShift                     0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdShiftAcc                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdSqrt                      0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAdd                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAlu                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCmp                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCvt                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatDiv                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMisc                 0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMult                 0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMultAcc              0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatSqrt                 0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::MemRead                 4230637     20.88%     84.48% # Class of executed instruction
+testsys.cpu.op_class::MemWrite                2319552     11.45%     95.93% # Class of executed instruction
+testsys.cpu.op_class::IprAccess                824102      4.07%    100.00% # Class of executed instruction
+testsys.cpu.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+testsys.cpu.op_class::total                  20261680                       # Class of executed instruction
 testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
 testsys.cpu.kern.inst.quiesce                   19580                       # number of quiesce instructions executed
 testsys.cpu.kern.inst.hwrei                    153667                       # number of hwrei instructions executed
@@ -336,6 +371,41 @@ drivesys.cpu.num_busy_cycles             19051473.772069                       #
 drivesys.cpu.not_idle_fraction               0.023766                       # Percentage of non-idle cycles
 drivesys.cpu.idle_fraction                   0.976234                       # Percentage of idle cycles
 drivesys.cpu.Branches                         2793313                       # Number of branches fetched
+drivesys.cpu.op_class::No_OpClass              623554      3.27%      3.27% # Class of executed instruction
+drivesys.cpu.op_class::IntAlu                11538630     60.57%     63.84% # Class of executed instruction
+drivesys.cpu.op_class::IntMult                  20663      0.11%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::IntDiv                       0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatAdd                   138      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatCmp                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatCvt                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatMult                    0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatDiv                    23      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatSqrt                    0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdAdd                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdAddAcc                   0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdAlu                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdCmp                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdCvt                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdMisc                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdMult                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdMultAcc                  0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdShift                    0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdShiftAcc                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdSqrt                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatAdd                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatAlu                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatCmp                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatCvt                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatDiv                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMisc                0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMult                0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMultAcc             0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatSqrt                0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::MemRead                4026028     21.13%     85.08% # Class of executed instruction
+drivesys.cpu.op_class::MemWrite               2085021     10.94%     96.02% # Class of executed instruction
+drivesys.cpu.op_class::IprAccess               757336      3.98%    100.00% # Class of executed instruction
+drivesys.cpu.op_class::InstPrefetch                 0      0.00%    100.00% # Class of executed instruction
+drivesys.cpu.op_class::total                 19051393                       # Class of executed instruction
 drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
 drivesys.cpu.kern.inst.quiesce                  19876                       # number of quiesce instructions executed
 drivesys.cpu.kern.inst.hwrei                   143591                       # number of hwrei instructions executed
@@ -455,11 +525,11 @@ sim_seconds                                  0.000407                       # Nu
 sim_ticks                                   407341500                       # Number of ticks simulated
 final_tick                               4321621592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                             6913599452                       # Simulator instruction rate (inst/s)
-host_op_rate                               6911980937                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5373353780                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 524140                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                             7312019890                       # Simulator instruction rate (inst/s)
+host_op_rate                               7310591323                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5683411932                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 513712                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                   523862353                       # Number of instructions simulated
 sim_ops                                     523862353                       # Number of ops (including micro ops) simulated
 testsys.voltage_domain.voltage                      1                       # Voltage in Volts
@@ -561,6 +631,41 @@ testsys.cpu.num_busy_cycles              36406.828108                       # Nu
 testsys.cpu.not_idle_fraction                0.044344                       # Percentage of non-idle cycles
 testsys.cpu.idle_fraction                    0.955656                       # Percentage of idle cycles
 testsys.cpu.Branches                             5238                       # Number of branches fetched
+testsys.cpu.op_class::No_OpClass                 1261      3.49%      3.49% # Class of executed instruction
+testsys.cpu.op_class::IntAlu                    21664     59.97%     63.46% # Class of executed instruction
+testsys.cpu.op_class::IntMult                      44      0.12%     63.58% # Class of executed instruction
+testsys.cpu.op_class::IntDiv                        0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatAdd                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatCmp                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatCvt                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatMult                     0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatDiv                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatSqrt                     0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdAdd                       0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdAddAcc                    0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdAlu                       0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdCmp                       0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdCvt                       0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdMisc                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdMult                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdMultAcc                   0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdShift                     0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdShiftAcc                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdSqrt                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAdd                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAlu                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCmp                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCvt                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatDiv                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMisc                 0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMult                 0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMultAcc              0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatSqrt                 0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::MemRead                    7674     21.24%     84.82% # Class of executed instruction
+testsys.cpu.op_class::MemWrite                   3938     10.90%     95.72% # Class of executed instruction
+testsys.cpu.op_class::IprAccess                  1545      4.28%    100.00% # Class of executed instruction
+testsys.cpu.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+testsys.cpu.op_class::total                     36126                       # Class of executed instruction
 testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
 testsys.cpu.kern.inst.quiesce                      40                       # number of quiesce instructions executed
 testsys.cpu.kern.inst.hwrei                       295                       # number of hwrei instructions executed
@@ -735,6 +840,41 @@ drivesys.cpu.num_busy_cycles             36082.640939                       # Nu
 drivesys.cpu.not_idle_fraction               0.022188                       # Percentage of non-idle cycles
 drivesys.cpu.idle_fraction                   0.977812                       # Percentage of idle cycles
 drivesys.cpu.Branches                            5243                       # Number of branches fetched
+drivesys.cpu.op_class::No_OpClass                1262      3.49%      3.49% # Class of executed instruction
+drivesys.cpu.op_class::IntAlu                   21687     59.99%     63.48% # Class of executed instruction
+drivesys.cpu.op_class::IntMult                     44      0.12%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::IntDiv                       0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::FloatAdd                     0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::FloatCmp                     0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::FloatCvt                     0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::FloatMult                    0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::FloatDiv                     0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::FloatSqrt                    0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdAdd                      0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdAddAcc                   0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdAlu                      0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdCmp                      0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdCvt                      0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdMisc                     0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdMult                     0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdMultAcc                  0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdShift                    0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdShiftAcc                 0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdSqrt                     0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatAdd                 0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatAlu                 0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatCmp                 0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatCvt                 0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatDiv                 0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMisc                0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMult                0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMultAcc             0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatSqrt                0      0.00%     63.60% # Class of executed instruction
+drivesys.cpu.op_class::MemRead                   7678     21.24%     84.84% # Class of executed instruction
+drivesys.cpu.op_class::MemWrite                  3936     10.89%     95.73% # Class of executed instruction
+drivesys.cpu.op_class::IprAccess                 1545      4.27%    100.00% # Class of executed instruction
+drivesys.cpu.op_class::InstPrefetch                 0      0.00%    100.00% # Class of executed instruction
+drivesys.cpu.op_class::total                    36152                       # Class of executed instruction
 drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
 drivesys.cpu.kern.inst.quiesce                     41                       # number of quiesce instructions executed
 drivesys.cpu.kern.inst.hwrei                      295                       # number of hwrei instructions executed
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 0bab63428..a216e15cb 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    25552000                       # Number of ticks simulated
 final_tick                                   25552000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  78801                       # Simulator instruction rate (inst/s)
-host_op_rate                                    78787                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              314994021                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262608                       # Number of bytes of host memory used
+host_inst_rate                                  78387                       # Simulator instruction rate (inst/s)
+host_op_rate                                    78372                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              313333088                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263656                       # Number of bytes of host memory used
 host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
@@ -91,8 +91,8 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       313                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       126                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       127                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,27 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           54                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      317.629630                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     196.201768                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     327.982069                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             16     29.63%     29.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           16     29.63%     59.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            7     12.96%     72.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            4      7.41%     79.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            1      1.85%     81.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            1      1.85%     83.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      3.70%     87.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            7     12.96%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             54                       # Bytes accessed per row activation
-system.physmem.totQLat                        2560250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12605250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           86                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      330.418605                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     204.922237                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     319.300576                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             27     31.40%     31.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           21     24.42%     55.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           10     11.63%     67.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8      9.30%     76.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            1      1.16%     77.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      3.49%     81.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            7      8.14%     89.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      2.33%     91.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            7      8.14%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             86                       # Bytes accessed per row activation
+system.physmem.totQLat                        3845750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12639500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2345000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     7700000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        5458.96                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16417.91                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        8199.89                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26876.87                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  26949.89                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                        1174.70                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                     1174.70                       # Average system read bandwidth in MiByte/s
@@ -223,7 +222,11 @@ system.physmem.readRowHitRate                   80.60                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        54450.96                       # Average gap between requests
 system.physmem.pageHitRate                      80.60                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.05                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.memoryStateTime::IDLE            13500                       # Time in different power states
+system.physmem.memoryStateTime::REF            780000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          22839000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.membus.throughput                   1172197871                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 396                       # Transaction distribution
 system.membus.trans_dist::ReadResp                395                       # Transaction distribution
@@ -237,7 +240,7 @@ system.membus.data_through_bus                  29952                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              560000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4371250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            4371000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             17.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1632                       # Number of BP lookups
@@ -304,9 +307,9 @@ system.cpu.execution_unit.executions             4448                       # Nu
 system.cpu.mult_div_unit.multiplies                 1                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         11596                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         11594                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             469                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled                             467                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           43730                       # Number of cycles cpu's stages were not processed
 system.cpu.runCycles                             7375                       # Number of cycles cpu stages are processed.
 system.cpu.activity                         14.431073                       # Percentage of cycles cpu is active
@@ -343,14 +346,14 @@ system.cpu.stage4.idleCycles                    46641                       # Nu
 system.cpu.stage4.runCycles                      4464                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage4.utilization                8.734957                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           142.169993                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           142.073249                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 560                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               301                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              1.860465                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   142.169993                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.069419                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.069419                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   142.073249                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.069372                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.069372                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          301                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
@@ -369,12 +372,12 @@ system.cpu.icache.demand_misses::cpu.inst          355                       # n
 system.cpu.icache.demand_misses::total            355                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          355                       # number of overall misses
 system.cpu.icache.overall_misses::total           355                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25349750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25349750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25349750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25349750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25349750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25349750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     24875750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     24875750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     24875750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     24875750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     24875750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     24875750                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst          915                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total          915                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst          915                       # number of demand (read+write) accesses
@@ -387,12 +390,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.387978
 system.cpu.icache.demand_miss_rate::total     0.387978                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.387978                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.387978                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71407.746479                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 71407.746479                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 71407.746479                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 71407.746479                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 71407.746479                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 71407.746479                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70072.535211                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70072.535211                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70072.535211                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70072.535211                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70072.535211                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70072.535211                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs           89                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -413,24 +416,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          302
 system.cpu.icache.demand_mshr_misses::total          302                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          302                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21532500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     21532500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21532500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     21532500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21532500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     21532500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21058500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     21058500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21058500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     21058500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21058500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     21058500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.330055                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.330055                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.330055                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.330055                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.330055                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.330055                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71299.668874                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71299.668874                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71299.668874                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71299.668874                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71299.668874                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71299.668874                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69730.132450                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69730.132450                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69730.132450                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69730.132450                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69730.132450                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69730.132450                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.throughput              1174702567                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            397                       # Transaction distribution
@@ -449,19 +452,19 @@ system.cpu.toL2Bus.reqLayer0.occupancy         235000                       # La
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        508000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        274750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        276000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          198.925679                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          198.803908                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              395                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002532                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   142.205920                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    56.719759                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004340                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001731                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006071                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   142.109548                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    56.694360                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004337                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001730                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006067                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          240                       # Occupied blocks per task id
@@ -485,17 +488,17 @@ system.cpu.l2cache.demand_misses::total           469                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          469                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21214000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6927250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     28141250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4931500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4931500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     21214000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11858750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     33072750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     21214000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11858750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     33072750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20740000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7180750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     27920750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5181250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5181250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20740000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     12362000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     33102000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20740000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     12362000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     33102000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          302                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           95                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          397                       # number of ReadReq accesses(hits+misses)
@@ -518,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.997872                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996689                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997872                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70478.405316                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72918.421053                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71063.762626                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67554.794521                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67554.794521                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70478.405316                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70587.797619                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70517.590618                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70478.405316                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70587.797619                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70517.590618                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68903.654485                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75586.842105                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70506.944444                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70976.027397                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70976.027397                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68903.654485                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73583.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70579.957356                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68903.654485                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73583.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70579.957356                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -548,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total          469
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          469                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17443000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5745750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     23188750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4029500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4029500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17443000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9775250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     27218250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17443000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9775250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     27218250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16969500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5998750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     22968250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4278250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4278250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16969500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10277000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     27246500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16969500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10277000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     27246500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997481                       # mshr miss rate for ReadReq accesses
@@ -570,27 +573,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.997872
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997872                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57950.166113                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.578947                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58557.449495                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55198.630137                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55198.630137                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57950.166113                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58186.011905                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58034.648188                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57950.166113                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58186.011905                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58034.648188                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56377.076412                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63144.736842                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58000.631313                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58606.164384                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58606.164384                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56377.076412                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.619048                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58094.882729                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56377.076412                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.619048                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58094.882729                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           103.450623                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse           103.396801                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1601                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              9.529762                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   103.450623                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.025256                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025256                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.396801                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025243                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025243                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
@@ -613,14 +616,14 @@ system.cpu.dcache.demand_misses::cpu.data          447                       # n
 system.cpu.dcache.demand_misses::total            447                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          447                       # number of overall misses
 system.cpu.dcache.overall_misses::total           447                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7371250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7371250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     21672250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     21672250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     29043500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     29043500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     29043500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     29043500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7625750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7625750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     22645250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     22645250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     30271000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     30271000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     30271000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     30271000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1183                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1183                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
@@ -637,19 +640,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.218262
 system.cpu.dcache.demand_miss_rate::total     0.218262                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.218262                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.218262                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75992.268041                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75992.268041                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61920.714286                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61920.714286                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64974.272931                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64974.272931                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64974.272931                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64974.272931                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          487                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78615.979381                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 78615.979381                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64700.714286                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64700.714286                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 67720.357942                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67720.357942                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67720.357942                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67720.357942                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          476                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                26                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    18.730769                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    18.307692                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -669,14 +672,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          168
 system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7028750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7028750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5009000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5009000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12037750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12037750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12037750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12037750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7282250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7282250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5258750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5258750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12541000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     12541000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12541000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     12541000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
@@ -685,14 +688,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.082031
 system.cpu.dcache.demand_mshr_miss_rate::total     0.082031                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.082031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73986.842105                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73986.842105                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68616.438356                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68616.438356                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71653.273810                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71653.273810                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71653.273810                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71653.273810                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76655.263158                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76655.263158                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72037.671233                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72037.671233                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74648.809524                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74648.809524                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74648.809524                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74648.809524                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 8bfd28333..33f9c5fe9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    21078000                       # Number of ticks simulated
-final_tick                                   21078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21025000                       # Number of ticks simulated
+final_tick                                   21025000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72140                       # Simulator instruction rate (inst/s)
-host_op_rate                                    72127                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              238549554                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265696                       # Number of bytes of host memory used
+host_inst_rate                                  72274                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72262                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              238397605                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265716                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6372                       # Number of instructions simulated
 sim_ops                                          6372                       # Number of ops (including micro ops) simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           20032                       # Nu
 system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                174                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   487                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            950374798                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            528323370                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1478698169                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       950374798                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          950374798                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           950374798                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           528323370                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1478698169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            952770511                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            529655172                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1482425684                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       952770511                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          952770511                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           952770511                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           529655172                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1482425684                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           488                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         488                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21045000                       # Total gap between requests
+system.physmem.totGap                        20992000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       275                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       146                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        48                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        50                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           61                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      328.393443                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     194.167058                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     347.898610                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             21     34.43%     34.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           16     26.23%     60.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            6      9.84%     70.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            4      6.56%     77.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      4.92%     81.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.64%     83.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     16.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             61                       # Bytes accessed per row activation
-system.physmem.totQLat                        3243750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13328750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           79                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      351.594937                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     224.218426                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.360278                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             21     26.58%     26.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           19     24.05%     50.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           11     13.92%     64.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8     10.13%     74.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            5      6.33%     81.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      1.27%     82.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      2.53%     84.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      2.53%     87.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     12.66%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             79                       # Bytes accessed per row activation
+system.physmem.totQLat                        4394750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13544750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2440000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     7645000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6647.03                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15665.98                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        9005.64                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27313.01                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1481.73                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27755.64                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1485.47                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1481.73                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1485.47                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.58                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.58                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.61                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.61                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.72                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.73                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        394                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   80.74                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43125.00                       # Average gap between requests
+system.physmem.avgGap                        43016.39                       # Average gap between requests
 system.physmem.pageHitRate                      80.74                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.10                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1478698169                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE            22000                       # Time in different power states
+system.physmem.memoryStateTime::REF            520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15304250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1482425684                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 415                       # Transaction distribution
 system.membus.trans_dist::ReadResp                414                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
@@ -234,10 +238,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               31168                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  31168                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              617000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              618500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4550500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4556750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             21.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2894                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1702                       # Number of conditional branches predicted
@@ -252,22 +256,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         2078                       # DTB read hits
+system.cpu.dtb.read_hits                         2077                       # DTB read hits
 system.cpu.dtb.read_misses                         47                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     2125                       # DTB read accesses
+system.cpu.dtb.read_accesses                     2124                       # DTB read accesses
 system.cpu.dtb.write_hits                        1062                       # DTB write hits
 system.cpu.dtb.write_misses                        31                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                    1093                       # DTB write accesses
-system.cpu.dtb.data_hits                         3140                       # DTB hits
+system.cpu.dtb.data_hits                         3139                       # DTB hits
 system.cpu.dtb.data_misses                         78                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     3218                       # DTB accesses
-system.cpu.itb.fetch_hits                        2388                       # ITB hits
+system.cpu.dtb.data_accesses                     3217                       # DTB accesses
+system.cpu.itb.fetch_hits                        2387                       # ITB hits
 system.cpu.itb.fetch_misses                        39                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2427                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2426                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -281,95 +285,95 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            42157                       # number of cpu cycles simulated
+system.cpu.numCycles                            42051                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8510                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          16605                       # Number of instructions fetch has processed
+system.cpu.fetch.icacheStallCycles               8515                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          16590                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        2894                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches               1172                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2970                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles                          2968                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    1911                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1405                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles                   1438                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           747                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2388                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   385                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14964                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.109663                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.506678                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      2387                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   384                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              15000                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.106000                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.503194                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11994     80.15%     80.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      318      2.13%     82.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      234      1.56%     83.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      214      1.43%     85.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      255      1.70%     86.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      241      1.61%     88.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      264      1.76%     90.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      184      1.23%     91.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1260      8.42%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    12032     80.21%     80.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      318      2.12%     82.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      234      1.56%     83.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      214      1.43%     85.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      255      1.70%     87.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      241      1.61%     88.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      264      1.76%     90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      183      1.22%     91.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1259      8.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14964                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.068648                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.393885                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     9327                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1567                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2770                       # Number of cycles decode is running
+system.cpu.fetch.rateDist::total                15000                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.068821                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.394521                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     9332                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1599                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2769                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    74                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                   1226                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  243                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    86                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  15343                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  15335                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   223                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                   1226                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     9537                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     678                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            554                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2628                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   341                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  14637                       # Number of instructions processed by rename
+system.cpu.rename.IdleCycles                     9542                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     708                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            553                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2627                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   344                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  14630                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                    10                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                      5                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   297                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               10979                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 18262                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            18253                       # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents                   301                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               10973                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 18255                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            18246                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 8                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4570                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6409                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     6403                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 30                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             24                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       843                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2769                       # Number of loads inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       874                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2768                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1356                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 3                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      12974                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      12973                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  29                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     10780                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                     10779                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                56                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            6201                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3614                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            6200                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3613                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14964                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.720396                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.363744                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         15000                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.718600                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.361398                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10463     69.92%     69.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1623     10.85%     80.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1158      7.74%     88.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 756      5.05%     93.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 501      3.35%     96.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 270      1.80%     98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 146      0.98%     99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10485     69.90%     69.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1646     10.97%     80.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1153      7.69%     88.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 753      5.02%     93.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 501      3.34%     96.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 269      1.79%     98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 146      0.97%     99.69% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  33      0.22%     99.91% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  14      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14964                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           15000                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                      14     12.50%     12.50% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     12.50% # attempts to use FU when none available
@@ -405,7 +409,7 @@ system.cpu.iq.fu_full::MemWrite                    38     33.93%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7243     67.19%     67.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7243     67.20%     67.21% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.22% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.22% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.24% # Type of FU issued
@@ -434,39 +438,39 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.24% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.24% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.24% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2399     22.25%     89.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2398     22.25%     89.49% # Type of FU issued
 system.cpu.iq.FU_type_0::MemWrite                1133     10.51%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10780                       # Type of FU issued
-system.cpu.iq.rate                           0.255711                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                  10779                       # Type of FU issued
+system.cpu.iq.rate                           0.256332                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         112                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010390                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              36671                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             19208                       # Number of integer instruction queue writes
+system.cpu.iq.fu_busy_rate                   0.010391                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              36705                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             19206                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses         9602                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  10879                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  10878                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               73                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1586                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1585                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
 system.cpu.iew.lsq.thread0.squashedStores          491                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           127                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked           132                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                   1226                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                     247                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    13                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               13092                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts               13091                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts               175                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2769                       # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts                  2768                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1356                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 29                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
@@ -475,43 +479,43 @@ system.cpu.iew.memOrderViolationEvents             16                       # Nu
 system.cpu.iew.predictedTakenIncorrect            122                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          382                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  504                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 10072                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2136                       # Number of load instructions executed
+system.cpu.iew.iewExecutedInsts                 10071                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2135                       # Number of load instructions executed
 system.cpu.iew.iewExecSquashedInsts               708                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            89                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3231                       # number of memory reference insts executed
+system.cpu.iew.exec_refs                         3230                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1589                       # Number of branches executed
 system.cpu.iew.exec_stores                       1095                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.238916                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.239495                       # Inst execution rate
 system.cpu.iew.wb_sent                           9755                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                          9612                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      5080                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6838                       # num instructions consuming a value
+system.cpu.iew.wb_producers                      5069                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6811                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.228005                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.742907                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.228580                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.744237                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            6701                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            6700                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               431                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13738                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.465060                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.277866                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        13774                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.463845                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.273398                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10960     79.78%     79.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1479     10.77%     90.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          519      3.78%     94.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          236      1.72%     96.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          157      1.14%     97.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          106      0.77%     97.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          104      0.76%     98.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           34      0.25%     98.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10981     79.72%     79.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1489     10.81%     90.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          532      3.86%     94.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          235      1.71%     96.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          155      1.13%     97.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          100      0.73%     97.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          106      0.77%     98.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           33      0.24%     98.96% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8          143      1.04%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13738                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13774                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 6389                       # Number of instructions committed
 system.cpu.commit.committedOps                   6389                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -522,26 +526,61 @@ system.cpu.commit.branches                       1050                       # Nu
 system.cpu.commit.fp_insts                         10                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      6307                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  127                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass           19      0.30%      0.30% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             4319     67.60%     67.90% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               1      0.02%     67.91% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.91% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              2      0.03%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            1183     18.52%     86.46% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            865     13.54%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total              6389                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   143                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        26334                       # The number of ROB reads
-system.cpu.rob.rob_writes                       27415                       # The number of ROB writes
+system.cpu.rob.rob_reads                        26369                       # The number of ROB reads
+system.cpu.rob.rob_writes                       27413                       # The number of ROB writes
 system.cpu.timesIdled                             272                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           27193                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           27051                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        6372                       # Number of Instructions Simulated
 system.cpu.committedOps                          6372                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  6372                       # Number of Instructions Simulated
-system.cpu.cpi                               6.615976                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.615976                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.151149                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.151149                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    12785                       # number of integer regfile reads
+system.cpu.cpi                               6.599341                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.599341                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.151530                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.151530                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    12784                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    7268                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1481734510                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1485469679                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            416                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           415                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
@@ -556,61 +595,61 @@ system.cpu.toL2Bus.data_through_bus             31232                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         244500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        528000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        529000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        276000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        278250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           159.411930                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1899                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           159.423717                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1898                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               314                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.047771                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.044586                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   159.411930                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.077838                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.077838                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   159.423717                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.077844                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.077844                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.153320                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              5090                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             5090                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1899                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1899                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1899                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1899                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1899                       # number of overall hits
-system.cpu.icache.overall_hits::total            1899                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              5088                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5088                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1898                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1898                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1898                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1898                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1898                       # number of overall hits
+system.cpu.icache.overall_hits::total            1898                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          489                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           489                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          489                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            489                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          489                       # number of overall misses
 system.cpu.icache.overall_misses::total           489                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31431750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31431750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31431750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31431750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31431750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31431750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2388                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2388                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2388                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2388                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2388                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2388                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.204774                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.204774                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.204774                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.204774                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.204774                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.204774                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64277.607362                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64277.607362                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64277.607362                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64277.607362                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64277.607362                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64277.607362                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     31330250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     31330250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     31330250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     31330250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     31330250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     31330250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2387                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2387                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2387                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2387                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2387                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2387                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.204860                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.204860                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.204860                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.204860                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.204860                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.204860                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 64070.040900                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 64070.040900                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -631,34 +670,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          315
 system.cpu.icache.demand_mshr_misses::total          315                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          315                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          315                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22098000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22098000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22098000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22098000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22098000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22098000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.131910                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.131910                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.131910                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.131910                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.131910                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.131910                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70152.380952                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70152.380952                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70152.380952                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70152.380952                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70152.380952                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70152.380952                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22016000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22016000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22016000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22016000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22016000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22016000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.131965                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.131965                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.131965                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.131965                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.131965                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.131965                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          219.244506                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          219.258059                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              414                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   159.494883                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    59.749622                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004867                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   159.507047                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    59.751013                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004868                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001823                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.006691                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          414                       # Occupied blocks per task id
@@ -684,17 +723,17 @@ system.cpu.l2cache.demand_misses::total           488                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          314                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          174                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          488                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21772000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7725500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     29497500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5467500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5467500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     21772000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     13193000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     34965000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     21772000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     13193000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     34965000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21690000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7718000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     29408000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5717750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5717750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     21690000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     13435750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     35125750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     21690000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     13435750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     35125750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          315                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          101                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          416                       # number of ReadReq accesses(hits+misses)
@@ -717,17 +756,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.997955                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996825                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997955                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69337.579618                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76490.099010                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.313253                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74897.260274                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74897.260274                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69337.579618                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75821.839080                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71649.590164                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69337.579618                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75821.839080                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71649.590164                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -747,17 +786,17 @@ system.cpu.l2cache.demand_mshr_misses::total          488
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          314                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          488                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17823000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6485500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24308500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4573000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4573000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17823000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11058500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     28881500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17823000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11058500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     28881500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17737500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6477000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24214500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4818250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4818250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17737500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11295250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     29032750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17737500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11295250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     29032750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997596                       # mshr miss rate for ReadReq accesses
@@ -769,41 +808,41 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.997955
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997955                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56761.146497                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64212.871287                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58574.698795                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62643.835616                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62643.835616                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56761.146497                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63554.597701                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59183.401639                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56761.146497                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63554.597701                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59183.401639                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58348.192771                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66003.424658                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66003.424658                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56488.853503                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64915.229885                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59493.340164                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56488.853503                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64915.229885                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59493.340164                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           107.267771                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2230                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           107.231811                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2229                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               174                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.816092                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.810345                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   107.267771                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.026188                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.026188                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   107.231811                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.026180                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.026180                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          174                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.042480                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5694                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5694                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1724                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1724                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              5692                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5692                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1723                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1723                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            506                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2230                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2230                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2230                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2230                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          2229                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2229                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2229                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2229                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          171                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           171                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          359                       # number of WriteReq misses
@@ -812,43 +851,43 @@ system.cpu.dcache.demand_misses::cpu.data          530                       # n
 system.cpu.dcache.demand_misses::total            530                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          530                       # number of overall misses
 system.cpu.dcache.overall_misses::total           530                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11467500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11467500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     23223733                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     23223733                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     34691233                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     34691233                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     34691233                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     34691233                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1895                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1895                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11460500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11460500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     25449978                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     25449978                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     36910478                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     36910478                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     36910478                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     36910478                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1894                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1894                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2760                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2760                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2760                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2760                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.090237                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.090237                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2759                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2759                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2759                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2759                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.090285                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.090285                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.192029                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.192029                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.192029                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.192029                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65455.156604                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65455.156604                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1533                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.192099                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.192099                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.192099                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.192099                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69642.411321                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69642.411321                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1529                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                29                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                34                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    52.862069                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    44.970588                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -868,30 +907,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          174
 system.cpu.dcache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          174                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7915000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7915000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5462500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5462500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13377500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     13377500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13377500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     13377500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053826                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053826                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7907500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7907500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5712750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5712750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13620250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     13620250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13620250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     13620250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053854                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053854                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063043                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.063043                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063043                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.063043                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063066                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.063066                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063066                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.063066                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 53f3ae2a8..60119bd53 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     3208000                       # Number of ticks simulated
 final_tick                                    3208000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 105446                       # Simulator instruction rate (inst/s)
-host_op_rate                                   105415                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52907298                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 268408                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                 172950                       # Simulator instruction rate (inst/s)
+host_op_rate                                   172880                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               86758979                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253924                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -95,5 +95,40 @@ system.cpu.num_busy_cycles                       6417                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      4320     67.50%     67.80% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.02%     67.81% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.81% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1190     18.59%     86.44% # Class of executed instruction
+system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       6400                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
index 913b33750..351b1338b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000139                       # Nu
 sim_ticks                                      138616                       # Number of ticks simulated
 final_tick                                     138616                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  14698                       # Simulator instruction rate (inst/s)
-host_op_rate                                    14697                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 318804                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 174728                       # Number of bytes of host memory used
-host_seconds                                     0.43                       # Real time elapsed on the host
+host_inst_rate                                  36011                       # Simulator instruction rate (inst/s)
+host_op_rate                                    36008                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 781041                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 161164                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -210,6 +210,41 @@ system.cpu.num_busy_cycles                     138616                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      4320     67.50%     67.80% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.02%     67.81% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.81% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1190     18.59%     86.44% # Class of executed instruction
+system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       6400                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.369871                      
 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0         1041                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1         1490                      
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index f70111f0d..a76851914 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000118                       # Nu
 sim_ticks                                      117611                       # Number of ticks simulated
 final_tick                                     117611                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  21881                       # Simulator instruction rate (inst/s)
-host_op_rate                                    21879                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 402676                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 177980                       # Number of bytes of host memory used
-host_seconds                                     0.29                       # Real time elapsed on the host
+host_inst_rate                                  31716                       # Simulator instruction rate (inst/s)
+host_op_rate                                    31714                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 583663                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 164416                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -200,6 +200,41 @@ system.cpu.num_busy_cycles                     117611                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      4320     67.50%     67.80% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.02%     67.81% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.81% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1190     18.59%     86.44% # Class of executed instruction
+system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       6400                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.786874                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2         1109                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2          253                      
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index e6916bab3..706264b43 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000114                       # Nu
 sim_ticks                                      113627                       # Number of ticks simulated
 final_tick                                     113627                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  28822                       # Simulator instruction rate (inst/s)
-host_op_rate                                    28819                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 512426                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 175880                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
+host_inst_rate                                  50343                       # Simulator instruction rate (inst/s)
+host_op_rate                                    50337                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 894983                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 161272                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -186,6 +186,41 @@ system.cpu.num_busy_cycles                     113627                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      4320     67.50%     67.80% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.02%     67.81% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.81% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1190     18.59%     86.44% # Class of executed instruction
+system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       6400                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.473611                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1178                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4          204                      
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 66f09eeb4..29b31fb1d 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000093                       # Nu
 sim_ticks                                       93341                       # Number of ticks simulated
 final_tick                                      93341                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  31508                       # Simulator instruction rate (inst/s)
-host_op_rate                                    31505                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 460155                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 175808                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  52665                       # Simulator instruction rate (inst/s)
+host_op_rate                                    52659                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 769125                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 161200                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -185,6 +185,41 @@ system.cpu.num_busy_cycles                      93341                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      4320     67.50%     67.80% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.02%     67.81% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.81% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1190     18.59%     86.44% # Class of executed instruction
+system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       6400                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     6.199848                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1159                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1143                      
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index d0515d3c9..17ffa2150 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000144                       # Nu
 sim_ticks                                      143853                       # Number of ticks simulated
 final_tick                                     143853                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  14935                       # Simulator instruction rate (inst/s)
-host_op_rate                                    14935                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 336198                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 174340                       # Number of bytes of host memory used
-host_seconds                                     0.43                       # Real time elapsed on the host
+host_inst_rate                                  53676                       # Simulator instruction rate (inst/s)
+host_op_rate                                    53669                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1208067                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 160752                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -160,6 +160,41 @@ system.cpu.num_busy_cycles                     143853                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      4320     67.50%     67.80% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.02%     67.81% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.81% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1190     18.59%     86.44% # Class of executed instruction
+system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       6400                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     6.011692                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1730                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1726                      
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 72bd7571c..e6ec389d1 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000033                       # Nu
 sim_ticks                                    32544000                       # Number of ticks simulated
 final_tick                                   32544000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 163681                       # Simulator instruction rate (inst/s)
-host_op_rate                                   163603                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              832819326                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277116                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                 550056                       # Simulator instruction rate (inst/s)
+host_op_rate                                   549394                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2794675827                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262632                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -101,6 +101,41 @@ system.cpu.num_busy_cycles                      65088                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1050                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      4320     67.50%     67.80% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.02%     67.81% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.81% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.84% # Class of executed instruction
+system.cpu.op_class::MemRead                     1190     18.59%     86.44% # Class of executed instruction
+system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       6400                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           127.998991                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6122                       # Total number of references to valid blocks.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 88231a1ee..5be5fa9ed 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    12006500                       # Number of ticks simulated
-final_tick                                   12006500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    11975500                       # Number of ticks simulated
+final_tick                                   11975500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60243                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60220                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              302796832                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264400                       # Number of bytes of host memory used
+host_inst_rate                                  56599                       # Simulator instruction rate (inst/s)
+host_op_rate                                    56579                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              283759448                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265424                       # Number of bytes of host memory used
 host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           12032                       # Nu
 system.physmem.num_reads::cpu.inst                188                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   273                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1002123850                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            453087911                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1455211760                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1002123850                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1002123850                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1002123850                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           453087911                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1455211760                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1004717966                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            454260782                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1458978748                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1004717966                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1004717966                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1004717966                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           454260782                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1458978748                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           273                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         273                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        11917000                       # Total gap between requests
+system.physmem.totGap                        11886000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       159                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       158                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        84                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        25                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,33 +186,33 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           24                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean             464                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     290.487911                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     387.347726                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127              6     25.00%     25.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255            4     16.67%     41.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            3     12.50%     54.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            1      4.17%     58.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      8.33%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      8.33%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            6     25.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             24                       # Bytes accessed per row activation
-system.physmem.totQLat                        1638000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7265500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           38                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      387.368421                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     224.223359                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     366.580725                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             14     36.84%     36.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            5     13.16%     50.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            4     10.53%     60.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            2      5.26%     65.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      5.26%     71.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      5.26%     76.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      5.26%     81.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      2.63%     84.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            6     15.79%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             38                       # Bytes accessed per row activation
+system.physmem.totQLat                        2067500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   7186250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1365000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     4262500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6000.00                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15613.55                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        7573.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26613.55                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1455.21                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26323.26                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1458.98                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1455.21                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1458.98                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.37                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.37                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.40                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.40                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -220,10 +220,14 @@ system.physmem.readRowHits                        225                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.42                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43652.01                       # Average gap between requests
+system.physmem.avgGap                        43538.46                       # Average gap between requests
 system.physmem.pageHitRate                      82.42                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.18                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1455211760                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE            22000                       # Time in different power states
+system.physmem.memoryStateTime::REF            260000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT           7796750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1458978748                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 249                       # Transaction distribution
 system.membus.trans_dist::ReadResp                249                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                24                       # Transaction distribution
@@ -234,9 +238,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               17472                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  17472                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              344000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              344500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2552500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2556250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             21.3                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1176                       # Number of BP lookups
@@ -281,42 +285,42 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            24014                       # number of cpu cycles simulated
+system.cpu.numCycles                            23952                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               4349                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               4342                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                           7011                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        1176                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                465                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          1209                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                     869                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    541                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles                    531                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   18                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          1022                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
 system.cpu.fetch.CacheLines                      1065                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   187                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples               7722                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.907925                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.314691                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples               7705                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.909929                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.316850                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     6513     84.34%     84.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                       53      0.69%     85.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      115      1.49%     86.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                       95      1.23%     87.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      176      2.28%     90.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       76      0.98%     91.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       64      0.83%     91.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                       65      0.84%     92.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      565      7.32%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     6496     84.31%     84.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                       53      0.69%     85.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      115      1.49%     86.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                       95      1.23%     87.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      176      2.28%     90.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       76      0.99%     90.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       64      0.83%     91.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                       65      0.84%     92.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      565      7.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                 7722                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.048971                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.291955                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     5487                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   579                       # Number of cycles decode is blocked
+system.cpu.fetch.rateDist::total                 7705                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.049098                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.292710                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     5480                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   569                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      1153                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                     9                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    494                       # Number of cycles decode is squashing
@@ -325,9 +329,9 @@ system.cpu.decode.BranchMispred                    81                       # Nu
 system.cpu.decode.DecodedInsts                   6199                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   292                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    494                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     5585                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                     5578                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     254                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            290                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles            280                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      1063                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                    36                       # Number of cycles rename is unblocking
 system.cpu.rename.RenamedInsts                   5900                       # Number of instructions processed by rename
@@ -354,23 +358,23 @@ system.cpu.iq.iqSquashedInstsIssued                54                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            2341                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined         1389                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples          7722                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.523828                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.238657                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples          7705                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.524984                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.239779                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                6098     78.97%     78.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 565      7.32%     86.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 401      5.19%     91.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 263      3.41%     94.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 200      2.59%     97.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 120      1.55%     99.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                6081     78.92%     78.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 565      7.33%     86.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 401      5.20%     91.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 263      3.41%     94.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 200      2.60%     97.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 120      1.56%     99.03% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                  47      0.61%     99.64% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  17      0.22%     99.86% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  11      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total            7722                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total            7705                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       3      6.82%      6.82% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      6.82% # attempts to use FU when none available
@@ -440,10 +444,10 @@ system.cpu.iq.FU_type_0::MemWrite                 395      9.77%    100.00% # Ty
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                   4045                       # Type of FU issued
-system.cpu.iq.rate                           0.168443                       # Inst issue rate
+system.cpu.iq.rate                           0.168879                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                          44                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.010878                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              15897                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads              15880                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes              7311                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses         3652                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
@@ -484,26 +488,26 @@ system.cpu.iew.exec_nop                           336                       # nu
 system.cpu.iew.exec_refs                         1130                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                      644                       # Number of branches executed
 system.cpu.iew.exec_stores                        388                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.160531                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.160947                       # Inst execution rate
 system.cpu.iew.wb_sent                           3738                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                          3658                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                      1710                       # num instructions producing a value
 system.cpu.iew.wb_consumers                      2211                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.152328                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       0.152722                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.773406                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts            2726                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               180                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples         7228                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.356392                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.198445                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples         7211                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.357232                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.199732                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         6359     87.98%     87.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          204      2.82%     90.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          308      4.26%     95.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          114      1.58%     96.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         6342     87.95%     87.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          204      2.83%     90.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          308      4.27%     95.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          114      1.58%     96.63% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::4           72      1.00%     97.63% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::5           51      0.71%     98.34% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6           32      0.44%     98.78% # Number of insts commited each cycle
@@ -512,7 +516,7 @@ system.cpu.commit.committed_per_cycle::8           63      0.87%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total         7228                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         7211                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 2576                       # Number of instructions committed
 system.cpu.commit.committedOps                   2576                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -523,25 +527,60 @@ system.cpu.commit.branches                        396                       # Nu
 system.cpu.commit.fp_insts                          6                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      2367                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   71                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass          189      7.34%      7.34% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             1677     65.10%     72.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               1      0.04%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead             415     16.11%     88.59% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            294     11.41%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total              2576                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                    63                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        12220                       # The number of ROB reads
+system.cpu.rob.rob_reads                        12203                       # The number of ROB reads
 system.cpu.rob.rob_writes                       11111                       # The number of ROB writes
-system.cpu.timesIdled                             158                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           16292                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                             157                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           16247                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedOps                          2387                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  2387                       # Number of Instructions Simulated
-system.cpu.cpi                              10.060327                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                        10.060327                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.099400                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.099400                       # IPC: Total IPC of All Threads
+system.cpu.cpi                              10.034353                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                        10.034353                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.099658                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.099658                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                     4672                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    2825                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1455211760                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1458978748                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            249                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           249                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           24                       # Transaction distribution
@@ -556,19 +595,19 @@ system.cpu.toL2Bus.data_through_bus             17472                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         136500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        315500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        316750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        133000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        133500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse            93.163170                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse            93.052511                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 815                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               188                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              4.335106                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    93.163170                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.045490                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.045490                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst    93.052511                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.045436                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.045436                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          188                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
@@ -587,12 +626,12 @@ system.cpu.icache.demand_misses::cpu.inst          250                       # n
 system.cpu.icache.demand_misses::total            250                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          250                       # number of overall misses
 system.cpu.icache.overall_misses::total           250                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     17591499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     17591499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     17591499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     17591499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     17591499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     17591499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     17506249                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     17506249                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     17506249                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     17506249                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     17506249                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     17506249                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1065                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1065                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1065                       # number of demand (read+write) accesses
@@ -605,12 +644,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.234742
 system.cpu.icache.demand_miss_rate::total     0.234742                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.234742                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.234742                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70365.996000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70365.996000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70365.996000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70365.996000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70365.996000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70365.996000                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70024.996000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70024.996000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70024.996000                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70024.996000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70024.996000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70024.996000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          112                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
@@ -631,36 +670,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          188
 system.cpu.icache.demand_mshr_misses::total          188                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          188                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          188                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13162249                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     13162249                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13162249                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     13162249                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13162249                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     13162249                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13110499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     13110499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13110499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     13110499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13110499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     13110499                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.176526                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.176526                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.176526                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.176526                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.176526                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.176526                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70011.962766                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70011.962766                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70011.962766                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70011.962766                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70011.962766                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70011.962766                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69736.696809                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69736.696809                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69736.696809                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69736.696809                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69736.696809                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69736.696809                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          122.028433                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          121.888429                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              249                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    93.360563                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    28.667870                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002849                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000875                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.003724                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    93.250749                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    28.637680                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002846                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000874                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.003720                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          249                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          211                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
@@ -678,17 +717,17 @@ system.cpu.l2cache.demand_misses::total           273                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          188                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          273                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12973500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4680750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     17654250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1693750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1693750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     12973500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6374500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     19348000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     12973500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6374500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     19348000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12921750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4652500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     17574250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1688000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1688000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     12921750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6340500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     19262250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     12921750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6340500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     19262250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          188                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           61                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          249                       # number of ReadReq accesses(hits+misses)
@@ -711,17 +750,17 @@ system.cpu.l2cache.demand_miss_rate::total            1                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69007.978723                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76733.606557                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70900.602410                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70572.916667                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70572.916667                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69007.978723                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74994.117647                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70871.794872                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69007.978723                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74994.117647                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70871.794872                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68732.712766                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76270.491803                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70579.317269                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68732.712766                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74594.117647                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70557.692308                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68732.712766                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74594.117647                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70557.692308                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -741,17 +780,17 @@ system.cpu.l2cache.demand_mshr_misses::total          273
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          188                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          273                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10603500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3934250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14537750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1399750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1399750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10603500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5334000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     15937500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10603500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5334000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     15937500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10547750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3905000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14452750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1393500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1393500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10547750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5298500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15846250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10547750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5298500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15846250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -763,30 +802,30 @@ system.cpu.l2cache.demand_mshr_miss_rate::total            1
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56401.595745                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64495.901639                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58384.538153                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58322.916667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58322.916667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56401.595745                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62752.941176                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58379.120879                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56401.595745                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62752.941176                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58379.120879                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56105.053191                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64016.393443                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58043.172691                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58062.500000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58062.500000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56105.053191                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62335.294118                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58044.871795                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56105.053191                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62335.294118                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            45.630537                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            45.583444                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                 759                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              8.929412                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    45.630537                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011140                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011140                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    45.583444                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011129                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011129                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              1995                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             1995                       # Number of data accesses
@@ -806,14 +845,14 @@ system.cpu.dcache.demand_misses::cpu.data          196                       # n
 system.cpu.dcache.demand_misses::total            196                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          196                       # number of overall misses
 system.cpu.dcache.overall_misses::total           196                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7964000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7964000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5323250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5323250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     13287250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     13287250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     13287250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     13287250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7876750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7876750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5302250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5302250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     13179000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     13179000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     13179000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     13179000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          661                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          661                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
@@ -830,14 +869,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.205236
 system.cpu.dcache.demand_miss_rate::total     0.205236                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.205236                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.205236                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69252.173913                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69252.173913                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65719.135802                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65719.135802                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67792.091837                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67792.091837                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67792.091837                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67792.091837                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65459.876543                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 67239.795918                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67239.795918                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67239.795918                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67239.795918                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          145                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
@@ -862,14 +901,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4741750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4741750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1719250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1719250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6461000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6461000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6461000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6461000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4713500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4713500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1713500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1713500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6427000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6427000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6427000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6427000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.092284                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.092284                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
@@ -878,14 +917,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.089005
 system.cpu.dcache.demand_mshr_miss_rate::total     0.089005                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.089005                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.089005                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77733.606557                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77733.606557                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71635.416667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71635.416667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76011.764706                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76011.764706                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76011.764706                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76011.764706                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77270.491803                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77270.491803                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75611.764706                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75611.764706                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75611.764706                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75611.764706                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index 2cd66ec8a..6080ce665 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000001                       # Nu
 sim_ticks                                     1297500                       # Number of ticks simulated
 final_tick                                    1297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59390                       # Simulator instruction rate (inst/s)
-host_op_rate                                    59366                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               29878318                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267100                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                 741583                       # Simulator instruction rate (inst/s)
+host_op_rate                                   738395                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              370291096                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253628                       # Number of bytes of host memory used
+host_seconds                                     0.00                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -95,5 +95,40 @@ system.cpu.num_busy_cycles                       2596                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   189      7.31%      7.31% # Class of executed instruction
+system.cpu.op_class::IntAlu                      1678     64.91%     72.22% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.04%     72.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::MemRead                      419     16.21%     88.47% # Class of executed instruction
+system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       2585                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
index 944c5b9f4..d01144a54 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000053                       # Nu
 sim_ticks                                       52548                       # Number of ticks simulated
 final_tick                                      52548                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  15623                       # Simulator instruction rate (inst/s)
-host_op_rate                                    15622                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 318507                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 173288                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  36298                       # Simulator instruction rate (inst/s)
+host_op_rate                                    36291                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 739863                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 159844                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -209,6 +209,41 @@ system.cpu.num_busy_cycles                      52548                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   189      7.31%      7.31% # Class of executed instruction
+system.cpu.op_class::IntAlu                      1678     64.91%     72.22% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.04%     72.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::MemRead                      419     16.21%     88.47% # Class of executed instruction
+system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.426467                      
 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0          431                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1          572                      
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 215db9928..99c36fa52 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000045                       # Nu
 sim_ticks                                       44968                       # Number of ticks simulated
 final_tick                                      44968                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  18935                       # Simulator instruction rate (inst/s)
-host_op_rate                                    18932                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 330302                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 175652                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                  32543                       # Simulator instruction rate (inst/s)
+host_op_rate                                    32537                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 567670                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 162088                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -200,6 +200,41 @@ system.cpu.num_busy_cycles                      44968                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   189      7.31%      7.31% # Class of executed instruction
+system.cpu.op_class::IntAlu                      1678     64.91%     72.22% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.04%     72.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::MemRead                      419     16.21%     88.47% # Class of executed instruction
+system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.661804                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2          423                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2           87                      
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index eecde778c..c5b73657d 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000043                       # Nu
 sim_ticks                                       43073                       # Number of ticks simulated
 final_tick                                      43073                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  22164                       # Simulator instruction rate (inst/s)
-host_op_rate                                    22160                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 370326                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 173416                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_inst_rate                                  51660                       # Simulator instruction rate (inst/s)
+host_op_rate                                    51645                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 862979                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 159984                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -186,6 +186,41 @@ system.cpu.num_busy_cycles                      43073                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   189      7.31%      7.31% # Class of executed instruction
+system.cpu.op_class::IntAlu                      1678     64.91%     72.22% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.04%     72.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::MemRead                      419     16.21%     88.47% # Class of executed instruction
+system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.412904                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          448                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4           70                      
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 293fb7685..3c031887e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000035                       # Nu
 sim_ticks                                       35432                       # Number of ticks simulated
 final_tick                                      35432                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  22204                       # Simulator instruction rate (inst/s)
-host_op_rate                                    22201                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 305145                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 174496                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_inst_rate                                  51262                       # Simulator instruction rate (inst/s)
+host_op_rate                                    51245                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 704386                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 159904                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -184,6 +184,41 @@ system.cpu.num_busy_cycles                      35432                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   189      7.31%      7.31% # Class of executed instruction
+system.cpu.op_class::IntAlu                      1678     64.91%     72.22% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.04%     72.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::MemRead                      419     16.21%     88.47% # Class of executed instruction
+system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     6.200610                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          441                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          425                      
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 8be4f5dad..c9a4a26c5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000052                       # Nu
 sim_ticks                                       52498                       # Number of ticks simulated
 final_tick                                      52498                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  10658                       # Simulator instruction rate (inst/s)
-host_op_rate                                    10657                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 217095                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 172908                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
+host_inst_rate                                  55191                       # Simulator instruction rate (inst/s)
+host_op_rate                                    55175                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1123673                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 158428                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -159,6 +159,41 @@ system.cpu.num_busy_cycles                      52498                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   189      7.31%      7.31% # Class of executed instruction
+system.cpu.op_class::IntAlu                      1678     64.91%     72.22% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.04%     72.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::MemRead                      419     16.21%     88.47% # Class of executed instruction
+system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.958322                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          626                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          622                      
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 4ab5ef724..3ccccfd43 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    16524000                       # Number of ticks simulated
 final_tick                                   16524000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  56666                       # Simulator instruction rate (inst/s)
-host_op_rate                                    56644                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              363064230                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275808                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 366311                       # Simulator instruction rate (inst/s)
+host_op_rate                                   365532                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2339184598                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262348                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -101,6 +101,41 @@ system.cpu.num_busy_cycles                      33048                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   189      7.31%      7.31% # Class of executed instruction
+system.cpu.op_class::IntAlu                      1678     64.91%     72.22% # Class of executed instruction
+system.cpu.op_class::IntMult                        1      0.04%     72.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     72.26% # Class of executed instruction
+system.cpu.op_class::MemRead                      419     16.21%     88.47% # Class of executed instruction
+system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse            80.050296                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                2423                       # Total number of references to valid blocks.
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 18325fbc5..06219c218 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    17056000                       # Number of ticks simulated
-final_tick                                   17056000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    16955000                       # Number of ticks simulated
+final_tick                                   16955000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29277                       # Simulator instruction rate (inst/s)
-host_op_rate                                    36530                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              108745688                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308972                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  43189                       # Simulator instruction rate (inst/s)
+host_op_rate                                    53887                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              159459409                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309444                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           17280                       # Nu
 system.physmem.num_reads::cpu.inst                270                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                122                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   392                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1013133208                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            457786116                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1470919325                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1013133208                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1013133208                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1013133208                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           457786116                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1470919325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1019168387                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            460513123                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1479681510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1019168387                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1019168387                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1019168387                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           460513123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1479681510                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           392                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         392                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        16998500                       # Total gap between requests
+system.physmem.totGap                        16897500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       207                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       120                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        46                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       206                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        48                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           32                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean             450                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     276.111928                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     399.674706                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127              7     21.88%     21.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255            8     25.00%     46.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            4     12.50%     59.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            1      3.12%     62.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      6.25%     68.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            1      3.12%     71.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     28.12%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             32                       # Bytes accessed per row activation
-system.physmem.totQLat                        4223500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11614750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      392.258065                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     255.879233                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     338.156911                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             13     20.97%     20.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           16     25.81%     46.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            8     12.90%     59.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            5      8.06%     67.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.84%     72.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      4.84%     77.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            4      6.45%     83.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      3.23%     87.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            8     12.90%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
+system.physmem.totQLat                        3795000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11145000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1960000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     5431250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       10774.23                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13855.23                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        9681.12                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29629.46                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1470.92                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28431.12                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1479.68                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1470.92                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1479.68                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.49                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.49                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.56                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.56                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.91                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.89                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        326                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.16                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43363.52                       # Average gap between requests
+system.physmem.avgGap                        43105.87                       # Average gap between requests
 system.physmem.pageHitRate                      83.16                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1467166979                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
+system.physmem.memoryStateTime::REF            520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15324750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1475906812                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 351                       # Transaction distribution
 system.membus.trans_dist::ReadResp                350                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                41                       # Transaction distribution
@@ -235,9 +239,9 @@ system.membus.tot_pkt_size::total               25024                       # Cu
 system.membus.data_through_bus                  25024                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              484000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3645250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.4                       # Layer utilization (%)
+system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3650250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             21.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2481                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1780                       # Number of conditional branches predicted
@@ -420,39 +424,39 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.numCycles                            34113                       # number of cpu cycles simulated
+system.cpu.numCycles                            33911                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               6922                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               6937                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          11923                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        2481                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                990                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          2627                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    1612                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   2574                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles                   2582                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.CacheLines                      1947                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   283                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13229                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.138559                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.553229                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              13252                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.136583                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.551452                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10602     80.14%     80.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      226      1.71%     81.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      203      1.53%     83.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      226      1.71%     85.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      222      1.68%     86.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      269      2.03%     88.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       92      0.70%     89.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      145      1.10%     90.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1244      9.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10625     80.18%     80.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      226      1.71%     81.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      203      1.53%     83.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      226      1.71%     85.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      222      1.68%     86.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      269      2.03%     88.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       92      0.69%     89.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      145      1.09%     90.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1244      9.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13229                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.072729                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.349515                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6934                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2849                       # Number of cycles decode is blocked
+system.cpu.fetch.rateDist::total                13252                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.073162                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.351597                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6949                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2857                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      2426                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    69                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    951                       # Number of cycles decode is squashing
@@ -461,9 +465,9 @@ system.cpu.decode.BranchMispred                   159                       # Nu
 system.cpu.decode.DecodedInsts                  13218                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   538                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    951                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7200                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                     7215                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     361                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2278                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles           2286                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      2227                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                   212                       # Number of cycles rename is unblocking
 system.cpu.rename.RenamedInsts                  12456                       # Number of instructions processed by rename
@@ -490,23 +494,23 @@ system.cpu.iq.iqSquashedInstsIssued               113                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            5124                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined        14241                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13229                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.674352                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.378841                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         13252                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.673181                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.378149                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9649     72.94%     72.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1315      9.94%     82.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 815      6.16%     89.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 543      4.10%     93.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9672     72.99%     72.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1316      9.93%     82.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 814      6.14%     89.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 543      4.10%     93.16% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::4                 457      3.45%     96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 260      1.97%     98.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 123      0.93%     99.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 259      1.95%     98.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 124      0.94%     99.49% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  55      0.42%     99.91% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  12      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13229                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13252                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       8      3.57%      3.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      3.57% # attempts to use FU when none available
@@ -576,10 +580,10 @@ system.cpu.iq.FU_type_0::MemWrite                1210     13.56%    100.00% # Ty
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                   8921                       # Type of FU issued
-system.cpu.iq.rate                           0.261513                       # Inst issue rate
+system.cpu.iq.rate                           0.263071                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.025109                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31372                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads              31395                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes             16313                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses         8052                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
@@ -612,43 +616,43 @@ system.cpu.iew.memOrderViolationEvents             21                       # Nu
 system.cpu.iew.predictedTakenIncorrect            108                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          270                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  378                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8523                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2139                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               398                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                  8524                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2140                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               397                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3299                       # number of memory reference insts executed
+system.cpu.iew.exec_refs                         3300                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1437                       # Number of branches executed
 system.cpu.iew.exec_stores                       1160                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.249846                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.251364                       # Inst execution rate
 system.cpu.iew.wb_sent                           8226                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                          8068                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                      3883                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7788                       # num instructions consuming a value
+system.cpu.iew.wb_consumers                      7789                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.236508                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.498588                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.237917                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.498524                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts            5496                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               327                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12278                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.466607                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.298423                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        12301                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.465734                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.297365                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9992     81.38%     81.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1070      8.71%     90.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          401      3.27%     93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10015     81.42%     81.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1070      8.70%     90.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          401      3.26%     93.37% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3          262      2.13%     95.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          176      1.43%     96.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          176      1.43%     96.94% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::5          172      1.40%     98.33% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6           49      0.40%     98.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           35      0.29%     99.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          121      0.99%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           35      0.28%     99.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          121      0.98%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12278                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12301                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
 system.cpu.commit.committedOps                   5729                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -659,25 +663,60 @@ system.cpu.commit.branches                       1007                       # Nu
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      4976                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   82                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             3584     62.56%     62.56% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               4      0.07%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            3      0.05%     62.68% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     62.68% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     62.68% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     62.68% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            1200     20.95%     83.63% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            938     16.37%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total              5729                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   121                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        23225                       # The number of ROB reads
+system.cpu.rob.rob_reads                        23248                       # The number of ROB reads
 system.cpu.rob.rob_writes                       23415                       # The number of ROB writes
-system.cpu.timesIdled                             220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20884                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                             221                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           20659                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
 system.cpu.committedOps                          5729                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  4591                       # Number of Instructions Simulated
-system.cpu.cpi                               7.430407                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.430407                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.134582                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.134582                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    39210                       # number of integer regfile reads
+system.cpu.cpi                               7.386408                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.386408                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.135384                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.135384                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    39214                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    7985                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                    3239                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1636022514                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1645768210                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            396                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           395                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           41                       # Transaction distribution
@@ -692,22 +731,22 @@ system.cpu.toL2Bus.data_through_bus             27904                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         218500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        478500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        480250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        228745                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        229495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 4                       # number of replacements
-system.cpu.icache.tags.tagsinuse           147.751269                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           147.354343                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1584                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               290                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              5.462069                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   147.751269                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.072144                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.072144                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   147.354343                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.071950                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.071950                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          286                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.139648                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              4184                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             4184                       # Number of data accesses
@@ -723,12 +762,12 @@ system.cpu.icache.demand_misses::cpu.inst          363                       # n
 system.cpu.icache.demand_misses::total            363                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          363                       # number of overall misses
 system.cpu.icache.overall_misses::total           363                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     24948500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     24948500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     24948500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     24948500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     24948500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     24948500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     24681000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     24681000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     24681000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     24681000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     24681000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     24681000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1947                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1947                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1947                       # number of demand (read+write) accesses
@@ -741,12 +780,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.186441
 system.cpu.icache.demand_miss_rate::total     0.186441                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.186441                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.186441                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68728.650138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68728.650138                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67991.735537                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67991.735537                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          110                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
@@ -767,39 +806,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          290
 system.cpu.icache.demand_mshr_misses::total          290                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          290                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          290                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20177000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     20177000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20177000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     20177000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20177000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     20177000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19694750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     19694750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19694750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     19694750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19694750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     19694750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.148947                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.148947                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.148947                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          186.152493                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          185.664460                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 40                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              350                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.114286                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   139.100090                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    47.052403                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004245                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001436                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005681                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   138.724086                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    46.940374                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004234                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001433                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005666                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3887                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3887                       # Number of data accesses
@@ -823,17 +862,17 @@ system.cpu.l2cache.demand_misses::total           397                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          270                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          127                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          397                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19680500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6712250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     26392750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19198250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6669000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     25867250                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3002000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      3002000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     19680500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9714250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     29394750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     19680500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9714250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     29394750                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     19198250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9671000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     28869250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     19198250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9671000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     28869250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          290                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          106                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          396                       # number of ReadReq accesses(hits+misses)
@@ -856,17 +895,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.908467                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.931034                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.863946                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.908467                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -892,17 +931,17 @@ system.cpu.l2cache.demand_mshr_misses::total          392
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          270                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          122                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          392                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16292000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5423750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21715750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15805250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5377000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21182250                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2498500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2498500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16292000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7922250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     24214250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16292000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7922250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     24214250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15805250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     23680750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15805250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7875500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     23680750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.931034                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.764151                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.886364                       # mshr miss rate for ReadReq accesses
@@ -914,39 +953,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.897025
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.931034                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.829932                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.897025                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.338696                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2394                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            87.119879                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2395                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             16.397260                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             16.404110                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.338696                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021323                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021323                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.119879                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021270                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021270                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5930                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5930                       # Number of data accesses
+system.cpu.dcache.tags.tag_accesses              5932                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5932                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1767                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1767                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          606                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            606                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           10                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           10                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
 system.cpu.dcache.demand_hits::cpu.data          2373                       # number of demand (read+write) hits
@@ -963,22 +1002,22 @@ system.cpu.dcache.demand_misses::cpu.data          496                       # n
 system.cpu.dcache.demand_misses::total            496                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          496                       # number of overall misses
 system.cpu.dcache.overall_misses::total           496                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11160743                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11160743                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11163493                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11163493                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data     20397000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total     20397000                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     31557743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     31557743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     31557743                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     31557743                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     31560493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     31560493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     31560493                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     31560493                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1956                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1956                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           12                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           12                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.demand_accesses::cpu.data         2869                       # number of demand (read+write) accesses
@@ -989,22 +1028,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.096626
 system.cpu.dcache.ReadReq_miss_rate::total     0.096626                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.336254                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.336254                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.166667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.166667                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.172883                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.172883                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.172883                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.172883                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63624.481855                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63624.481855                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63630.026210                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63630.026210                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs           98                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
@@ -1031,14 +1070,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7022255                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7022255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6979005                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6979005                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3044000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      3044000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10066255                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10066255                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10066255                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10066255                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10023005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10023005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10023005                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10023005                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054192                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054192                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
@@ -1047,14 +1086,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051237
 system.cpu.dcache.demand_mshr_miss_rate::total     0.051237                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051237                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.051237                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index b2921c80f..41f6b039e 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    17056000                       # Number of ticks simulated
-final_tick                                   17056000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    16955000                       # Number of ticks simulated
+final_tick                                   16955000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  53685                       # Simulator instruction rate (inst/s)
-host_op_rate                                    66982                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              199380443                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308976                       # Number of bytes of host memory used
+host_inst_rate                                  52426                       # Simulator instruction rate (inst/s)
+host_op_rate                                    65410                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              193552438                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308400                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           17280                       # Nu
 system.physmem.num_reads::cpu.inst                270                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                122                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   392                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1013133208                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            457786116                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1470919325                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1013133208                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1013133208                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1013133208                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           457786116                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1470919325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1019168387                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            460513123                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1479681510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1019168387                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1019168387                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1019168387                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           460513123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1479681510                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           392                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         392                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        16998500                       # Total gap between requests
+system.physmem.totGap                        16897500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       207                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       120                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        46                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       206                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        48                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           32                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean             450                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     276.111928                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     399.674706                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127              7     21.88%     21.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255            8     25.00%     46.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            4     12.50%     59.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            1      3.12%     62.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      6.25%     68.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            1      3.12%     71.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     28.12%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             32                       # Bytes accessed per row activation
-system.physmem.totQLat                        4223500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11614750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      392.258065                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     255.879233                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     338.156911                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             13     20.97%     20.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           16     25.81%     46.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            8     12.90%     59.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            5      8.06%     67.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.84%     72.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      4.84%     77.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            4      6.45%     83.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      3.23%     87.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            8     12.90%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
+system.physmem.totQLat                        3795000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11145000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1960000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     5431250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       10774.23                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13855.23                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        9681.12                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29629.46                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1470.92                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28431.12                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1479.68                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1470.92                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1479.68                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.49                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.49                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.56                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.56                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.91                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.89                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        326                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.16                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43363.52                       # Average gap between requests
+system.physmem.avgGap                        43105.87                       # Average gap between requests
 system.physmem.pageHitRate                      83.16                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1467166979                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
+system.physmem.memoryStateTime::REF            520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15324750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1475906812                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 351                       # Transaction distribution
 system.membus.trans_dist::ReadResp                350                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                41                       # Transaction distribution
@@ -235,9 +239,9 @@ system.membus.tot_pkt_size::total               25024                       # Cu
 system.membus.data_through_bus                  25024                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              484000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3645250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.4                       # Layer utilization (%)
+system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3650250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             21.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2481                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1780                       # Number of conditional branches predicted
@@ -333,39 +337,39 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            34113                       # number of cpu cycles simulated
+system.cpu.numCycles                            33911                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               6922                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               6937                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          11923                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        2481                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                990                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          2627                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    1612                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   2574                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles                   2582                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.CacheLines                      1947                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   283                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13229                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.138559                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.553229                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              13252                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.136583                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.551452                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10602     80.14%     80.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      226      1.71%     81.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      203      1.53%     83.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      226      1.71%     85.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      222      1.68%     86.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      269      2.03%     88.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       92      0.70%     89.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      145      1.10%     90.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1244      9.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10625     80.18%     80.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      226      1.71%     81.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      203      1.53%     83.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      226      1.71%     85.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      222      1.68%     86.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      269      2.03%     88.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       92      0.69%     89.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      145      1.09%     90.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1244      9.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13229                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.072729                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.349515                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6934                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2849                       # Number of cycles decode is blocked
+system.cpu.fetch.rateDist::total                13252                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.073162                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.351597                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6949                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2857                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      2426                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    69                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    951                       # Number of cycles decode is squashing
@@ -374,9 +378,9 @@ system.cpu.decode.BranchMispred                   159                       # Nu
 system.cpu.decode.DecodedInsts                  13218                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   538                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    951                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7200                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                     7215                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     361                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2278                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles           2286                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      2227                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                   212                       # Number of cycles rename is unblocking
 system.cpu.rename.RenamedInsts                  12456                       # Number of instructions processed by rename
@@ -403,23 +407,23 @@ system.cpu.iq.iqSquashedInstsIssued               113                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            5124                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined        14241                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13229                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.674352                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.378841                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         13252                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.673181                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.378149                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9649     72.94%     72.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1315      9.94%     82.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 815      6.16%     89.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 543      4.10%     93.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9672     72.99%     72.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1316      9.93%     82.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 814      6.14%     89.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 543      4.10%     93.16% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::4                 457      3.45%     96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 260      1.97%     98.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 123      0.93%     99.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 259      1.95%     98.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 124      0.94%     99.49% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  55      0.42%     99.91% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  12      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13229                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13252                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       8      3.57%      3.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      3.57% # attempts to use FU when none available
@@ -489,10 +493,10 @@ system.cpu.iq.FU_type_0::MemWrite                1210     13.56%    100.00% # Ty
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                   8921                       # Type of FU issued
-system.cpu.iq.rate                           0.261513                       # Inst issue rate
+system.cpu.iq.rate                           0.263071                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.025109                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31372                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads              31395                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes             16313                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses         8052                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
@@ -525,43 +529,43 @@ system.cpu.iew.memOrderViolationEvents             21                       # Nu
 system.cpu.iew.predictedTakenIncorrect            108                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          270                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  378                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8523                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2139                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               398                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                  8524                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2140                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               397                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3299                       # number of memory reference insts executed
+system.cpu.iew.exec_refs                         3300                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1437                       # Number of branches executed
 system.cpu.iew.exec_stores                       1160                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.249846                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.251364                       # Inst execution rate
 system.cpu.iew.wb_sent                           8226                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                          8068                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                      3883                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7788                       # num instructions consuming a value
+system.cpu.iew.wb_consumers                      7789                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.236508                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.498588                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.237917                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.498524                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts            5496                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               327                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12278                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.466607                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.298423                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        12301                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.465734                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.297365                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9992     81.38%     81.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1070      8.71%     90.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          401      3.27%     93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10015     81.42%     81.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1070      8.70%     90.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          401      3.26%     93.37% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3          262      2.13%     95.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          176      1.43%     96.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          176      1.43%     96.94% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::5          172      1.40%     98.33% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6           49      0.40%     98.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           35      0.29%     99.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          121      0.99%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           35      0.28%     99.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          121      0.98%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12278                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12301                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
 system.cpu.commit.committedOps                   5729                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -572,25 +576,60 @@ system.cpu.commit.branches                       1007                       # Nu
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      4976                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   82                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             3584     62.56%     62.56% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               4      0.07%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     62.63% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            3      0.05%     62.68% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     62.68% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     62.68% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     62.68% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            1200     20.95%     83.63% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            938     16.37%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total              5729                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   121                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        23225                       # The number of ROB reads
+system.cpu.rob.rob_reads                        23248                       # The number of ROB reads
 system.cpu.rob.rob_writes                       23415                       # The number of ROB writes
-system.cpu.timesIdled                             220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20884                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                             221                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           20659                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
 system.cpu.committedOps                          5729                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  4591                       # Number of Instructions Simulated
-system.cpu.cpi                               7.430407                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.430407                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.134582                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.134582                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    39210                       # number of integer regfile reads
+system.cpu.cpi                               7.386408                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.386408                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.135384                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.135384                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    39214                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    7985                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                    3239                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1636022514                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1645768210                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            396                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           395                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           41                       # Transaction distribution
@@ -605,22 +644,22 @@ system.cpu.toL2Bus.data_through_bus             27904                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         218500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        478500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        480250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        228745                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        229495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 4                       # number of replacements
-system.cpu.icache.tags.tagsinuse           147.751269                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           147.354343                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1584                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               290                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              5.462069                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   147.751269                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.072144                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.072144                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   147.354343                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.071950                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.071950                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          286                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.139648                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              4184                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             4184                       # Number of data accesses
@@ -636,12 +675,12 @@ system.cpu.icache.demand_misses::cpu.inst          363                       # n
 system.cpu.icache.demand_misses::total            363                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          363                       # number of overall misses
 system.cpu.icache.overall_misses::total           363                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     24948500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     24948500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     24948500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     24948500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     24948500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     24948500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     24681000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     24681000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     24681000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     24681000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     24681000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     24681000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1947                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1947                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1947                       # number of demand (read+write) accesses
@@ -654,12 +693,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.186441
 system.cpu.icache.demand_miss_rate::total     0.186441                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.186441                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.186441                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68728.650138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68728.650138                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67991.735537                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67991.735537                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          110                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
@@ -680,39 +719,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          290
 system.cpu.icache.demand_mshr_misses::total          290                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          290                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          290                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20177000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     20177000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20177000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     20177000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20177000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     20177000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19694750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     19694750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19694750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     19694750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19694750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     19694750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.148947                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.148947                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.148947                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          186.152493                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          185.664460                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 40                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              350                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.114286                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   139.100090                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    47.052403                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004245                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001436                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005681                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   138.724086                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    46.940374                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004234                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001433                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005666                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3887                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3887                       # Number of data accesses
@@ -736,17 +775,17 @@ system.cpu.l2cache.demand_misses::total           397                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          270                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          127                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          397                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19680500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6712250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     26392750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19198250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6669000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     25867250                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3002000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      3002000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     19680500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9714250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     29394750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     19680500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9714250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     29394750                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     19198250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9671000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     28869250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     19198250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9671000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     28869250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          290                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          106                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          396                       # number of ReadReq accesses(hits+misses)
@@ -769,17 +808,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.908467                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.931034                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.863946                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.908467                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -805,17 +844,17 @@ system.cpu.l2cache.demand_mshr_misses::total          392
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          270                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          122                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          392                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16292000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5423750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21715750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15805250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5377000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21182250                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2498500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2498500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16292000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7922250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     24214250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16292000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7922250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     24214250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15805250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     23680750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15805250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7875500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     23680750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.931034                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.764151                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.886364                       # mshr miss rate for ReadReq accesses
@@ -827,39 +866,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.897025
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.931034                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.829932                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.897025                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.338696                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2394                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            87.119879                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2395                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             16.397260                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             16.404110                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.338696                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021323                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021323                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.119879                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021270                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021270                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5930                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5930                       # Number of data accesses
+system.cpu.dcache.tags.tag_accesses              5932                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5932                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1767                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1767                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          606                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            606                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           10                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           10                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
 system.cpu.dcache.demand_hits::cpu.data          2373                       # number of demand (read+write) hits
@@ -876,22 +915,22 @@ system.cpu.dcache.demand_misses::cpu.data          496                       # n
 system.cpu.dcache.demand_misses::total            496                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          496                       # number of overall misses
 system.cpu.dcache.overall_misses::total           496                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11160743                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11160743                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11163493                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11163493                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data     20397000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total     20397000                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     31557743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     31557743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     31557743                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     31557743                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     31560493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     31560493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     31560493                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     31560493                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1956                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1956                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           12                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           12                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.demand_accesses::cpu.data         2869                       # number of demand (read+write) accesses
@@ -902,22 +941,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.096626
 system.cpu.dcache.ReadReq_miss_rate::total     0.096626                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.336254                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.336254                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.166667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.166667                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.172883                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.172883                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.172883                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.172883                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63624.481855                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63624.481855                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63630.026210                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63630.026210                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs           98                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
@@ -944,14 +983,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7022255                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7022255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6979005                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6979005                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3044000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      3044000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10066255                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10066255                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10066255                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10066255                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10023005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10023005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10023005                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10023005                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054192                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054192                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
@@ -960,14 +999,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051237
 system.cpu.dcache.demand_mshr_miss_rate::total     0.051237                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051237                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.051237                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index e746c690f..fe7b25846 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2870500                       # Number of ticks simulated
 final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  97101                       # Simulator instruction rate (inst/s)
-host_op_rate                                   121123                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               60664840                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 311632                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 790734                       # Simulator instruction rate (inst/s)
+host_op_rate                                   984195                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              492029482                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 297624                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -234,5 +234,40 @@ system.cpu.num_busy_cycles                       5742                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3597     62.64%     62.64% # Class of executed instruction
+system.cpu.op_class::IntMult                        4      0.07%     62.71% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.05%     62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     62.77% # Class of executed instruction
+system.cpu.op_class::MemRead                     1200     20.90%     83.66% # Class of executed instruction
+system.cpu.op_class::MemWrite                     938     16.34%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5742                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 584aefada..2a0a91e3f 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2870500                       # Number of ticks simulated
 final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  82560                       # Simulator instruction rate (inst/s)
-host_op_rate                                   102991                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               51587489                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 311624                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                 770690                       # Simulator instruction rate (inst/s)
+host_op_rate                                   959471                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              479615706                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 296608                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -147,5 +147,40 @@ system.cpu.num_busy_cycles                       5742                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3597     62.64%     62.64% # Class of executed instruction
+system.cpu.op_class::IntMult                        4      0.07%     62.71% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.05%     62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     62.77% # Class of executed instruction
+system.cpu.op_class::MemRead                     1200     20.90%     83.66% # Class of executed instruction
+system.cpu.op_class::MemWrite                     938     16.34%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5742                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 3e831f55e..ba11ac8e8 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    25969000                       # Number of ticks simulated
 final_tick                                   25969000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  82063                       # Simulator instruction rate (inst/s)
-host_op_rate                                   101927                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              466514904                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320464                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                 376681                       # Simulator instruction rate (inst/s)
+host_op_rate                                   467447                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2137718143                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306356                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4565                       # Number of instructions simulated
 sim_ops                                          5672                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -153,6 +153,41 @@ system.cpu.num_busy_cycles                      51938                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3597     62.64%     62.64% # Class of executed instruction
+system.cpu.op_class::IntMult                        4      0.07%     62.71% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.05%     62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     62.77% # Class of executed instruction
+system.cpu.op_class::MemRead                     1200     20.90%     83.66% # Class of executed instruction
+system.cpu.op_class::MemWrite                     938     16.34%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5742                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 1                       # number of replacements
 system.cpu.icache.tags.tagsinuse           114.614391                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4364                       # Total number of references to valid blocks.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 5e15549ca..12868f8fc 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000025                       # Number of seconds simulated
-sim_ticks                                    24975000                       # Number of ticks simulated
-final_tick                                   24975000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    24907000                       # Number of ticks simulated
+final_tick                                   24907000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  86020                       # Simulator instruction rate (inst/s)
-host_op_rate                                    86001                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              369354314                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 263428                       # Number of bytes of host memory used
+host_inst_rate                                  84163                       # Simulator instruction rate (inst/s)
+host_op_rate                                    84145                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              360406899                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264444                       # Number of bytes of host memory used
 host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           20288                       # Nu
 system.physmem.num_reads::cpu.inst                317                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   455                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            812332332                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            353633634                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1165965966                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       812332332                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          812332332                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           812332332                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           353633634                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1165965966                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            814550126                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            354599109                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1169149235                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       814550126                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          814550126                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           814550126                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           354599109                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1169149235                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           455                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         455                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        24894000                       # Total gap between requests
+system.physmem.totGap                        24826000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -186,34 +186,32 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           75                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      267.093333                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     186.339521                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     256.296765                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             18     24.00%     24.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           29     38.67%     62.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            9     12.00%     74.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            8     10.67%     85.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      5.33%     90.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            1      1.33%     92.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            1      1.33%     93.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5      6.67%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             75                       # Bytes accessed per row activation
-system.physmem.totQLat                        3086250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13542500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          106                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      268.075472                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.680617                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     244.800860                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             25     23.58%     23.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           40     37.74%     61.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           14     13.21%     74.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           10      9.43%     83.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            7      6.60%     90.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      1.89%     92.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      2.83%     95.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      4.72%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            106                       # Bytes accessed per row activation
+system.physmem.totQLat                        4873000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13404250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2275000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     8181250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6782.97                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    17980.77                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                       10709.89                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29763.74                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1165.97                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29459.89                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1169.15                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1165.97                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1169.15                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.11                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.11                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.13                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.13                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.51                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -221,10 +219,14 @@ system.physmem.readRowHits                        344                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   75.60                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        54712.09                       # Average gap between requests
+system.physmem.avgGap                        54562.64                       # Average gap between requests
 system.physmem.pageHitRate                      75.60                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.04                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1165965966                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
+system.physmem.memoryStateTime::REF            780000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          22841500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1169149235                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 404                       # Transaction distribution
 system.membus.trans_dist::ReadResp                404                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                51                       # Transaction distribution
@@ -237,8 +239,8 @@ system.membus.data_through_bus                  29120                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              552000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4258000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             17.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4259500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             17.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1156                       # Number of BP lookups
 system.cpu.branchPred.condPredicted               861                       # Number of conditional branches predicted
@@ -268,7 +270,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            49951                       # number of cpu cycles simulated
+system.cpu.numCycles                            49815                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken          432                       # Number of Branches Predicted As Taken (True).
@@ -290,12 +292,12 @@ system.cpu.execution_unit.executions             3133                       # Nu
 system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9487                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                          9486                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             463                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           44568                       # Number of cycles cpu's stages were not processed
+system.cpu.timesIdled                             462                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           44432                       # Number of cycles cpu's stages were not processed
 system.cpu.runCycles                             5383                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         10.776561                       # Percentage of cycles cpu is active
+system.cpu.activity                         10.805982                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              1163                       # Number of Load instructions committed
 system.cpu.comStores                              925                       # Number of Store instructions committed
 system.cpu.comBranches                            915                       # Number of Branches instructions committed
@@ -307,36 +309,36 @@ system.cpu.committedInsts                        5814                       # Nu
 system.cpu.committedOps                          5814                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  5814                       # Number of Instructions committed (Total)
-system.cpu.cpi                               8.591503                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               8.568111                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         8.591503                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.116394                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         8.568111                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.116712                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.116394                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    46303                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.116712                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    46167                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                      3648                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization                7.303157                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    47138                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization                7.323095                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    47002                       # Number of cycles 0 instructions are processed.
 system.cpu.stage1.runCycles                      2813                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                5.631519                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    47184                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization                5.646894                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    47048                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                      2767                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                5.539429                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    48713                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization                5.554552                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    48577                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                      1238                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                2.478429                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    47063                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization                2.485195                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    46927                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                      2888                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                5.781666                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization                5.797451                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                13                       # number of replacements
-system.cpu.icache.tags.tagsinuse           150.508435                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           150.585033                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 428                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               319                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              1.341693                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   150.508435                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.073490                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.073490                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   150.585033                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.073528                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.073528                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          306                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
@@ -355,12 +357,12 @@ system.cpu.icache.demand_misses::cpu.inst          350                       # n
 system.cpu.icache.demand_misses::total            350                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          350                       # number of overall misses
 system.cpu.icache.overall_misses::total           350                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25364500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25364500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25364500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25364500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25364500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25364500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25291750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25291750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25291750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25291750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25291750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25291750                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst          778                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total          778                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst          778                       # number of demand (read+write) accesses
@@ -373,12 +375,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.449871
 system.cpu.icache.demand_miss_rate::total     0.449871                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.449871                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.449871                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        72470                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        72470                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        72470                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        72470                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        72470                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        72470                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72262.142857                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 72262.142857                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 72262.142857                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 72262.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 72262.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 72262.142857                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -399,26 +401,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          319
 system.cpu.icache.demand_mshr_misses::total          319                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          319                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          319                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23031000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     23031000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23031000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     23031000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23031000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     23031000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22956750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22956750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22956750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22956750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22956750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22956750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.410026                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.410026                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.410026                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72197.492163                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72197.492163                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72197.492163                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72197.492163                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72197.492163                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72197.492163                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71964.733542                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71964.733542                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71964.733542                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71964.733542                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71964.733542                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71964.733542                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput              1171091091                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1174288353                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            406                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           406                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           51                       # Transaction distribution
@@ -433,21 +435,21 @@ system.cpu.toL2Bus.data_through_bus             29248                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         228500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        538000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        538750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        225500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        226250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          208.255183                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          208.347330                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              404                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.004950                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   152.186433                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    56.068750                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004644                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   152.267110                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    56.080220                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004647                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001711                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006355                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006358                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
@@ -471,17 +473,17 @@ system.cpu.l2cache.demand_misses::total           455                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          317                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          455                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22685500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6903000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     29588500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3846500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3846500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22685500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10749500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     33435000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22685500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10749500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     33435000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22611250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6877000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     29488250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3810250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3810250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22611250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10687250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     33298500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22611250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10687250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     33298500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          319                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
@@ -504,17 +506,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995624                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995624                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71563.091483                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79344.827586                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73238.861386                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75421.568627                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75421.568627                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71563.091483                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77894.927536                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73483.516484                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71563.091483                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77894.927536                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73483.516484                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71328.864353                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79045.977011                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72990.717822                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74710.784314                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74710.784314                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71328.864353                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77443.840580                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73183.516484                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71328.864353                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77443.840580                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73183.516484                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -534,17 +536,17 @@ system.cpu.l2cache.demand_mshr_misses::total          455
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          317                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          455                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18705000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5824500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24529500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3204500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3204500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18705000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9029000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     27734000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18705000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9029000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     27734000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18629250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5798500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24427750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3166750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3166750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18629250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8965250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     27594500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18629250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8965250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     27594500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995074                       # mshr miss rate for ReadReq accesses
@@ -556,27 +558,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995624
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995624                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59006.309148                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66948.275862                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60716.584158                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59006.309148                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65427.536232                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60953.846154                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59006.309148                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65427.536232                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60953.846154                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58767.350158                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66649.425287                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60464.727723                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62093.137255                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62093.137255                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58767.350158                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64965.579710                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60647.252747                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58767.350158                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64965.579710                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60647.252747                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            90.278621                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            90.296415                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1638                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             11.869565                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    90.278621                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022041                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022041                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    90.296415                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022045                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022045                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
@@ -599,14 +601,14 @@ system.cpu.dcache.demand_misses::cpu.data          450                       # n
 system.cpu.dcache.demand_misses::total            450                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          450                       # number of overall misses
 system.cpu.dcache.overall_misses::total           450                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7687000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7687000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     21761250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     21761250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     29448250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     29448250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     29448250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     29448250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7634750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7634750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     21637250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     21637250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     29272000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     29272000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     29272000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     29272000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
@@ -623,14 +625,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.215517
 system.cpu.dcache.demand_miss_rate::total     0.215517                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.215517                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.215517                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79247.422680                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 79247.422680                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61646.600567                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61646.600567                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65440.555556                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65440.555556                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65440.555556                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65440.555556                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78708.762887                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 78708.762887                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61295.325779                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61295.325779                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65048.888889                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65048.888889                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65048.888889                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65048.888889                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          265                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
@@ -655,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          138
 system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6996500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6996500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3900500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3900500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10897000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10897000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10897000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10897000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6970500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6970500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3864250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3864250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10834750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10834750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10834750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10834750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
@@ -671,14 +673,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092
 system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80419.540230                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80419.540230                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76480.392157                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76480.392157                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78963.768116                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78963.768116                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78963.768116                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78963.768116                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80120.689655                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80120.689655                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75769.607843                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75769.607843                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78512.681159                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78512.681159                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78512.681159                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78512.681159                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index cbbbf2296..6e934b1b9 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    21918500                       # Number of ticks simulated
-final_tick                                   21918500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21843500                       # Number of ticks simulated
+final_tick                                   21843500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  56826                       # Simulator instruction rate (inst/s)
-host_op_rate                                    56817                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              241494238                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 266500                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  63396                       # Simulator instruction rate (inst/s)
+host_op_rate                                    63384                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              268482897                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267540                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5156                       # Number of instructions simulated
 sim_ops                                          5156                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           21440                       # Nu
 system.physmem.num_reads::cpu.inst                335                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                142                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   477                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            978169127                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            414626913                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1392796040                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       978169127                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          978169127                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           978169127                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           414626913                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1392796040                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            981527686                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            416050541                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1397578227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       981527686                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          981527686                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           981527686                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           416050541                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1397578227                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           477                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         477                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21839000                       # Total gap between requests
+system.physmem.totGap                        21764000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       285                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       132                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       284                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       133                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        41                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,34 +186,33 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           87                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      246.436782                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     168.540369                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     250.647056                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             26     29.89%     29.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           32     36.78%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           13     14.94%     81.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            6      6.90%     88.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      2.30%     90.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            1      1.15%     91.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.30%     94.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5      5.75%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             87                       # Bytes accessed per row activation
-system.physmem.totQLat                        2715000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13776250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          109                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      254.238532                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.990405                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     249.769927                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             31     28.44%     28.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           40     36.70%     65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           16     14.68%     79.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8      7.34%     87.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      3.67%     90.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      0.92%     91.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      2.75%     94.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      0.92%     95.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      4.59%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            109                       # Bytes accessed per row activation
+system.physmem.totQLat                        4715500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13659250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2385000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     8676250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        5691.82                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    18189.20                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        9885.74                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28881.03                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1392.80                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28635.74                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1397.58                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1392.80                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1397.58                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.88                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.88                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.92                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.92                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -221,10 +220,14 @@ system.physmem.readRowHits                        357                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   74.84                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        45784.07                       # Average gap between requests
+system.physmem.avgGap                        45626.83                       # Average gap between requests
 system.physmem.pageHitRate                      74.84                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.05                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1392796040                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
+system.physmem.memoryStateTime::REF            520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15319000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1397578227                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 426                       # Transaction distribution
 system.membus.trans_dist::ReadResp                426                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                51                       # Transaction distribution
@@ -235,10 +238,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               30528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  30528                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              605000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              604500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4473250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             20.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4474250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             20.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2174                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1490                       # Number of conditional branches predicted
@@ -268,7 +271,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            43838                       # number of cpu cycles simulated
+system.cpu.numCycles                            43688                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.fetch.icacheStallCycles               8831                       # Number of cycles fetch is stalled on an Icache miss
@@ -277,18 +280,18 @@ system.cpu.fetch.Branches                        2174                       # Nu
 system.cpu.fetch.predictedBranches                753                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          3213                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    1374                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1408                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles                   1402                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.PendingTrapStallCycles           143                       # Number of stall cycles due to pending traps
 system.cpu.fetch.CacheLines                      1965                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   277                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14505                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.908859                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.220900                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              14499                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.909235                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.221283                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11292     77.85%     77.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1317      9.08%     86.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      104      0.72%     87.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      131      0.90%     88.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11286     77.84%     77.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1317      9.08%     86.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      104      0.72%     87.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      131      0.90%     88.54% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::4                      305      2.10%     90.65% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::5                      115      0.79%     91.44% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::6                      150      1.03%     92.48% # Number of instructions fetched each cycle (Total)
@@ -297,11 +300,11 @@ system.cpu.fetch.rateDist::8                      933      6.43%    100.00% # Nu
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14505                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.049592                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.300721                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::total                14499                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.049762                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.301753                       # Number of inst fetches per cycle
 system.cpu.decode.IdleCycles                     8899                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1660                       # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles                  1654                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      3025                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    53                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    868                       # Number of cycles decode is squashing
@@ -311,8 +314,8 @@ system.cpu.decode.DecodedInsts                  12292                       # Nu
 system.cpu.decode.SquashedInsts                   174                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    868                       # Number of cycles rename is squashing
 system.cpu.rename.IdleCycles                     9081                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     527                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            983                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.BlockCycles                     531                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            973                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      2898                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                   148                       # Number of cycles rename is unblocking
 system.cpu.rename.RenamedInsts                  11862                       # Number of instructions processed by rename
@@ -339,14 +342,14 @@ system.cpu.iq.iqSquashedInstsIssued                39                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            3412                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined         2076                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14505                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.571734                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.240341                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14499                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.571970                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.240543                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10922     75.30%     75.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1422      9.80%     85.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 891      6.14%     91.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 553      3.81%     95.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10916     75.29%     75.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1422      9.81%     85.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 891      6.15%     91.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 553      3.81%     95.05% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::4                 355      2.45%     97.50% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                 226      1.56%     99.06% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                  89      0.61%     99.68% # Number of insts issued each cycle
@@ -355,7 +358,7 @@ system.cpu.iq.issued_per_cycle::8                  17      0.12%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14505                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14499                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       5      3.12%      3.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      3.12% # attempts to use FU when none available
@@ -425,10 +428,10 @@ system.cpu.iq.FU_type_0::MemWrite                1104     13.31%    100.00% # Ty
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                   8293                       # Type of FU issued
-system.cpu.iq.rate                           0.189174                       # Inst issue rate
+system.cpu.iq.rate                           0.189823                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         160                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.019293                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31286                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads              31280                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes             12643                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses         7453                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
@@ -469,23 +472,23 @@ system.cpu.iew.exec_nop                          1512                       # nu
 system.cpu.iew.exec_refs                         3186                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1344                       # Number of branches executed
 system.cpu.iew.exec_stores                       1079                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.180483                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.181102                       # Inst execution rate
 system.cpu.iew.wb_sent                           7546                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                          7455                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                      2921                       # num instructions producing a value
 system.cpu.iew.wb_consumers                      4197                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.170058                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       0.170642                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.695973                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts            4914                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               396                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13637                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.426267                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.206560                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        13631                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.426454                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.206792                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11235     82.39%     82.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11229     82.38%     82.38% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1          999      7.33%     89.71% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2          630      4.62%     94.33% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3          315      2.31%     96.64% # Number of insts commited each cycle
@@ -497,7 +500,7 @@ system.cpu.commit.committed_per_cycle::8          106      0.78%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13637                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13631                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5813                       # Number of instructions committed
 system.cpu.commit.committedOps                   5813                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -508,25 +511,60 @@ system.cpu.commit.branches                        915                       # Nu
 system.cpu.commit.fp_insts                          2                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      5111                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   87                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass          657     11.30%     11.30% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             3062     52.68%     63.98% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               3      0.05%     64.03% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                1      0.02%     64.05% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              2      0.03%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.08% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            1163     20.01%     84.09% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            925     15.91%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total              5813                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   106                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        24245                       # The number of ROB reads
+system.cpu.rob.rob_reads                        24239                       # The number of ROB reads
 system.cpu.rob.rob_writes                       22333                       # The number of ROB writes
-system.cpu.timesIdled                             286                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           29333                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                             287                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           29189                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5156                       # Number of Instructions Simulated
 system.cpu.committedOps                          5156                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5156                       # Number of Instructions Simulated
-system.cpu.cpi                               8.502327                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         8.502327                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.117615                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.117615                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               8.473235                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.473235                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.118019                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.118019                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    10743                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    5234                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                     148                       # number of misc regfile reads
-system.cpu.toL2Bus.throughput              1401555763                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1406368027                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            429                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           429                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           51                       # Transaction distribution
@@ -541,19 +579,19 @@ system.cpu.toL2Bus.data_through_bus             30720                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         240000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        570750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        571500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        227000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        228250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                17                       # number of replacements
-system.cpu.icache.tags.tagsinuse           161.390328                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           161.382673                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1514                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               338                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              4.479290                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   161.390328                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.078804                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.078804                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   161.382673                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.078800                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.078800                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          321                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
@@ -572,12 +610,12 @@ system.cpu.icache.demand_misses::cpu.inst          451                       # n
 system.cpu.icache.demand_misses::total            451                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          451                       # number of overall misses
 system.cpu.icache.overall_misses::total           451                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31256750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31256750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31256750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31256750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31256750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31256750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     31159250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     31159250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     31159250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     31159250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     31159250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     31159250                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1965                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1965                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1965                       # number of demand (read+write) accesses
@@ -590,12 +628,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.229517
 system.cpu.icache.demand_miss_rate::total     0.229517                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.229517                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.229517                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69305.432373                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69305.432373                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69089.246120                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69089.246120                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs           47                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -616,36 +654,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          338
 system.cpu.icache.demand_mshr_misses::total          338                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          338                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          338                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24262750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24262750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24262750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24262750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24262750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24262750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24154000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24154000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24154000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24154000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24154000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24154000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.172010                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.172010                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.172010                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.172010                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.172010                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.172010                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          221.496759                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          221.484913                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              426                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.007042                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   163.678282                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    57.818477                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   163.674419                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.810494                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004995                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001764                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006760                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006759                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          426                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          237                       # Occupied blocks per task id
@@ -669,17 +707,17 @@ system.cpu.l2cache.demand_misses::total           477                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          335                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          477                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     23894750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7065750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     30960500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3800750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3800750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     23894750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10866500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     34761250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     23894750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10866500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     34761250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     23786000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7056500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     30842500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3776250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3776250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     23786000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10832750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     34618750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     23786000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10832750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     34618750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          338                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           91                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          429                       # number of ReadReq accesses(hits+misses)
@@ -702,17 +740,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.993750                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991124                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.993750                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72874.737945                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72874.737945                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -732,17 +770,17 @@ system.cpu.l2cache.demand_mshr_misses::total          477
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          335                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          477                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19660250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5948250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25608500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3170750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3170750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19660250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9119000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     28779250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19660250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9119000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     28779250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19551000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5938500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25489500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3144250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3144250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19551000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9082750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     28633750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19551000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9082750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     28633750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991124                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993007                       # mshr miss rate for ReadReq accesses
@@ -754,27 +792,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.993750
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991124                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.993750                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            91.623425                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            91.603992                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                2395                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             16.866197                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    91.623425                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022369                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022369                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    91.603992                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022364                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022364                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
@@ -797,14 +835,14 @@ system.cpu.dcache.demand_misses::cpu.data          510                       # n
 system.cpu.dcache.demand_misses::total            510                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          510                       # number of overall misses
 system.cpu.dcache.overall_misses::total           510                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     10261250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     10261250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     22413999                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     22413999                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     32675249                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     32675249                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     32675249                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     32675249                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     10242750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     10242750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     22302249                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     22302249                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     32544999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     32544999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     32544999                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     32544999                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1980                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1980                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
@@ -821,19 +859,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.175559
 system.cpu.dcache.demand_miss_rate::total     0.175559                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.175559                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.175559                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64069.115686                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64069.115686                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          605                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63813.723529                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63813.723529                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          611                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           55                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.545455                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -853,14 +891,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          142
 system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7160250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7160250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3852749                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3852749                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11012999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11012999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11012999                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11012999                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7151000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7151000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3828249                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3828249                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10979249                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10979249                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10979249                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10979249                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045960                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.045960                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
@@ -869,14 +907,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048881
 system.cpu.dcache.demand_mshr_miss_rate::total     0.048881                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048881                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.048881                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
index b2f335f88..c5418ef55 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2907000                       # Number of ticks simulated
 final_tick                                    2907000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  99853                       # Simulator instruction rate (inst/s)
-host_op_rate                                    99820                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               49894332                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269208                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                1298058                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1293725                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              644853594                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255756                       # Number of bytes of host memory used
+host_seconds                                     0.00                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -81,5 +81,40 @@ system.cpu.num_busy_cycles                       5815                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               915                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   657     11.30%     11.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3063     52.67%     63.97% # Class of executed instruction
+system.cpu.op_class::IntMult                        3      0.05%     64.02% # Class of executed instruction
+system.cpu.op_class::IntDiv                         1      0.02%     64.04% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::MemRead                     1163     20.00%     84.08% # Class of executed instruction
+system.cpu.op_class::MemWrite                     926     15.92%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5815                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 24111f1bf..88e0b5c68 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000125                       # Nu
 sim_ticks                                      125334                       # Number of ticks simulated
 final_tick                                     125334                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  32356                       # Simulator instruction rate (inst/s)
-host_op_rate                                    32352                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 697352                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 176168                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                  56489                       # Simulator instruction rate (inst/s)
+host_op_rate                                    56481                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1217426                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 162604                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -146,6 +146,41 @@ system.cpu.num_busy_cycles                     125334                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               915                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   657     11.30%     11.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3063     52.67%     63.97% # Class of executed instruction
+system.cpu.op_class::IntMult                        3      0.05%     64.02% # Class of executed instruction
+system.cpu.op_class::IntDiv                         1      0.02%     64.04% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::MemRead                     1163     20.00%     84.08% # Class of executed instruction
+system.cpu.op_class::MemWrite                     926     15.92%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5815                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.954490                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1493                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1489                      
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index d941cff49..ee2cc6627 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000032                       # Nu
 sim_ticks                                    31633000                       # Number of ticks simulated
 final_tick                                   31633000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 119247                       # Simulator instruction rate (inst/s)
-host_op_rate                                   119199                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              648290000                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277916                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 474922                       # Simulator instruction rate (inst/s)
+host_op_rate                                   474341                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2577866515                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263440                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -87,6 +87,41 @@ system.cpu.num_busy_cycles                      63266                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               915                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   657     11.30%     11.30% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3063     52.67%     63.97% # Class of executed instruction
+system.cpu.op_class::IntMult                        3      0.05%     64.02% # Class of executed instruction
+system.cpu.op_class::IntDiv                         1      0.02%     64.04% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.08% # Class of executed instruction
+system.cpu.op_class::MemRead                     1163     20.00%     84.08% # Class of executed instruction
+system.cpu.op_class::MemWrite                     926     15.92%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5815                       # Class of executed instruction
 system.cpu.icache.tags.replacements                13                       # number of replacements
 system.cpu.icache.tags.tagsinuse           132.545353                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5513                       # Total number of references to valid blocks.
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index d62c7aac6..810e47329 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,12 +1,12 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000019                       # Number of seconds simulated
-sim_ticks                                    19079500                       # Number of ticks simulated
-final_tick                                   19079500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    19030500                       # Number of ticks simulated
+final_tick                                   19030500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  82615                       # Simulator instruction rate (inst/s)
-host_op_rate                                    82599                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              272039638                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  79159                       # Simulator instruction rate (inst/s)
+host_op_rate                                    79144                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              259986612                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 262500                       # Number of bytes of host memory used
 host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           22080                       # Nu
 system.physmem.num_reads::cpu.inst                345                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                101                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1157263031                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            338792945                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1496055976                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1157263031                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1157263031                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1157263031                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           338792945                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1496055976                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1160242768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            339665274                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1499908042                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1160242768                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1160242768                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1160242768                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           339665274                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1499908042                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           446                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         446                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        18951000                       # Total gap between requests
+system.physmem.totGap                        18902000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       245                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       248                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       143                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        41                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
@@ -186,45 +186,47 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           58                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      379.586207                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     226.841802                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     367.136049                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             17     29.31%     29.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           14     24.14%     53.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            6     10.34%     63.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            3      5.17%     68.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      6.90%     75.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      3.45%     79.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.72%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           11     18.97%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             58                       # Bytes accessed per row activation
-system.physmem.totQLat                        2851500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11984000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           77                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      342.441558                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     198.974683                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     351.274465                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             28     36.36%     36.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           17     22.08%     58.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            6      7.79%     66.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            5      6.49%     72.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            5      6.49%     79.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      2.60%     81.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      3.90%     85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           11     14.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             77                       # Bytes accessed per row activation
+system.physmem.totQLat                        3599250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11961750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2230000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     6902500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6393.50                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15476.46                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        8070.07                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26869.96                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1496.06                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26820.07                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1499.91                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1496.06                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1499.91                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.69                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.69                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.72                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.72                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.80                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.79                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        358                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   80.27                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        42491.03                       # Average gap between requests
+system.physmem.avgGap                        42381.17                       # Average gap between requests
 system.physmem.pageHitRate                      80.27                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1496055976                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
+system.physmem.memoryStateTime::REF            520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15315250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1499908042                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 399                       # Transaction distribution
 system.membus.trans_dist::ReadResp                399                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                47                       # Transaction distribution
@@ -235,10 +237,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               28544                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  28544                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              567500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              565500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4177500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4183750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             22.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2235                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1802                       # Number of conditional branches predicted
@@ -268,55 +270,55 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.numCycles                            38160                       # number of cpu cycles simulated
+system.cpu.numCycles                            38062                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               7440                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               7441                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          13154                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        2235                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                800                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          2260                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    1291                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1225                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles                   1309                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.CacheLines                      1810                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   309                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              11787                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.115975                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.532873                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              11872                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.107985                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.525542                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9527     80.83%     80.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      176      1.49%     82.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      176      1.49%     83.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      142      1.20%     85.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      227      1.93%     86.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      132      1.12%     88.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      257      2.18%     90.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      110      0.93%     91.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1040      8.82%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9612     80.96%     80.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      176      1.48%     82.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      176      1.48%     83.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      142      1.20%     85.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      227      1.91%     87.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      132      1.11%     88.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      257      2.16%     90.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      110      0.93%     91.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1040      8.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11787                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.058569                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.344706                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7519                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1384                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2094                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    81                       # Number of cycles decode is unblocking
+system.cpu.fetch.rateDist::total                11872                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.058720                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.345594                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7525                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1463                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2089                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    86                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    709                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  340                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   154                       # Number of times decode detected a branch misprediction
 system.cpu.decode.DecodedInsts                  11724                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   431                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    709                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7704                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     677                       # Number of cycles rename is blocking
+system.cpu.rename.IdleCycles                     7710                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     717                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            445                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      1984                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   268                       # Number of cycles rename is unblocking
+system.cpu.rename.RunCycles                      1980                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   311                       # Number of cycles rename is unblocking
 system.cpu.rename.RenamedInsts                  11305                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                      4                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   230                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.LSQFullEvents                   264                       # Number of times rename has blocked due to LSQ full
 system.cpu.rename.RenamedOperands                9699                       # Number of destination operands rename has renamed
 system.cpu.rename.RenameLookups                 18187                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups            18161                       # Number of integer rename lookups
@@ -325,7 +327,7 @@ system.cpu.rename.CommittedMaps                  4998                       # Nu
 system.cpu.rename.UndoneMaps                     4701                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 27                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       582                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                       615                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads                 2023                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1831                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                52                       # Number of conflicting loads.
@@ -337,23 +339,23 @@ system.cpu.iq.iqSquashedInstsIssued               241                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            4242                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined         3488                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             41                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         11787                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.755154                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.486388                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         11872                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.749747                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.477871                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8427     71.49%     71.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1098      9.32%     80.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 791      6.71%     87.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 500      4.24%     91.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 455      3.86%     95.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 306      2.60%     98.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 132      1.12%     99.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8485     71.47%     71.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1128      9.50%     80.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 793      6.68%     87.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 504      4.25%     91.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 456      3.84%     95.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 296      2.49%     98.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 132      1.11%     99.34% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  45      0.38%     99.72% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  33      0.28%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           11787                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           11872                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       8      4.62%      4.62% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      4.62% # attempts to use FU when none available
@@ -423,10 +425,10 @@ system.cpu.iq.FU_type_0::MemWrite                1627     18.28%    100.00% # Ty
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                   8901                       # Type of FU issued
-system.cpu.iq.rate                           0.233255                       # Inst issue rate
+system.cpu.iq.rate                           0.233855                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         173                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.019436                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              29941                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads              30026                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes             14573                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses         8128                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  62                       # Number of floating instruction queue reads
@@ -467,35 +469,35 @@ system.cpu.iew.exec_nop                             0                       # nu
 system.cpu.iew.exec_refs                         3201                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1350                       # Number of branches executed
 system.cpu.iew.exec_stores                       1523                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.222746                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.223320                       # Inst execution rate
 system.cpu.iew.wb_sent                           8270                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                          8155                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4217                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6678                       # num instructions consuming a value
+system.cpu.iew.wb_producers                      4187                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6623                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.213705                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.631476                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.214256                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.632191                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts            4574                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               266                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        11078                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.522838                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.323591                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        11163                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.518857                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.312790                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8698     78.52%     78.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1008      9.10%     87.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          609      5.50%     93.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          270      2.44%     95.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          170      1.53%     97.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          108      0.97%     98.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           70      0.63%     98.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           44      0.40%     99.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          101      0.91%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         8756     78.44%     78.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1031      9.24%     87.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          625      5.60%     93.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          263      2.36%     95.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          174      1.56%     97.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          104      0.93%     98.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           65      0.58%     98.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           44      0.39%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          101      0.90%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        11078                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11163                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5792                       # Number of instructions committed
 system.cpu.commit.committedOps                   5792                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -506,24 +508,59 @@ system.cpu.commit.branches                       1037                       # Nu
 system.cpu.commit.fp_insts                         22                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      5698                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  103                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             3783     65.31%     65.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               0      0.00%     65.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     65.31% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              2      0.03%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.35% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead             961     16.59%     81.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite           1046     18.06%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total              5792                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   101                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        21343                       # The number of ROB reads
+system.cpu.rob.rob_reads                        21428                       # The number of ROB reads
 system.cpu.rob.rob_writes                       21442                       # The number of ROB writes
-system.cpu.timesIdled                             246                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           26373                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                             247                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           26190                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5792                       # Number of Instructions Simulated
 system.cpu.committedOps                          5792                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5792                       # Number of Instructions Simulated
-system.cpu.cpi                               6.588398                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.588398                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.151782                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.151782                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               6.571478                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.571478                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.152173                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.152173                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    13470                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    7047                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
-system.cpu.toL2Bus.throughput              1519536675                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1523449200                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            406                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           406                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           47                       # Transaction distribution
@@ -538,19 +575,19 @@ system.cpu.toL2Bus.data_through_bus             28992                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         226500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        585250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        587750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          3.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        161250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        163000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           168.852168                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           168.931685                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1369                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               351                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              3.900285                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   168.852168                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.082447                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.082447                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   168.931685                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.082486                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.082486                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          351                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
@@ -569,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst          441                       # n
 system.cpu.icache.demand_misses::total            441                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          441                       # number of overall misses
 system.cpu.icache.overall_misses::total           441                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     30135000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     30135000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     30135000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     30135000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     30135000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     30135000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     30033500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     30033500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     30033500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     30033500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     30033500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     30033500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1810                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1810                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1810                       # number of demand (read+write) accesses
@@ -587,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.243646
 system.cpu.icache.demand_miss_rate::total     0.243646                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.243646                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.243646                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68333.333333                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68333.333333                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68333.333333                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68333.333333                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68333.333333                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68333.333333                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68103.174603                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68103.174603                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          460                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
@@ -613,36 +650,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          351
 system.cpu.icache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          351                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          351                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24444750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24444750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24444750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24444750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24444750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24444750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24362250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24362250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24362250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24362250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24362250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24362250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.193923                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.193923                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.193923                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.193923                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.193923                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.193923                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69643.162393                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69643.162393                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69643.162393                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69643.162393                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69643.162393                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69643.162393                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          199.197303                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          199.280245                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  7                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              399                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.017544                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.717049                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.480255                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005118                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.794904                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.485341                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005121                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000961                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006079                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006082                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          216                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          183                       # Occupied blocks per task id
@@ -669,17 +706,17 @@ system.cpu.l2cache.demand_misses::total           446                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          345                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          101                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24033250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4074500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     28107750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3621750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3621750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     24033250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7696250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     31729500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     24033250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7696250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     31729500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     23950750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4072250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     28023000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3614250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3614250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     23950750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7686500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     31637250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     23950750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7686500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     31637250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          351                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
@@ -702,17 +739,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.984547                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.982906                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.990196                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.984547                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69661.594203                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70445.488722                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77058.510638                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77058.510638                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69661.594203                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76200.495050                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71142.376682                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69661.594203                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76200.495050                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71142.376682                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -732,17 +769,17 @@ system.cpu.l2cache.demand_mshr_misses::total          446
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          345                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          101                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19691750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3410500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     23102250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3044750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3044750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19691750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6455250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26147000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19691750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6455250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26147000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19603250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3407750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     23011000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3033250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3033250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19603250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6441000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26044250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19603250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6441000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26044250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.982906                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981818                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.982759                       # mshr miss rate for ReadReq accesses
@@ -754,25 +791,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.984547
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.982906                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.990196                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.984547                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57077.536232                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.375940                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.914894                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.914894                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.536232                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63913.366337                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58625.560538                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.536232                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63913.366337                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58625.560538                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            63.689105                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            63.690367                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                2188                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               102                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             21.450980                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    63.689105                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data    63.690367                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.015549                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.015549                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          102                       # Occupied blocks per task id
@@ -797,14 +834,14 @@ system.cpu.dcache.demand_misses::cpu.data          435                       # n
 system.cpu.dcache.demand_misses::total            435                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          435                       # number of overall misses
 system.cpu.dcache.overall_misses::total           435                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7364750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7364750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     20363246                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     20363246                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     27727996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     27727996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     27727996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     27727996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7366750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7366750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     20319996                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     20319996                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     27686746                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     27686746                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     27686746                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     27686746                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1577                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1577                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
@@ -821,19 +858,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.165841
 system.cpu.dcache.demand_miss_rate::total     0.165841                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.165841                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.165841                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70814.903846                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 70814.903846                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61520.380665                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61520.380665                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63742.519540                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63742.519540                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63742.519540                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63742.519540                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          501                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63647.691954                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63647.691954                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          492                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   100.200000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    98.400000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -853,14 +890,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          102
 system.cpu.dcache.demand_mshr_misses::total          102                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          102                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          102                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4140000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4140000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3671748                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3671748                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7811748                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7811748                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7811748                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7811748                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4137750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4137750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3664248                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3664248                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7801998                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7801998                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7801998                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7801998                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.034876                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.034876                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044933                       # mshr miss rate for WriteReq accesses
@@ -869,14 +906,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.038887
 system.cpu.dcache.demand_mshr_miss_rate::total     0.038887                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.038887                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.038887                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78122.297872                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78122.297872                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76585.764706                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76585.764706                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76585.764706                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76585.764706                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
index 96c448d8d..bcfd2d5d0 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2896000                       # Number of ticks simulated
 final_tick                                    2896000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 139089                       # Simulator instruction rate (inst/s)
-host_op_rate                                   138996                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               69453756                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265200                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                1148266                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1144862                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              570752858                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250716                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5793                       # Number of instructions simulated
 sim_ops                                          5793                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -81,5 +81,40 @@ system.cpu.num_busy_cycles                       5793                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1037                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3784     65.32%     65.32% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     65.32% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     65.32% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       2      0.03%     65.35% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.35% # Class of executed instruction
+system.cpu.op_class::MemRead                      961     16.59%     81.94% # Class of executed instruction
+system.cpu.op_class::MemWrite                    1046     18.06%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5793                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index ca26bca81..90109d140 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    20970500                       # Number of ticks simulated
-final_tick                                   20970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20918500                       # Number of ticks simulated
+final_tick                                   20918500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71497                       # Simulator instruction rate (inst/s)
-host_op_rate                                    71482                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              281347268                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269780                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  69876                       # Simulator instruction rate (inst/s)
+host_op_rate                                    69862                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              274294219                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 270808                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           18496                       # Nu
 system.physmem.num_reads::cpu.inst                289                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   423                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            882000906                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            408955437                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1290956343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       882000906                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          882000906                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           882000906                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           408955437                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1290956343                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            884193417                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            409972034                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1294165452                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       884193417                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          884193417                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           884193417                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           409972034                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1294165452                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           423                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         423                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20901000                       # Total gap between requests
+system.physmem.totGap                        20849000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       251                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       250                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       127                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        34                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,33 +186,31 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           48                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      337.333333                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     221.579222                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     300.401245                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             13     27.08%     27.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255            9     18.75%     45.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            6     12.50%     58.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            7     14.58%     72.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            6     12.50%     85.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      4.17%     89.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5     10.42%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             48                       # Bytes accessed per row activation
-system.physmem.totQLat                        3113750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11732500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           74                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      323.459459                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     226.188766                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     265.234411                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             17     22.97%     22.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           16     21.62%     44.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           11     14.86%     59.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           13     17.57%     77.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            8     10.81%     87.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            4      5.41%     93.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      6.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             74                       # Bytes accessed per row activation
+system.physmem.totQLat                        3773250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11704500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2115000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     6503750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        7361.11                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15375.30                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        8920.21                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27736.41                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1290.96                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27670.21                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1294.17                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1290.96                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1294.17                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.09                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.09                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.11                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.66                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -220,10 +218,14 @@ system.physmem.readRowHits                        339                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   80.14                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        49411.35                       # Average gap between requests
+system.physmem.avgGap                        49288.42                       # Average gap between requests
 system.physmem.pageHitRate                      80.14                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1290956343                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE            13500                       # Time in different power states
+system.physmem.memoryStateTime::REF            520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15312750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1294165452                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 342                       # Transaction distribution
 system.membus.trans_dist::ReadResp                342                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                81                       # Transaction distribution
@@ -236,8 +238,8 @@ system.membus.data_through_bus                  27072                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              501500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3929500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             18.7                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3931250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             18.8                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1636                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1090                       # Number of conditional branches predicted
@@ -249,7 +251,7 @@ system.cpu.branchPred.BTBHitPct             43.484736                       # BT
 system.cpu.branchPred.usedRAS                      67                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            41942                       # number of cpu cycles simulated
+system.cpu.numCycles                            41838                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken          651                       # Number of Branches Predicted As Taken (True).
@@ -271,12 +273,12 @@ system.cpu.execution_unit.executions             3957                       # Nu
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9659                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                          9657                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             424                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           35694                       # Number of cycles cpu's stages were not processed
+system.cpu.timesIdled                             422                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           35590                       # Number of cycles cpu's stages were not processed
 system.cpu.runCycles                             6248                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         14.896762                       # Percentage of cycles cpu is active
+system.cpu.activity                         14.933792                       # Percentage of cycles cpu is active
 system.cpu.comLoads                               715                       # Number of Load instructions committed
 system.cpu.comStores                              673                       # Number of Store instructions committed
 system.cpu.comBranches                           1115                       # Number of Branches instructions committed
@@ -288,36 +290,36 @@ system.cpu.committedInsts                        5327                       # Nu
 system.cpu.committedOps                          5327                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  5327                       # Number of Instructions committed (Total)
-system.cpu.cpi                               7.873475                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               7.853952                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         7.873475                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.127009                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         7.853952                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.127324                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.127009                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    37302                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.127324                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    37198                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                      4640                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               11.062896                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    38748                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization               11.090396                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    38644                       # Number of cycles 0 instructions are processed.
 system.cpu.stage1.runCycles                      3194                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                7.615278                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    38908                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization                7.634208                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    38804                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                      3034                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                7.233799                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    40966                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization                7.251781                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    40862                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                       976                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                2.327023                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    38785                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization                2.332807                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    38681                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                      3157                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                7.527061                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization                7.545772                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           142.644710                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           142.676310                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 892                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               291                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              3.065292                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   142.644710                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.069651                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.069651                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   142.676310                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.069666                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.069666                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          291                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          147                       # Occupied blocks per task id
@@ -336,12 +338,12 @@ system.cpu.icache.demand_misses::cpu.inst          366                       # n
 system.cpu.icache.demand_misses::total            366                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          366                       # number of overall misses
 system.cpu.icache.overall_misses::total           366                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25482750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25482750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25482750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25482750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25482750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25482750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25425250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25425250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25425250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25425250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25425250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25425250                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1258                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1258                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1258                       # number of demand (read+write) accesses
@@ -354,12 +356,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.290938
 system.cpu.icache.demand_miss_rate::total     0.290938                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.290938                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.290938                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        69625                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        69625                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        69625                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        69625                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        69625                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        69625                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69467.896175                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69467.896175                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69467.896175                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69467.896175                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69467.896175                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69467.896175                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -380,26 +382,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          291
 system.cpu.icache.demand_mshr_misses::total          291                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          291                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          291                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20711750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     20711750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20711750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     20711750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20711750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     20711750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20653250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     20653250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20653250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     20653250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20653250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     20653250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.231320                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.231320                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.231320                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.231320                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.231320                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.231320                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71174.398625                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71174.398625                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71174.398625                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71174.398625                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71174.398625                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71174.398625                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70973.367698                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70973.367698                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70973.367698                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70973.367698                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70973.367698                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70973.367698                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput              1300112062                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1303343930                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            345                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           345                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           81                       # Transaction distribution
@@ -414,24 +416,24 @@ system.cpu.toL2Bus.data_through_bus             27264                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         213000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        485750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        486250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        216250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        217000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          169.087834                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          169.122448                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              342                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.008772                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   142.075458                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    27.012376                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004336                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   142.106217                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    27.016231                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004337                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000824                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005160                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005161                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          342                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010437                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3831                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3831                       # Number of data accesses
@@ -455,17 +457,17 @@ system.cpu.l2cache.demand_misses::total           423                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          289                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          423                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20393250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4031000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     24424250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6031750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6031750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20393250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10062750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     30456000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20393250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10062750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     30456000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20334750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4016000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     24350750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5999500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5999500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20334750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10015500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     30350250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20334750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10015500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     30350250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          291                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           54                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          345                       # number of ReadReq accesses(hits+misses)
@@ -488,17 +490,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.992958                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993127                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.992958                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70564.878893                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76056.603774                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71415.935673                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74466.049383                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74466.049383                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70564.878893                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75095.149254                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        72000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70564.878893                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75095.149254                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        72000                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70362.456747                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75773.584906                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71201.023392                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74067.901235                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74067.901235                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70362.456747                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74742.537313                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        71750                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70362.456747                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74742.537313                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        71750                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -518,17 +520,17 @@ system.cpu.l2cache.demand_mshr_misses::total          423
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          289                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          423                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16781250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3376000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20157250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5037250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5037250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16781250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8413250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     25194500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16781250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8413250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     25194500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16720750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3361000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20081750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5004000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5004000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16720750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8365000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     25085750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16720750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8365000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     25085750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.991304                       # mshr miss rate for ReadReq accesses
@@ -540,27 +542,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.992958
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.992958                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58066.608997                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63698.113208                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58939.327485                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62188.271605                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62188.271605                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58066.608997                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62785.447761                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59561.465721                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58066.608997                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62785.447761                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59561.465721                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57857.266436                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63415.094340                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58718.567251                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61777.777778                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61777.777778                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57857.266436                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62425.373134                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59304.373522                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57857.266436                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62425.373134                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59304.373522                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            85.369033                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            85.354091                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                 914                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               135                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              6.770370                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    85.369033                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020842                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020842                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    85.354091                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020838                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020838                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
@@ -583,14 +585,14 @@ system.cpu.dcache.demand_misses::cpu.data          474                       # n
 system.cpu.dcache.demand_misses::total            474                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          474                       # number of overall misses
 system.cpu.dcache.overall_misses::total           474                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4594750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4594750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     29091500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     29091500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33686250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33686250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33686250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33686250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4579750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4579750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     28882250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     28882250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     33462000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     33462000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     33462000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     33462000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          715                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          715                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
@@ -607,14 +609,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.341499
 system.cpu.dcache.demand_miss_rate::total     0.341499                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.341499                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.341499                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75323.770492                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75323.770492                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70439.467312                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70439.467312                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71068.037975                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71068.037975                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71068.037975                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71068.037975                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75077.868852                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75077.868852                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69932.808717                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69932.808717                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70594.936709                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70594.936709                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 70594.936709                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 70594.936709                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          818                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                31                       # number of cycles access was blocked
@@ -639,14 +641,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          135
 system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4097500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4097500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6115250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6115250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10212750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10212750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10212750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10212750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4082500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4082500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6083000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6083000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10165500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10165500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10165500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10165500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075524                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075524                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
@@ -655,14 +657,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097262
 system.cpu.dcache.demand_mshr_miss_rate::total     0.097262                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097262                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.097262                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75879.629630                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75879.629630                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75496.913580                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75496.913580                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        75650                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        75650                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        75650                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        75650                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75601.851852                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75601.851852                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75098.765432                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75098.765432                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        75300                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        75300                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        75300                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        75300                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index fd2ae491a..0e41891dc 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2694500                       # Number of ticks simulated
 final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  97647                       # Simulator instruction rate (inst/s)
-host_op_rate                                    97614                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               49358124                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275540                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                1015247                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1012545                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              510902541                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261064                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -63,5 +63,40 @@ system.cpu.num_busy_cycles                       5390                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1121                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   173      3.22%      3.22% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3796     70.69%     73.91% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::MemRead                      723     13.46%     87.37% # Class of executed instruction
+system.cpu.op_class::MemWrite                     678     12.63%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5370                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 97d6558cc..0f04f9760 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000108                       # Nu
 sim_ticks                                      107952                       # Number of ticks simulated
 final_tick                                     107952                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   1705                       # Simulator instruction rate (inst/s)
-host_op_rate                                     1705                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                  34543                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 182496                       # Number of bytes of host memory used
-host_seconds                                     3.13                       # Real time elapsed on the host
+host_inst_rate                                  57135                       # Simulator instruction rate (inst/s)
+host_op_rate                                    57126                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1157488                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 168948                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -128,6 +128,41 @@ system.cpu.num_busy_cycles                     107952                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1121                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   173      3.22%      3.22% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3796     70.69%     73.91% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::MemRead                      723     13.46%     87.37% # Class of executed instruction
+system.cpu.op_class::MemWrite                     678     12.63%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5370                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.968393                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1289                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1285                      
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 9e27f540c..f251b736b 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    27800000                       # Number of ticks simulated
 final_tick                                   27800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  49661                       # Simulator instruction rate (inst/s)
-host_op_rate                                    49653                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              259077754                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 284248                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                 487107                       # Simulator instruction rate (inst/s)
+host_op_rate                                   486440                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2535570960                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269788                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -69,6 +69,41 @@ system.cpu.num_busy_cycles                      55600                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1121                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   173      3.22%      3.22% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3796     70.69%     73.91% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     73.91% # Class of executed instruction
+system.cpu.op_class::MemRead                      723     13.46%     87.37% # Class of executed instruction
+system.cpu.op_class::MemWrite                     678     12.63%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       5370                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           117.043638                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5114                       # Total number of references to valid blocks.
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 33851c6e5..32cefdc54 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    20069500                       # Number of ticks simulated
-final_tick                                   20069500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20011500                       # Number of ticks simulated
+final_tick                                   20011500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42536                       # Simulator instruction rate (inst/s)
-host_op_rate                                    77054                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              158640887                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 283320                       # Number of bytes of host memory used
+host_inst_rate                                  41048                       # Simulator instruction rate (inst/s)
+host_op_rate                                    74359                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              152650007                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 284392                       # Number of bytes of host memory used
 host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           17472                       # Nu
 system.physmem.num_reads::cpu.inst                273                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   414                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            870574753                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            449637510                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1320212262                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       870574753                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          870574753                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           870574753                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           449637510                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1320212262                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            873097969                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            450940709                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1324038678                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       873097969                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          873097969                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           873097969                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           450940709                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1324038678                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           415                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         415                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20021000                       # Total gap between requests
+system.physmem.totGap                        19963000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -186,33 +186,31 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           71                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      240.676056                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     152.837127                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     281.987222                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             26     36.62%     36.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           26     36.62%     73.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            8     11.27%     84.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            2      2.82%     87.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      2.82%     90.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      2.82%     92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5      7.04%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             71                       # Bytes accessed per row activation
-system.physmem.totQLat                        2360500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12135500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           97                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      248.742268                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     161.697208                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     270.249471                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             33     34.02%     34.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           34     35.05%     69.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           13     13.40%     82.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            3      3.09%     85.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            6      6.19%     91.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      3.09%     94.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      5.15%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             97                       # Bytes accessed per row activation
+system.physmem.totQLat                        4234000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12015250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2075000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     7700000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        5687.95                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    18554.22                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                       10202.41                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29242.17                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1323.40                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28952.41                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1327.24                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1323.40                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1327.24                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.34                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.34                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.37                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.37                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.61                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -220,10 +218,14 @@ system.physmem.readRowHits                        307                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   73.98                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        48243.37                       # Average gap between requests
+system.physmem.avgGap                        48103.61                       # Average gap between requests
 system.physmem.pageHitRate                      73.98                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.05                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1320212262                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
+system.physmem.memoryStateTime::REF            520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15333750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1324038678                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 338                       # Transaction distribution
 system.membus.trans_dist::ReadResp                337                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                77                       # Transaction distribution
@@ -236,109 +238,109 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total        26496
 system.membus.tot_pkt_size::total               26496                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  26496                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              500500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              501000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3871750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             19.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3873250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             19.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    3084                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              3084                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               542                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2283                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     726                       # Number of BTB hits
+system.cpu.branchPred.lookups                    3083                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3083                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               541                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2281                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     725                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             31.800263                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             31.784305                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     207                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 74                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            40140                       # number of cpu cycles simulated
+system.cpu.numCycles                            40024                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              10289                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          14134                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3084                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                933                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          3940                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2474                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   5352                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles              10292                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          14141                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3083                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                932                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3942                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2472                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   5349                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   58                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           392                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      1980                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   267                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              21899                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.150509                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.666400                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1981                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   269                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              21900                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.150913                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.666787                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    18060     82.47%     82.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      216      0.99%     83.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    18059     82.46%     82.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      217      0.99%     83.45% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::2                      142      0.65%     84.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      224      1.02%     85.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      181      0.83%     85.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      200      0.91%     86.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      224      1.02%     85.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      180      0.82%     85.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      201      0.92%     86.86% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::6                      275      1.26%     88.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      159      0.73%     88.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2442     11.15%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      159      0.73%     88.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2443     11.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                21899                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.076831                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.352118                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    11081                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  5247                       # Number of cycles decode is blocked
+system.cpu.fetch.rateDist::total                21900                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.077029                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.353313                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    11088                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  5242                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      3583                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                   131                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1857                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  24173                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1857                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    11446                       # Number of cycles rename is idle
+system.cpu.decode.SquashCycles                   1856                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  24179                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1856                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    11454                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                    3886                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            603                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3331                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   776                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  22661                       # Number of instructions processed by rename
+system.cpu.rename.serializeStallCycles            592                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3330                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   782                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  22657                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     32                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   663                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               25256                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 55040                       # Number of register rename lookups that rename has made
+system.cpu.rename.IQFullEvents                     37                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   664                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               25254                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 55037                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups            31380                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 4                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                 11063                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    14193                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                    14191                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 30                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             30                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2047                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                      2053                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads                 2285                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1565                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      20236                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      20246                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  26                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     17027                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               290                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            9729                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        13960                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     17025                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               298                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            9739                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        13977                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             14                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         21899                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.777524                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.652832                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         21900                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.777397                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.653011                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               16413     74.95%     74.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1539      7.03%     81.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1092      4.99%     86.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 724      3.31%     90.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 698      3.19%     93.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 576      2.63%     96.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 581      2.65%     98.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               16414     74.95%     74.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1544      7.05%     82.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1087      4.96%     86.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 722      3.30%     90.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 701      3.20%     93.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 573      2.62%     96.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 583      2.66%     98.74% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                 234      1.07%     99.81% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  42      0.19%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           21899                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           21900                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                     140     77.35%     77.35% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     77.35% # attempts to use FU when none available
@@ -374,7 +376,7 @@ system.cpu.iq.fu_full::MemWrite                    15      8.29%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 3      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 13667     80.27%     80.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 13665     80.26%     80.28% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    4      0.02%     80.31% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.35% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.35% # Type of FU issued
@@ -407,17 +409,17 @@ system.cpu.iq.FU_type_0::MemRead                 1973     11.59%     91.94% # Ty
 system.cpu.iq.FU_type_0::MemWrite                1373      8.06%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  17027                       # Type of FU issued
-system.cpu.iq.rate                           0.424190                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                  17025                       # Type of FU issued
+system.cpu.iq.rate                           0.425370                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         181                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010630                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              56416                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             29998                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        15642                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate                   0.010631                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              56421                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             30018                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        15641                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  17201                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  17199                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads              168                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
@@ -430,10 +432,10 @@ system.cpu.iew.lsq.thread0.blockedLoads             0                       # Nu
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            21                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1857                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    3086                       # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles                   1856                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    3085                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    35                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               20262                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts               20272                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                39                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts                  2285                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1565                       # Number of dispatched store instructions
@@ -442,33 +444,33 @@ system.cpu.iew.iewIQFullEvents                      4                       # Nu
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             12                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect            116                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          570                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  686                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16124                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1854                       # Number of load instructions executed
+system.cpu.iew.predictedNotTakenIncorrect          571                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  687                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 16122                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1853                       # Number of load instructions executed
 system.cpu.iew.iewExecSquashedInsts               903                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3127                       # number of memory reference insts executed
+system.cpu.iew.exec_refs                         3126                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1623                       # Number of branches executed
 system.cpu.iew.exec_stores                       1273                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.401694                       # Inst execution rate
-system.cpu.iew.wb_sent                          15865                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         15646                       # cumulative count of insts written-back
+system.cpu.iew.exec_rate                     0.402808                       # Inst execution rate
+system.cpu.iew.wb_sent                          15864                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         15645                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                     10128                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     15579                       # num instructions consuming a value
+system.cpu.iew.wb_consumers                     15590                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.389786                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.650106                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.390890                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.649647                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           10526                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           10536                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               593                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        20042                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.486329                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.342699                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               592                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        20044                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.486280                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.342641                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        16474     82.20%     82.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        16476     82.20%     82.20% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1         1360      6.79%     88.98% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2          589      2.94%     91.92% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3          713      3.56%     95.48% # Number of insts commited each cycle
@@ -480,7 +482,7 @@ system.cpu.commit.committed_per_cycle::8          212      1.06%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        20042                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        20044                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
 system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -491,27 +493,62 @@ system.cpu.commit.branches                       1208                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      9653                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  106                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass            1      0.01%      0.01% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             7748     79.49%     79.50% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               3      0.03%     79.53% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                7      0.07%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     79.60% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            1053     10.80%     90.41% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            935      9.59%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total              9747                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   212                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        40103                       # The number of ROB reads
-system.cpu.rob.rob_writes                       42426                       # The number of ROB writes
-system.cpu.timesIdled                             166                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           18241                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        40115                       # The number of ROB reads
+system.cpu.rob.rob_writes                       42444                       # The number of ROB writes
+system.cpu.timesIdled                             165                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           18124                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
 system.cpu.committedOps                          9747                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5380                       # Number of Instructions Simulated
-system.cpu.cpi                               7.460967                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.460967                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.134031                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.134031                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    20727                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   12358                       # number of integer regfile writes
+system.cpu.cpi                               7.439405                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.439405                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.134419                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.134419                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    20731                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   12356                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                      8004                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                     4850                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    7135                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                      8007                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     4854                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                    7133                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1326590099                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1330435000                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            340                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           77                       # Transaction distribution
@@ -526,61 +563,61 @@ system.cpu.toL2Bus.data_through_bus             26624                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         208500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        458250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        459500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        235500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        236250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           130.897576                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1609                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           130.942440                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1610                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               274                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.872263                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.875912                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   130.897576                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.063915                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.063915                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   130.942440                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.063937                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.063937                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          274                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          150                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.133789                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4234                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4234                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1609                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1609                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1609                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1609                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1609                       # number of overall hits
-system.cpu.icache.overall_hits::total            1609                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              4236                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4236                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1610                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1610                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1610                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1610                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1610                       # number of overall hits
+system.cpu.icache.overall_hits::total            1610                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          371                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           371                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          371                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            371                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          371                       # number of overall misses
 system.cpu.icache.overall_misses::total           371                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25180750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25180750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25180750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25180750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25180750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25180750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1980                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1980                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1980                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1980                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1980                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1980                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.187374                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.187374                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.187374                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.187374                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.187374                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.187374                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67872.641509                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67872.641509                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67872.641509                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67872.641509                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67872.641509                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67872.641509                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25106250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25106250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25106250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25106250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25106250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25106250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1981                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1981                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1981                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1981                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1981                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1981                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.187279                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.187279                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.187279                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.187279                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.187279                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.187279                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67671.832884                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67671.832884                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67671.832884                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67671.832884                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67671.832884                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67671.832884                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs           53                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -601,39 +638,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          274
 system.cpu.icache.demand_mshr_misses::total          274                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          274                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          274                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19745750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     19745750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19745750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     19745750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19745750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     19745750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138384                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138384                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138384                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.138384                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138384                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.138384                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72064.781022                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72064.781022                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72064.781022                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72064.781022                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72064.781022                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72064.781022                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19660000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     19660000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19660000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     19660000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19660000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     19660000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138314                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138314                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138314                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.138314                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138314                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.138314                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71751.824818                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71751.824818                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71751.824818                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71751.824818                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71751.824818                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71751.824818                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          163.708534                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          163.759335                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              337                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.005935                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.966386                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    32.742148                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003997                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   131.011600                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    32.747734                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003998                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000999                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004996                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004998                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          337                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          181                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010284                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3750                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3750                       # Number of data accesses
@@ -657,17 +694,17 @@ system.cpu.l2cache.demand_misses::total           415                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          273                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          415                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19460250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5265000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     24725250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5444500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5444500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     19460250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10709500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     30169750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     19460250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10709500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     30169750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19374500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5212250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     24586750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5445500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5445500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     19374500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10657750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     30032250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     19374500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10657750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     30032250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          274                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           66                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          340                       # number of ReadReq accesses(hits+misses)
@@ -690,17 +727,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995204                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996350                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.993007                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995204                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71282.967033                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        81000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73151.627219                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70707.792208                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70707.792208                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71282.967033                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75419.014085                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72698.192771                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71282.967033                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75419.014085                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72698.192771                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70968.864469                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80188.461538                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72741.863905                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70720.779221                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70720.779221                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70968.864469                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75054.577465                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72366.867470                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70968.864469                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75054.577465                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72366.867470                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -720,17 +757,17 @@ system.cpu.l2cache.demand_mshr_misses::total          415
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          273                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          415                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16034750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4466500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20501250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4485000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4485000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16034750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8951500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     24986250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16034750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8951500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     24986250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15946000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4413250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20359250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4486000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4486000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15946000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8899250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     24845250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15946000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8899250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     24845250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996350                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.984848                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994118                       # mshr miss rate for ReadReq accesses
@@ -742,81 +779,81 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995204
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996350                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.993007                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995204                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58735.347985                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68715.384615                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60654.585799                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58246.753247                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58246.753247                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58735.347985                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63038.732394                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60207.831325                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58735.347985                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63038.732394                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60207.831325                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58410.256410                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67896.153846                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60234.467456                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58259.740260                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58259.740260                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58410.256410                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62670.774648                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59868.072289                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58410.256410                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62670.774648                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59868.072289                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            83.267922                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2337                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            83.261165                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2335                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             16.457746                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             16.443662                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    83.267922                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020329                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020329                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    83.261165                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020327                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020327                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.034668                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5234                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5234                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1479                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1479                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              5232                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5232                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1477                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1477                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2337                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2337                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2337                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2337                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          132                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           132                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2335                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2335                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2335                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2335                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          133                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           133                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           77                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           77                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          209                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            209                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          209                       # number of overall misses
-system.cpu.dcache.overall_misses::total           209                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9669000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9669000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5702500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5702500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     15371500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     15371500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     15371500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     15371500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1611                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1611                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          210                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            210                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          210                       # number of overall misses
+system.cpu.dcache.overall_misses::total           210                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      9645750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      9645750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5703500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5703500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     15349250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     15349250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     15349250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     15349250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1610                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1610                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2546                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2546                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2546                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2546                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081937                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.081937                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2545                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2545                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2545                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2545                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.082609                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.082609                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.082353                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.082353                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.082090                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.082090                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.082090                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.082090                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        73250                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        73250                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74058.441558                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74058.441558                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73547.846890                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73547.846890                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73547.846890                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73547.846890                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.082515                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.082515                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.082515                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.082515                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72524.436090                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 72524.436090                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74071.428571                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 74071.428571                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73091.666667                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73091.666667                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73091.666667                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73091.666667                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          183                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
@@ -825,12 +862,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.750000
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           66                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           66                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           66                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           66                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           66                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           67                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           67                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           67                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           67                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           67                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           67                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           66                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           66                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           77                       # number of WriteReq MSHR misses
@@ -839,30 +876,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          143
 system.cpu.dcache.demand_mshr_misses::total          143                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          143                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5340000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5340000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5521500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5521500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10861500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10861500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10861500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10861500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040968                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040968                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5287250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5287250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5522500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5522500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10809750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10809750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10809750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10809750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040994                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040994                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.082353                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.082353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.056167                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.056167                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.056167                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.056167                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80909.090909                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80909.090909                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71707.792208                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71707.792208                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75954.545455                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75954.545455                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75954.545455                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75954.545455                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.056189                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.056189                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.056189                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.056189                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80109.848485                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80109.848485                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71720.779221                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71720.779221                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75592.657343                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75592.657343                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75592.657343                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75592.657343                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 95eaee017..0a6735ef0 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000006                       # Nu
 sim_ticks                                     5615000                       # Number of ticks simulated
 final_tick                                    5615000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  57597                       # Simulator instruction rate (inst/s)
-host_op_rate                                   104318                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               60076981                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 286548                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                 478524                       # Simulator instruction rate (inst/s)
+host_op_rate                                   865796                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              498092788                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271572                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -66,5 +66,40 @@ system.cpu.num_busy_cycles                      11231                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1208                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     1      0.01%      0.01% # Class of executed instruction
+system.cpu.op_class::IntAlu                      7749     79.49%     79.50% # Class of executed instruction
+system.cpu.op_class::IntMult                        3      0.03%     79.53% # Class of executed instruction
+system.cpu.op_class::IntDiv                         7      0.07%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::MemRead                     1053     10.80%     90.41% # Class of executed instruction
+system.cpu.op_class::MemWrite                     935      9.59%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       9748                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index f68024429..be3906efe 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000122                       # Nu
 sim_ticks                                      121759                       # Number of ticks simulated
 final_tick                                     121759                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27489                       # Simulator instruction rate (inst/s)
-host_op_rate                                    49793                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 621883                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 193512                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  47256                       # Simulator instruction rate (inst/s)
+host_op_rate                                    85597                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1069027                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 179456                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -131,6 +131,41 @@ system.cpu.num_busy_cycles                     121759                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1208                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     1      0.01%      0.01% # Class of executed instruction
+system.cpu.op_class::IntAlu                      7749     79.49%     79.50% # Class of executed instruction
+system.cpu.op_class::IntMult                        3      0.03%     79.53% # Class of executed instruction
+system.cpu.op_class::IntDiv                         7      0.07%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::MemRead                     1053     10.80%     90.41% # Class of executed instruction
+system.cpu.op_class::MemWrite                     935      9.59%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       9748                       # Class of executed instruction
 system.ruby.network.routers0.throttle0.link_utilization     5.652970                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1377                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1373                      
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 35c0c845e..bc4d8d180 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28358000                       # Number of ticks simulated
 final_tick                                   28358000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  50744                       # Simulator instruction rate (inst/s)
-host_op_rate                                    91910                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              267330545                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 295388                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                 260669                       # Simulator instruction rate (inst/s)
+host_op_rate                                   471875                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1371807276                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 281320                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -74,6 +74,41 @@ system.cpu.num_busy_cycles                      56716                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1208                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                     1      0.01%      0.01% # Class of executed instruction
+system.cpu.op_class::IntAlu                      7749     79.49%     79.50% # Class of executed instruction
+system.cpu.op_class::IntMult                        3      0.03%     79.53% # Class of executed instruction
+system.cpu.op_class::IntDiv                         7      0.07%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     79.61% # Class of executed instruction
+system.cpu.op_class::MemRead                     1053     10.80%     90.41% # Class of executed instruction
+system.cpu.op_class::MemWrite                     935      9.59%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                       9748                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           105.550219                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6637                       # Total number of references to valid blocks.
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 463d0c1e4..343b8a125 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000024                       # Number of seconds simulated
-sim_ticks                                    24279500                       # Number of ticks simulated
-final_tick                                   24279500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000025                       # Number of seconds simulated
+sim_ticks                                    24520500                       # Number of ticks simulated
+final_tick                                   24520500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  38690                       # Simulator instruction rate (inst/s)
-host_op_rate                                    38688                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               73697435                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 279072                       # Number of bytes of host memory used
-host_seconds                                     0.33                       # Real time elapsed on the host
+host_inst_rate                                  60032                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60027                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              115480799                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266308                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                       12745                       # Number of instructions simulated
 sim_ops                                         12745                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             39872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             22464                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                62336                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        39872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           39872                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                623                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                351                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   974                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1642208447                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            925224984                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2567433431                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1642208447                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1642208447                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1642208447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           925224984                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2567433431                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           974                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             40128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             22656                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                62784                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        40128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           40128                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                627                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                354                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   981                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1636508228                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            923961583                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2560469811                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1636508228                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1636508228                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1636508228                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           923961583                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2560469811                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           981                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         974                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         981                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    62336                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    62784                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     62336                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     62784                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                  83                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 153                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 156                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  77                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  58                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  59                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  87                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  48                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  49                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  32                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  50                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  51                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                  42                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                  39                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                 30                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                  38                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                 31                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 33                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 15                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                121                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 70                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                123                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                 69                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                 36                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        24131500                       # Total gap between requests
+system.physmem.totGap                        24372500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     974                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     981                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,13 +90,13 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       337                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       372                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       176                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        67                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       352                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       345                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       195                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        65                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        18                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -186,90 +186,92 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          172                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      270.511628                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     165.030710                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     293.903144                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             69     40.12%     40.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           42     24.42%     64.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           21     12.21%     76.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            7      4.07%     80.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            7      4.07%     84.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            5      2.91%     87.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            7      4.07%     91.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      1.16%     93.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           12      6.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            172                       # Bytes accessed per row activation
-system.physmem.totQLat                        8865250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  30510250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      4870000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    16775000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        9101.90                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    17222.79                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples          218                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      281.541284                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     177.445911                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     284.903946                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             77     35.32%     35.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           55     25.23%     60.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           27     12.39%     72.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           16      7.34%     80.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            7      3.21%     83.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           13      5.96%     89.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            7      3.21%     92.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            4      1.83%     94.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           12      5.50%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            218                       # Bytes accessed per row activation
+system.physmem.totQLat                       12385000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  30778750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      4905000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12624.87                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31324.69                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        2567.43                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31374.87                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        2560.47                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     2567.43                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     2560.47                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          20.06                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      20.06                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          20.00                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      20.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.36                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         2.35                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        754                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        755                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.41                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.96                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        24775.67                       # Average gap between requests
-system.physmem.pageHitRate                      77.41                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.13                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   2567433431                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 828                       # Transaction distribution
-system.membus.trans_dist::ReadResp                828                       # Transaction distribution
+system.physmem.avgGap                        24844.55                       # Average gap between requests
+system.physmem.pageHitRate                      76.96                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE            22000                       # Time in different power states
+system.physmem.memoryStateTime::REF            780000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          22830500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   2560469811                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 835                       # Transaction distribution
+system.membus.trans_dist::ReadResp                835                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               146                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              146                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1948                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1948                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               62336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  62336                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1962                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1962                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62784                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               62784                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  62784                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             1237000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             1242500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               5.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            9036000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            9118000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             37.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    6878                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              3868                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1521                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 4939                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     851                       # Number of BTB hits
+system.cpu.branchPred.lookups                    6989                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3925                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect              1533                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 5035                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     984                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             17.230209                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     911                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                184                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             19.543198                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     915                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                192                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         4650                       # DTB read hits
-system.cpu.dtb.read_misses                        105                       # DTB read misses
+system.cpu.dtb.read_hits                         4762                       # DTB read hits
+system.cpu.dtb.read_misses                        100                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     4755                       # DTB read accesses
-system.cpu.dtb.write_hits                        2025                       # DTB write hits
-system.cpu.dtb.write_misses                        86                       # DTB write misses
+system.cpu.dtb.read_accesses                     4862                       # DTB read accesses
+system.cpu.dtb.write_hits                        2071                       # DTB write hits
+system.cpu.dtb.write_misses                        87                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    2111                       # DTB write accesses
-system.cpu.dtb.data_hits                         6675                       # DTB hits
-system.cpu.dtb.data_misses                        191                       # DTB misses
+system.cpu.dtb.write_accesses                    2158                       # DTB write accesses
+system.cpu.dtb.data_hits                         6833                       # DTB hits
+system.cpu.dtb.data_misses                        187                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     6866                       # DTB accesses
-system.cpu.itb.fetch_hits                        5377                       # ITB hits
-system.cpu.itb.fetch_misses                        57                       # ITB misses
+system.cpu.dtb.data_accesses                     7020                       # DTB accesses
+system.cpu.itb.fetch_hits                        5544                       # ITB hits
+system.cpu.itb.fetch_misses                        61                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    5434                       # ITB accesses
+system.cpu.itb.fetch_accesses                    5605                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -284,322 +286,322 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload0.num_syscalls                  17                       # Number of system calls
 system.cpu.workload1.num_syscalls                  17                       # Number of system calls
-system.cpu.numCycles                            48560                       # number of cpu cycles simulated
+system.cpu.numCycles                            49042                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               1593                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          37812                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6878                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1762                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          6306                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1885                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  390                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      5377                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   876                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              28501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.326690                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.748404                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               1654                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          38433                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        6989                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1899                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          6450                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1925                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  460                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                      5544                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   915                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              29475                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.303919                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.725203                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    22195     77.87%     77.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      545      1.91%     79.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      361      1.27%     81.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      442      1.55%     82.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      446      1.56%     84.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      426      1.49%     85.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      467      1.64%     87.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      449      1.58%     88.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     3170     11.12%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    23025     78.12%     78.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      583      1.98%     80.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      359      1.22%     81.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      471      1.60%     82.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      462      1.57%     84.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      415      1.41%     85.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      502      1.70%     87.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      480      1.63%     89.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     3178     10.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                28501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.141639                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.778666                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    39333                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  8850                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      5436                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   479                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   2774                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  616                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   400                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  33055                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   811                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   2774                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    40067                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    5599                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1111                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      5029                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  2292                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  30468                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    68                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     66                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                  2187                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               22824                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 37480                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            37462                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                29475                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.142511                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.783675                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    40916                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  9080                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      5548                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   476                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   2800                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  645                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   409                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  33474                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   772                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   2800                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    41622                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    5416                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1578                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      5169                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  2235                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  30891                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    39                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                     88                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                  2140                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               23128                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 38063                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            38045                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9140                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    13684                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 49                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             37                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      6207                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2994                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1412                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
+system.cpu.rename.UndoneMaps                    13988                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 50                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             38                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      5886                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 3185                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1450                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads                 3053                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores                1420                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads                 2                       # Number of conflicting loads.
+system.cpu.memDep1.insertedLoads                 2945                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1353                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads                17                       # Number of conflicting loads.
 system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      26659                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      26844                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  79                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21903                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               125                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           12970                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         8208                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     22133                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               124                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           13088                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         8205                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             45                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         28501                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.768499                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.351420                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         29475                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.750908                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.340856                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               19061     66.88%     66.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3422     12.01%     78.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2553      8.96%     87.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1621      5.69%     93.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                1071      3.76%     97.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 496      1.74%     99.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 208      0.73%     99.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  52      0.18%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  17      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               19871     67.42%     67.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3550     12.04%     79.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2637      8.95%     88.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1555      5.28%     93.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                1051      3.57%     97.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 510      1.73%     98.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 229      0.78%     99.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  60      0.20%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  12      0.04%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           28501                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           29475                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       1      0.63%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     93     58.86%     59.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    64     40.51%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       7      3.80%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    112     60.87%     64.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    65     35.33%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7187     65.71%     65.72% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.73% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.73% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2598     23.75%     89.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1148     10.50%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7355     65.30%     65.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2746     24.38%     89.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1157     10.27%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10938                       # Type of FU issued
+system.cpu.iq.FU_type_0::total                  11263                       # Type of FU issued
 system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu                  7209     65.75%     65.76% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult                    1      0.01%     65.77% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     65.77% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     65.79% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead                 2626     23.95%     89.74% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite                1125     10.26%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  7126     65.56%     65.57% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult                    1      0.01%     65.58% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     65.58% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     65.60% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2577     23.71%     89.31% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1162     10.69%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total                  10965                       # Type of FU issued
-system.cpu.iq.FU_type::total                    21903      0.00%      0.00% # Type of FU issued
-system.cpu.iq.rate                           0.451050                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0                       75                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1                       83                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total                  158                       # FU busy when requested
-system.cpu.iq.fu_busy_rate::0                0.003424                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1                0.003789                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total            0.007214                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              72548                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             39716                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        18903                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total                  10870                       # Type of FU issued
+system.cpu.iq.FU_type::total                    22133      0.00%      0.00% # Type of FU issued
+system.cpu.iq.rate                           0.451307                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0                       83                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1                      101                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total                  184                       # FU busy when requested
+system.cpu.iq.fu_busy_rate::0                0.003750                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1                0.004563                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total            0.008313                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              74007                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             40020                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        19098                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  22035                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  22291                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               72                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               89                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1811                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           15                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          547                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads         2002                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          585                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           298                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads               59                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked           438                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads               66                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads         1870                       # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses           10                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation           15                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores          555                       # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads         1762                       # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation           17                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores          488                       # Number of stores squashed
 system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked           395                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked           324                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   2774                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    2285                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    33                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               26933                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               586                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  6047                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2832                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                   2800                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    2321                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    38                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               27123                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               657                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  6130                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2803                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 79                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     2                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             30                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            242                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect         1098                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1340                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 20369                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0               2363                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1               2406                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total           4769                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1534                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                      8                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     1                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             31                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            244                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect         1106                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1350                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 20610                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0               2500                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1               2378                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total           4878                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1523                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
-system.cpu.iew.exec_nop::0                        106                       # number of nop insts executed
+system.cpu.iew.exec_nop::0                        111                       # number of nop insts executed
 system.cpu.iew.exec_nop::1                         89                       # number of nop insts executed
-system.cpu.iew.exec_nop::total                    195                       # number of nop insts executed
-system.cpu.iew.exec_refs::0                      3425                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::1                      3474                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::total                  6899                       # number of memory reference insts executed
-system.cpu.iew.exec_branches::0                  1614                       # Number of branches executed
-system.cpu.iew.exec_branches::1                  1639                       # Number of branches executed
-system.cpu.iew.exec_branches::total              3253                       # Number of branches executed
-system.cpu.iew.exec_stores::0                    1062                       # Number of stores executed
-system.cpu.iew.exec_stores::1                    1068                       # Number of stores executed
-system.cpu.iew.exec_stores::total                2130                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.419460                       # Inst execution rate
-system.cpu.iew.wb_sent::0                        9620                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1                        9621                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total                   19241                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0                       9442                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::1                       9481                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::total                  18923                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0                   4820                       # num instructions producing a value
-system.cpu.iew.wb_producers::1                   4844                       # num instructions producing a value
-system.cpu.iew.wb_producers::total               9664                       # num instructions producing a value
-system.cpu.iew.wb_consumers::0                   6291                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::1                   6358                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::total              12649                       # num instructions consuming a value
+system.cpu.iew.exec_nop::total                    200                       # number of nop insts executed
+system.cpu.iew.exec_refs::0                      3609                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      3448                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  7057                       # number of memory reference insts executed
+system.cpu.iew.exec_branches::0                  1643                       # Number of branches executed
+system.cpu.iew.exec_branches::1                  1628                       # Number of branches executed
+system.cpu.iew.exec_branches::total              3271                       # Number of branches executed
+system.cpu.iew.exec_stores::0                    1109                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1070                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2179                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.420252                       # Inst execution rate
+system.cpu.iew.wb_sent::0                        9814                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                        9602                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   19416                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0                       9666                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       9452                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  19118                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0                   4886                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   4825                       # num instructions producing a value
+system.cpu.iew.wb_producers::total               9711                       # num instructions producing a value
+system.cpu.iew.wb_consumers::0                   6421                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   6315                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              12736                       # num instructions consuming a value
 system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0                    0.194440                       # insts written-back per cycle
-system.cpu.iew.wb_rate::1                    0.195243                       # insts written-back per cycle
-system.cpu.iew.wb_rate::total                0.389683                       # insts written-back per cycle
-system.cpu.iew.wb_fanout::0                  0.766174                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::1                  0.761875                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::total              0.764013                       # average fanout of values written-back
+system.cpu.iew.wb_rate::0                    0.197096                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.192733                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.389829                       # insts written-back per cycle
+system.cpu.iew.wb_fanout::0                  0.760941                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.764054                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              0.762484                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           14135                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           14324                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1145                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        28452                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.449142                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.218832                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1153                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        29419                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.434379                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.208273                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        22772     80.04%     80.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         2961     10.41%     90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1118      3.93%     94.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          506      1.78%     96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          376      1.32%     97.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          249      0.88%     98.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          186      0.65%     99.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           73      0.26%     99.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          211      0.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        23668     80.45%     80.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         3132     10.65%     91.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1070      3.64%     94.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          465      1.58%     96.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          341      1.16%     97.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          243      0.83%     98.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          188      0.64%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           91      0.31%     99.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          221      0.75%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        28452                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts::0              6390                       # Number of instructions committed
-system.cpu.commit.committedInsts::1              6389                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total        29419                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts::0              6389                       # Number of instructions committed
+system.cpu.commit.committedInsts::1              6390                       # Number of instructions committed
 system.cpu.commit.committedInsts::total         12779                       # Number of instructions committed
-system.cpu.commit.committedOps::0                6390                       # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::1                6389                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::0                6389                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::1                6390                       # Number of ops (including micro ops) committed
 system.cpu.commit.committedOps::total           12779                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count::0                      0                       # Number of s/w prefetches committed
 system.cpu.commit.swp_count::1                      0                       # Number of s/w prefetches committed
@@ -625,222 +627,293 @@ system.cpu.commit.int_insts::total              12614                       # Nu
 system.cpu.commit.function_calls::0               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::1               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::total           254                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   211                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass           19      0.30%      0.30% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             4319     67.60%     67.90% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               1      0.02%     67.91% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.91% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              2      0.03%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            1183     18.52%     86.46% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            865     13.54%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total              6389                       # Class of committed instruction
+system.cpu.commit.op_class_1::No_OpClass           19      0.30%      0.30% # Class of committed instruction
+system.cpu.commit.op_class_1::IntAlu             4320     67.61%     67.90% # Class of committed instruction
+system.cpu.commit.op_class_1::IntMult               1      0.02%     67.92% # Class of committed instruction
+system.cpu.commit.op_class_1::IntDiv                0      0.00%     67.92% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatAdd              2      0.03%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatCmp              0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatCvt              0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatMult             0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatDiv              0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatSqrt             0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdAdd               0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdAddAcc            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdAlu               0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdCmp               0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdCvt               0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdMisc              0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdMult              0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdMultAcc            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdShift             0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdShiftAcc            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdSqrt              0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatAdd            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatAlu            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatCmp            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatCvt            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatDiv            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatMisc            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatMult            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatMultAcc            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatSqrt            0      0.00%     67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::MemRead            1183     18.51%     86.46% # Class of committed instruction
+system.cpu.commit.op_class_1::MemWrite            865     13.54%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_1::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_1::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_1::total              6390                       # Class of committed instruction
+system.cpu.commit.op_class::total               12779      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.bw_lim_events                   221                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited::0                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::1                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::total                 0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                       131641                       # The number of ROB reads
-system.cpu.rob.rob_writes                       56622                       # The number of ROB writes
-system.cpu.timesIdled                             379                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20059                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts::0                     6373                       # Number of Instructions Simulated
-system.cpu.committedInsts::1                     6372                       # Number of Instructions Simulated
-system.cpu.committedOps::0                       6373                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::1                       6372                       # Number of Ops (including micro ops) Simulated
+system.cpu.rob.rob_reads                       133441                       # The number of ROB reads
+system.cpu.rob.rob_writes                       57026                       # The number of ROB writes
+system.cpu.timesIdled                             384                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           19567                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts::0                     6372                       # Number of Instructions Simulated
+system.cpu.committedInsts::1                     6373                       # Number of Instructions Simulated
+system.cpu.committedOps::0                       6372                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps::1                       6373                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                 12745                       # Number of Instructions Simulated
-system.cpu.cpi::0                            7.619645                       # CPI: Cycles Per Instruction
-system.cpu.cpi::1                            7.620841                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.810122                       # CPI: Total CPI of All Threads
-system.cpu.ipc::0                            0.131240                       # IPC: Instructions Per Cycle
-system.cpu.ipc::1                            0.131219                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.262459                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    25548                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   14297                       # number of integer regfile writes
+system.cpu.cpi::0                            7.696485                       # CPI: Cycles Per Instruction
+system.cpu.cpi::1                            7.695277                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.847940                       # CPI: Total CPI of All Threads
+system.cpu.ipc::0                            0.129929                       # IPC: Instructions Per Cycle
+system.cpu.ipc::1                            0.129950                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.259879                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    25834                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   14427                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      2                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              2572705369                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            830                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           830                       # Transaction distribution
+system.cpu.toL2Bus.throughput              2565689933                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            837                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           837                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq          146                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp          146                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1250                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          702                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1952                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          62464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             62464                       # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1258                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          708                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1966                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40256                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22656                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          62912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             62912                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         488000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy         491500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1024500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1033500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          4.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        562000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        567500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
 system.cpu.icache.tags.replacements::0              6                       # number of replacements
 system.cpu.icache.tags.replacements::1              0                       # number of replacements
 system.cpu.icache.tags.replacements::total            6                       # number of replacements
-system.cpu.icache.tags.tagsinuse           311.393112                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                4352                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               625                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.963200                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           315.418856                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4518                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               629                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.182830                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   311.393112                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.152047                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.152047                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          619                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          262                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          357                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.302246                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             11367                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            11367                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         4352                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4352                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4352                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4352                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4352                       # number of overall hits
-system.cpu.icache.overall_hits::total            4352                       # number of overall hits
+system.cpu.icache.tags.occ_blocks::cpu.inst   315.418856                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.154013                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.154013                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          623                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          255                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.304199                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             11703                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11703                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         4518                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4518                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4518                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4518                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4518                       # number of overall hits
+system.cpu.icache.overall_hits::total            4518                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         1019                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          1019                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         1019                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total           1019                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         1019                       # number of overall misses
 system.cpu.icache.overall_misses::total          1019                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     67780746                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     67780746                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     67780746                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     67780746                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     67780746                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     67780746                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5371                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5371                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5371                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5371                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5371                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5371                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.189723                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.189723                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.189723                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.189723                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.189723                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.189723                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66516.924436                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 66516.924436                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 66516.924436                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 66516.924436                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 66516.924436                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 66516.924436                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         2455                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     68389495                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     68389495                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     68389495                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     68389495                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     68389495                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     68389495                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5537                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5537                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5537                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5537                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5537                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5537                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.184035                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.184035                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.184035                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.184035                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.184035                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.184035                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67114.322866                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67114.322866                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67114.322866                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67114.322866                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67114.322866                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67114.322866                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2439                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                61                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                58                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    40.245902                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    42.051724                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          394                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          394                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          394                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          394                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          394                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          394                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          625                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          625                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          625                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          625                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          625                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          625                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46793246                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     46793246                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46793246                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     46793246                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46793246                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     46793246                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116366                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116366                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116366                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.116366                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116366                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.116366                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74869.193600                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74869.193600                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74869.193600                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74869.193600                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74869.193600                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 74869.193600                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          390                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          390                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          390                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          390                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          390                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          390                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          629                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          629                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          629                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          629                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          629                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          629                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46962248                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     46962248                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46962248                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     46962248                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46962248                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     46962248                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.113599                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.113599                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.113599                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.113599                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.113599                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.113599                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74661.761526                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74661.761526                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74661.761526                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 74661.761526                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74661.761526                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 74661.761526                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          432.103746                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          437.810879                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              828                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              835                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002395                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   311.897684                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   120.206062                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009518                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003668                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.013187                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          828                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          336                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          492                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025269                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             8782                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            8782                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   315.920365                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   121.890513                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009641                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.003720                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.013361                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          835                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          328                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          507                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025482                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             8845                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            8845                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          623                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          205                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          828                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          627                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          208                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          835                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data          146                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total          146                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          623                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          351                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           974                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          623                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          351                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          974                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     46144500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     16158500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     62303000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     11997000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     11997000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     46144500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     28155500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     74300000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     46144500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     28155500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     74300000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          625                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          205                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          830                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst          627                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          354                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           981                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          627                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          354                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          981                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     46310000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     17053750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     63363750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     11492750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     11492750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     46310000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     28546500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     74856500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     46310000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     28546500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     74856500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          629                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          208                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          837                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data          146                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total          146                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          625                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          351                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          976                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          625                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          351                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          976                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996800                       # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          629                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          354                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          983                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          629                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          354                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          983                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996820                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997590                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.997611                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996800                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996820                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997951                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996800                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997965                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996820                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997951                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74068.218299                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78821.951220                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75245.169082                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82171.232877                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82171.232877                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74068.218299                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80215.099715                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76283.367556                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74068.218299                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80215.099715                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76283.367556                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997965                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73859.649123                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81989.182692                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 75884.730539                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78717.465753                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78717.465753                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73859.649123                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80639.830508                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76306.320082                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73859.649123                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80639.830508                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76306.320082                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -849,164 +922,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          623                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          205                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          828                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          627                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          208                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          835                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          146                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total          146                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          623                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          351                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          974                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          623                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          351                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          974                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     38385500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     13633000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     52018500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     10201000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     10201000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     38385500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     23834000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     62219500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     38385500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     23834000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     62219500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996800                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          627                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          354                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          981                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          627                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          354                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          981                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     38486500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     14492750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     52979250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      9689750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      9689750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     38486500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     24182500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     62669000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     38486500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     24182500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     62669000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996820                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997590                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997611                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996800                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996820                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997951                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996800                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997965                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996820                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997951                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61613.964687                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66502.439024                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62824.275362                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69869.863014                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69869.863014                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61613.964687                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67903.133903                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63880.390144                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61613.964687                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67903.133903                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63880.390144                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997965                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61381.977671                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69676.682692                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63448.203593                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66368.150685                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66368.150685                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61381.977671                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68312.146893                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63882.772681                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61381.977671                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68312.146893                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63882.772681                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements::0              0                       # number of replacements
 system.cpu.dcache.tags.replacements::1              0                       # number of replacements
 system.cpu.dcache.tags.replacements::total            0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           213.465522                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                4559                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               351                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.988604                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           215.425119                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4587                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               354                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.957627                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   213.465522                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.052116                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.052116                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          351                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data   215.425119                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.052594                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.052594                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          255                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.085693                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses             11545                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses            11545                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         3545                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3545                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1014                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1014                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          4559                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4559                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4559                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4559                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          322                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           322                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          716                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          716                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1038                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1038                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1038                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1038                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     22755500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     22755500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     51611211                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     51611211                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     74366711                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     74366711                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     74366711                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     74366711                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3867                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3867                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          258                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.086426                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses             11596                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses            11596                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         3561                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3561                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1026                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1026                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          4587                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4587                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4587                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4587                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          330                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           330                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          704                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          704                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1034                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1034                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1034                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1034                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     24450500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     24450500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     50450459                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     50450459                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     74900959                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     74900959                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     74900959                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     74900959                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3891                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3891                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         5597                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         5597                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         5597                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         5597                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.083269                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.083269                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.413873                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.413873                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.185456                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.185456                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.185456                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.185456                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70669.254658                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 70669.254658                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72082.696927                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72082.696927                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71644.230250                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71644.230250                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71644.230250                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71644.230250                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         4526                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         5621                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5621                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5621                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5621                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.084811                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.084811                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.406936                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.406936                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.183953                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.183953                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.183953                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.183953                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74092.424242                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 74092.424242                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71662.583807                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 71662.583807                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.064797                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72438.064797                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72438.064797                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72438.064797                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         4010                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               103                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               101                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.941748                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    39.702970                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          117                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          117                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          570                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          570                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          687                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          687                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          687                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          687                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          205                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          205                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          122                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          122                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          558                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          558                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          680                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          680                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          680                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          680                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          208                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          208                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data          146                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total          146                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          351                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          351                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          351                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     16372000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     16372000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12145496                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     12145496                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     28517496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     28517496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     28517496                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     28517496                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053013                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053013                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          354                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          354                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          354                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          354                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17272750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     17272750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     11640746                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     11640746                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     28913496                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     28913496                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     28913496                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     28913496                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053457                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053457                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.062712                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.062712                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.062712                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.062712                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79863.414634                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79863.414634                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83188.328767                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83188.328767                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81246.427350                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 81246.427350                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81246.427350                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 81246.427350                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.062978                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.062978                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.062978                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.062978                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83042.067308                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83042.067308                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79731.136986                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79731.136986                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81676.542373                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 81676.542373                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81676.542373                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 81676.542373                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
index 260a10b90..2ad955d95 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000028                       # Number of seconds simulated
-sim_ticks                                    27725000                       # Number of ticks simulated
-final_tick                                   27725000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    27662000                       # Number of ticks simulated
+final_tick                                   27662000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72342                       # Simulator instruction rate (inst/s)
-host_op_rate                                    72337                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              132265036                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269700                       # Number of bytes of host memory used
+host_inst_rate                                  71683                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71677                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              130761776                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 270740                       # Number of bytes of host memory used
 host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           19008                       # Nu
 system.physmem.num_reads::cpu.inst                297                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   435                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            685590622                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            318557259                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1004147881                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       685590622                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          685590622                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           685590622                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           318557259                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1004147881                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            687152050                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            319282771                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1006434820                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       687152050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          687152050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           687152050                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           319282771                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1006434820                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           436                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         436                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        27691500                       # Total gap between requests
+system.physmem.totGap                        27628500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       274                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       117                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       273                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       115                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        35                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,44 +186,47 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           36                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      487.111111                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     330.231493                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     390.430808                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127              3      8.33%      8.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255            9     25.00%     33.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            8     22.22%     55.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            2      5.56%     61.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      5.56%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            1      2.78%     69.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           11     30.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             36                       # Bytes accessed per row activation
-system.physmem.totQLat                        2136500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10682750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           66                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      390.787879                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     254.304435                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.314954                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             12     18.18%     18.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           19     28.79%     46.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           10     15.15%     62.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            4      6.06%     68.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      6.06%     74.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      4.55%     78.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      4.55%     83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           11     16.67%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             66                       # Bytes accessed per row activation
+system.physmem.totQLat                        2526750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10701750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2180000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     6366250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        4900.23                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14601.49                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        5795.30                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24501.72                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1006.46                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24545.30                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1008.75                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1006.46                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1008.75                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.86                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.86                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.88                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.88                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.48                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.49                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        362                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.03                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        63512.61                       # Average gap between requests
+system.physmem.avgGap                        63368.12                       # Average gap between requests
 system.physmem.pageHitRate                      83.03                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.51                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1004147881                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE          1258750                       # Time in different power states
+system.physmem.memoryStateTime::REF            780000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          21617500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1006434820                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 351                       # Transaction distribution
 system.membus.trans_dist::ReadResp                350                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                85                       # Transaction distribution
@@ -236,7 +239,7 @@ system.membus.data_through_bus                  27840                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              519500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4047500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            4048500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             14.6                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    5146                       # Number of BP lookups
@@ -249,7 +252,7 @@ system.cpu.branchPred.BTBHitPct             66.317073                       # BT
 system.cpu.branchPred.usedRAS                     174                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  5                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            55451                       # number of cpu cycles simulated
+system.cpu.numCycles                            55325                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken         2893                       # Number of Branches Predicted As Taken (True).
@@ -271,12 +274,12 @@ system.cpu.execution_unit.executions            11045                       # Nu
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         21862                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         21861                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             439                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           37883                       # Number of cycles cpu's stages were not processed
+system.cpu.timesIdled                             438                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           37757                       # Number of cycles cpu's stages were not processed
 system.cpu.runCycles                            17568                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         31.682026                       # Percentage of cycles cpu is active
+system.cpu.activity                         31.754180                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              2225                       # Number of Load instructions committed
 system.cpu.comStores                             1448                       # Number of Store instructions committed
 system.cpu.comBranches                           3358                       # Number of Branches instructions committed
@@ -288,36 +291,36 @@ system.cpu.committedInsts                       15162                       # Nu
 system.cpu.committedOps                         15162                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                 15162                       # Number of Instructions committed (Total)
-system.cpu.cpi                               3.657235                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               3.648925                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         3.657235                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.273431                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         3.648925                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.274053                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.273431                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    42025                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.274053                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    41899                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                     13426                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               24.212368                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    46098                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization               24.267510                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    45972                       # Number of cycles 0 instructions are processed.
 system.cpu.stage1.runCycles                      9353                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               16.867144                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    46648                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization               16.905558                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    46522                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                      8803                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               15.875277                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    52573                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization               15.911432                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    52447                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                      2878                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                5.190168                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    46142                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization                5.201988                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    46016                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                      9309                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               16.787795                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization               16.826028                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           168.846335                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           168.857752                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                3004                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               299                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             10.046823                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   168.846335                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.082444                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.082444                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   168.857752                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.082450                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.082450                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          299                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
@@ -336,12 +339,12 @@ system.cpu.icache.demand_misses::cpu.inst          381                       # n
 system.cpu.icache.demand_misses::total            381                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          381                       # number of overall misses
 system.cpu.icache.overall_misses::total           381                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25942000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25942000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25942000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25942000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25942000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25942000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25881500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25881500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25881500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25881500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25881500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25881500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         3385                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         3385                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         3385                       # number of demand (read+write) accesses
@@ -354,12 +357,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.112555
 system.cpu.icache.demand_miss_rate::total     0.112555                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.112555                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.112555                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68089.238845                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68089.238845                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68089.238845                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68089.238845                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68089.238845                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68089.238845                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67930.446194                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67930.446194                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67930.446194                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67930.446194                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67930.446194                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67930.446194                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -380,26 +383,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          301
 system.cpu.icache.demand_mshr_misses::total          301                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          301                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20512000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     20512000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20512000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     20512000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20512000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     20512000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20450500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     20450500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20450500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     20450500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20450500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     20450500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.088922                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.088922                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.088922                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68146.179402                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68146.179402                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68146.179402                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68146.179402                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68146.179402                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68146.179402                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67941.860465                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67941.860465                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67941.860465                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67941.860465                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67941.860465                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67941.860465                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput              1008764653                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1011062107                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            354                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           352                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           85                       # Transaction distribution
@@ -414,24 +417,24 @@ system.cpu.toL2Bus.data_through_bus             27968                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         219500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        499500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        500000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        221500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        222000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          199.869816                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          199.884332                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              350                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.005714                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   168.179067                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.690749                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005132                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   168.191422                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.692910                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005133                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000967                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.006100                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3947                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3947                       # Number of data accesses
@@ -452,17 +455,17 @@ system.cpu.l2cache.demand_misses::total           437                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          299                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          437                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20188500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3701000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     23889500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6006500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6006500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20188500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9707500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     29896000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20188500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9707500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     29896000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20127000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3695250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     23822250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6008750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6008750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20127000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9704000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     29831000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20127000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9704000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     29831000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          301                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          354                       # number of ReadReq accesses(hits+misses)
@@ -485,17 +488,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995444                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993355                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995444                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67520.066890                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69830.188679                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67867.897727                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70664.705882                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70664.705882                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67520.066890                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70344.202899                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68411.899314                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67520.066890                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70344.202899                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68411.899314                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67314.381271                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69721.698113                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67676.846591                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70691.176471                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70691.176471                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67314.381271                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70318.840580                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68263.157895                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67314.381271                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70318.840580                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68263.157895                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -515,17 +518,17 @@ system.cpu.l2cache.demand_mshr_misses::total          437
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          299                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          437                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16473000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3042500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     19515500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4962500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4962500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16473000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8005000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     24478000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16473000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8005000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     24478000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16410500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3036250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     19446750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4964250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4964250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16410500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8000500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     24411000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16410500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8000500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     24411000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994350                       # mshr miss rate for ReadReq accesses
@@ -537,27 +540,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995444
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995444                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55093.645485                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57405.660377                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55441.761364                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58382.352941                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58382.352941                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55093.645485                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58007.246377                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56013.729977                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55093.645485                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58007.246377                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56013.729977                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54884.615385                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57287.735849                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55246.448864                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58402.941176                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58402.941176                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54884.615385                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57974.637681                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55860.411899                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54884.615385                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57974.637681                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55860.411899                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            98.543212                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            98.520897                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                3193                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             23.137681                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    98.543212                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.024058                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.024058                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    98.520897                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.024053                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.024053                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
@@ -582,14 +585,14 @@ system.cpu.dcache.demand_misses::cpu.data          480                       # n
 system.cpu.dcache.demand_misses::total            480                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          480                       # number of overall misses
 system.cpu.dcache.overall_misses::total           480                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4273500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4273500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     25910250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     25910250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     30183750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     30183750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     30183750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     30183750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4268250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4268250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     25916250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     25916250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     30184500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     30184500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     30184500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     30184500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
@@ -608,19 +611,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.130897
 system.cpu.dcache.demand_miss_rate::total     0.130897                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.130897                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.130897                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73681.034483                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73681.034483                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61398.696682                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61398.696682                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62882.812500                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62882.812500                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62882.812500                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62882.812500                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1097                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61412.914692                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61412.914692                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62884.375000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62884.375000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62884.375000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62884.375000                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1102                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                33                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    33.242424                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    33.393939                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -640,14 +643,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          138
 system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3755500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3755500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6094500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6094500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9850000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9850000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9850000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9850000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3749750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3749750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6096750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6096750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9846500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9846500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9846500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9846500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
@@ -656,14 +659,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633
 system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70858.490566                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70858.490566                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        71700                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        71700                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71376.811594                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71376.811594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71376.811594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71376.811594                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        70750                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        70750                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71726.470588                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71726.470588                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71351.449275                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71351.449275                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71351.449275                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71351.449275                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 48a264b11..a29a98d10 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000027                       # Number of seconds simulated
-sim_ticks                                    26743500                       # Number of ticks simulated
-final_tick                                   26743500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    26706500                       # Number of ticks simulated
+final_tick                                   26706500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  53060                       # Simulator instruction rate (inst/s)
-host_op_rate                                    53057                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               98286640                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 272776                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
+host_inst_rate                                  64712                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64708                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              119701044                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272800                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
 sim_insts                                       14436                       # Number of instructions simulated
 sim_ops                                         14436                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           21440                       # Nu
 system.physmem.num_reads::cpu.inst                335                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                147                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   482                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            801690130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            351786415                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1153476546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       801690130                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          801690130                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           801690130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           351786415                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1153476546                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            802800816                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            352273791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1155074607                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       802800816                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          802800816                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           802800816                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           352273791                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1155074607                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           482                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         482                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        26582500                       # Total gap between requests
+system.physmem.totGap                        26545500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       283                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       140                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       281                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       142                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        48                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
@@ -186,34 +186,33 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           41                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean             448                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     298.774659                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     377.002918                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127              5     12.20%     12.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           12     29.27%     41.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            7     17.07%     58.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            2      4.88%     63.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      4.88%     68.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            1      2.44%     70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      4.88%     75.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     24.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             41                       # Bytes accessed per row activation
-system.physmem.totQLat                        2269000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11609000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           70                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      403.200000                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     265.551535                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.027861                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             12     17.14%     17.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           22     31.43%     48.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            9     12.86%     61.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            3      4.29%     65.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      5.71%     71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      4.29%     75.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            6      8.57%     84.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.43%     85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     14.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             70                       # Bytes accessed per row activation
+system.physmem.totQLat                        2602000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11639500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2410000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     6930000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        4707.47                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14377.59                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        5398.34                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24085.06                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1153.48                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24148.34                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1155.07                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1153.48                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1155.07                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.01                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.01                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.51                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -221,10 +220,14 @@ system.physmem.readRowHits                        403                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.61                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        55150.41                       # Average gap between requests
+system.physmem.avgGap                        55073.65                       # Average gap between requests
 system.physmem.pageHitRate                      83.61                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               5.72                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1153476546                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE          1553250                       # Time in different power states
+system.physmem.memoryStateTime::REF            780000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          21299250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1155074607                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 399                       # Transaction distribution
 system.membus.trans_dist::ReadResp                399                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                83                       # Transaction distribution
@@ -235,105 +238,105 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               30848                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  30848                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              607500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              606500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4495000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            4499500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             16.8                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    6710                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              4453                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                    6716                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              4456                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect              1076                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 5017                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups                 5022                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                    2432                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             48.475184                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             48.426922                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     444                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                168                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            53488                       # number of cpu cycles simulated
+system.cpu.numCycles                            53414                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              12425                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          31097                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6710                       # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles              12411                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          31121                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        6716                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches               2876                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          9129                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    3043                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   9229                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.Cycles                          9132                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    3044                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   9191                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           921                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      5378                       # Number of cache lines fetched
+system.cpu.fetch.CacheLines                      5379                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   469                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              33579                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.926085                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.119056                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              33531                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.928126                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.121319                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    24450     72.81%     72.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     4510     13.43%     86.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      474      1.41%     87.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      392      1.17%     88.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      680      2.03%     90.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      706      2.10%     92.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      235      0.70%     93.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      253      0.75%     94.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1879      5.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    24399     72.77%     72.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     4510     13.45%     86.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      474      1.41%     87.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      392      1.17%     88.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      680      2.03%     90.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      706      2.11%     92.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      235      0.70%     93.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      253      0.75%     94.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1882      5.61%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                33579                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.125449                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.581383                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    12934                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                 10235                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      8342                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   197                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1871                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  28992                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1871                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    13577                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     435                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9274                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      7946                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   476                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  26641                       # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total                33531                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.125735                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.582638                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    12927                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 10191                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      8340                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   201                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1872                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  29008                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1872                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    13569                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     456                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9204                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      7948                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   482                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  26657                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   148                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               23939                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 49429                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            40899                       # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents                   152                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               23951                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 49456                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            40918                       # Number of integer rename lookups
 system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    10120                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                    10132                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                691                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts            694                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2745                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3528                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2282                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                      2747                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 3529                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                2285                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      22511                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      22517                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 655                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21117                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                     21121                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                97                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            7892                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         5484                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            7903                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         5498                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            180                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         33579                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.628875                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.255627                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         33531                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.629895                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.256216                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               24339     72.48%     72.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3553     10.58%     83.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2322      6.92%     89.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1704      5.07%     95.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 887      2.64%     97.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 469      1.40%     99.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 240      0.71%     99.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               24281     72.41%     72.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3570     10.65%     83.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2315      6.90%     89.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1704      5.08%     95.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 886      2.64%     97.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 470      1.40%     99.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 240      0.72%     99.81% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  45      0.13%     99.94% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  20      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           33579                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           33531                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                      46     31.29%     31.29% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     31.29% # attempts to use FU when none available
@@ -369,7 +372,7 @@ system.cpu.iq.fu_full::MemWrite                    75     51.02%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 15648     74.10%     74.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 15650     74.10%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     74.10% # Type of FU issued
@@ -398,40 +401,40 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     74.10% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 3362     15.92%     90.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2107      9.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 3362     15.92%     90.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                2109      9.99%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  21117                       # Type of FU issued
-system.cpu.iq.rate                           0.394799                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                  21121                       # Type of FU issued
+system.cpu.iq.rate                           0.395421                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006961                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              76057                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             31084                       # Number of integer instruction queue writes
+system.cpu.iq.fu_busy_rate                   0.006960                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              76017                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             31101                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses        19522                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  21264                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  21268                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               29                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1303                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1304                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           26                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          834                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          837                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            26                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1871                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     286                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    14                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               24299                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               399                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  3528                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2282                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                   1872                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     300                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    16                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               24306                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               403                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  3529                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2285                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                655                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
@@ -441,32 +444,32 @@ system.cpu.iew.predictedNotTakenIncorrect          946                       # N
 system.cpu.iew.branchMispredicts                 1210                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewExecutedInsts                 20074                       # Number of executed instructions
 system.cpu.iew.iewExecLoadInsts                  3202                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1043                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts              1047                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1133                       # number of nop insts executed
+system.cpu.iew.exec_nop                          1134                       # number of nop insts executed
 system.cpu.iew.exec_refs                         5224                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     4239                       # Number of branches executed
 system.cpu.iew.exec_stores                       2022                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.375299                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.375819                       # Inst execution rate
 system.cpu.iew.wb_sent                          19749                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                         19522                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      9122                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     11233                       # num instructions consuming a value
+system.cpu.iew.wb_producers                      9116                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     11226                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.364979                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.812072                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.365485                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.812043                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            9039                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            9046                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts              1076                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        31708                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.478176                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.176132                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        31659                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.478916                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.176623                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        24394     76.93%     76.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         4067     12.83%     89.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1357      4.28%     94.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          765      2.41%     96.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        24337     76.87%     76.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         4081     12.89%     89.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1353      4.27%     94.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          763      2.41%     96.45% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::4          348      1.10%     97.55% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::5          270      0.85%     98.40% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6          322      1.02%     99.42% # Number of insts commited each cycle
@@ -475,7 +478,7 @@ system.cpu.commit.committed_per_cycle::8          117      0.37%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        31708                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        31659                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                15162                       # Number of instructions committed
 system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -486,24 +489,59 @@ system.cpu.commit.branches                       3358                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                     12174                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  187                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass          726      4.79%      4.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu            10763     70.99%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     75.77% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            2225     14.67%     90.45% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite           1448      9.55%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total             15162                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   117                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        54969                       # The number of ROB reads
-system.cpu.rob.rob_writes                       50281                       # The number of ROB writes
+system.cpu.rob.rob_reads                        54927                       # The number of ROB reads
+system.cpu.rob.rob_writes                       50296                       # The number of ROB writes
 system.cpu.timesIdled                             211                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           19909                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           19883                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
 system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                 14436                       # Number of Instructions Simulated
-system.cpu.cpi                               3.705181                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.705181                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.269892                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.269892                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               3.700055                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.700055                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.270266                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.270266                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    32043                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   17841                       # number of integer regfile writes
 system.cpu.misc_regfile_reads                    6919                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1158262755                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1159867448                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            401                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           401                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           83                       # Transaction distribution
@@ -518,61 +556,61 @@ system.cpu.toL2Bus.data_through_bus             30976                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         242000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        562250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        564000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        233750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        235000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           187.339200                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                4870                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           187.422918                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4872                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               337                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             14.451039                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs             14.456973                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   187.339200                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.091474                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.091474                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   187.422918                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.091515                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.091515                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          337                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.164551                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             11093                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            11093                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         4870                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4870                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4870                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4870                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4870                       # number of overall hits
-system.cpu.icache.overall_hits::total            4870                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          508                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           508                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          508                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            508                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          508                       # number of overall misses
-system.cpu.icache.overall_misses::total           508                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31654500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31654500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31654500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31654500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31654500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31654500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5378                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5378                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5378                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5378                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5378                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5378                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.094459                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.094459                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.094459                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.094459                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.094459                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.094459                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62312.007874                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62312.007874                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62312.007874                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62312.007874                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62312.007874                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62312.007874                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses             11095                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11095                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         4872                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4872                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4872                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4872                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4872                       # number of overall hits
+system.cpu.icache.overall_hits::total            4872                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          507                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           507                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          507                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            507                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          507                       # number of overall misses
+system.cpu.icache.overall_misses::total           507                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     31638750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     31638750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     31638750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     31638750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     31638750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     31638750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5379                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5379                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5379                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5379                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5379                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5379                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.094255                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.094255                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.094255                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.094255                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.094255                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.094255                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62403.846154                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 62403.846154                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62403.846154                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 62403.846154                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62403.846154                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 62403.846154                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -581,48 +619,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          171                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          171                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          171                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          171                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          171                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          171                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          170                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          170                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          170                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          170                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          170                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          170                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          337                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          337                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          337                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          337                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          337                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          337                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22543250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22543250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22543250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22543250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22543250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22543250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.062663                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.062663                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.062663                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.062663                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.062663                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.062663                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66893.916914                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66893.916914                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66893.916914                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66893.916914                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66893.916914                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66893.916914                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22516000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22516000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22516000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22516000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.062651                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.062651                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.062651                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.062651                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.062651                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.062651                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66813.056380                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66813.056380                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66813.056380                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66813.056380                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66813.056380                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66813.056380                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          221.171170                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          221.271055                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              399                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.005013                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   186.732473                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    34.438696                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005699                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001051                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006750                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   186.815406                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    34.455649                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005701                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001052                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006753                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          288                       # Occupied blocks per task id
@@ -646,17 +684,17 @@ system.cpu.l2cache.demand_misses::total           482                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          335                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          147                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          482                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22186250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4642250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     26828500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6101000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6101000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22186250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10743250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     32929500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22186250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10743250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     32929500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22159000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4637250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     26796250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6037250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6037250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22159000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10674500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     32833500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22159000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10674500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     32833500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          337                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           64                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          401                       # number of ReadReq accesses(hits+misses)
@@ -679,17 +717,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995868                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994065                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995868                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66227.611940                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72535.156250                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67239.348371                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73506.024096                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73506.024096                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66227.611940                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73083.333333                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68318.464730                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66227.611940                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73083.333333                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68318.464730                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66146.268657                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72457.031250                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67158.521303                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72737.951807                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72737.951807                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66146.268657                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72615.646259                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68119.294606                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66146.268657                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72615.646259                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68119.294606                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -709,17 +747,17 @@ system.cpu.l2cache.demand_mshr_misses::total          482
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          335                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          482                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17979250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3856250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21835500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5083000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5083000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17979250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8939250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26918500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17979250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8939250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26918500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17946500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3851750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21798250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5016750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5016750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17946500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8868500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26815000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17946500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8868500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26815000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.994065                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995012                       # mshr miss rate for ReadReq accesses
@@ -731,27 +769,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995868
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994065                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995868                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53669.402985                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60253.906250                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54725.563910                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61240.963855                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61240.963855                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53669.402985                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.224490                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55847.510373                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53669.402985                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.224490                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55847.510373                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53571.641791                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60183.593750                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54632.205514                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60442.771084                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60442.771084                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53571.641791                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60329.931973                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55632.780083                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53571.641791                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60329.931973                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55632.780083                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            99.038544                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            99.054052                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                4001                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               147                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             27.217687                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    99.038544                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.024179                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.024179                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    99.054052                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.024183                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.024183                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          147                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
@@ -776,14 +814,14 @@ system.cpu.dcache.demand_misses::cpu.data          535                       # n
 system.cpu.dcache.demand_misses::total            535                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          535                       # number of overall misses
 system.cpu.dcache.overall_misses::total           535                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7972250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7972250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     25777976                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     25777976                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33750226                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33750226                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33750226                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33750226                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7967250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7967250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     25697977                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     25697977                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     33665227                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     33665227                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     33665227                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     33665227                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         3088                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         3088                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
@@ -802,19 +840,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.118102
 system.cpu.dcache.demand_miss_rate::total     0.118102                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.118102                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.118102                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63271.825397                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63271.825397                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63026.836186                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63026.836186                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63084.534579                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63084.534579                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63084.534579                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63084.534579                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          792                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63232.142857                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63232.142857                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62831.239609                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62831.239609                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62925.657944                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62925.657944                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62925.657944                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62925.657944                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          776                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                26                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                25                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.461538                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.040000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -834,14 +872,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4706750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4706750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6185000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6185000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10891750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10891750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10891750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10891750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4701750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4701750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6121250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6121250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10823000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10823000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10823000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10823000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020725                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020725                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
@@ -850,14 +888,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032450
 system.cpu.dcache.demand_mshr_miss_rate::total     0.032450                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032450                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.032450                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73542.968750                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73542.968750                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74518.072289                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74518.072289                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74093.537415                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74093.537415                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74093.537415                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74093.537415                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73464.843750                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73464.843750                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        73750                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        73750                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73625.850340                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73625.850340                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73625.850340                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73625.850340                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index fd07afc4b..33f452573 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000008                       # Nu
 sim_ticks                                     7612000                       # Number of ticks simulated
 final_tick                                    7612000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  30038                       # Simulator instruction rate (inst/s)
-host_op_rate                                    30037                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               15079139                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275464                       # Number of bytes of host memory used
-host_seconds                                     0.51                       # Real time elapsed on the host
+host_inst_rate                                 945144                       # Simulator instruction rate (inst/s)
+host_op_rate                                   944261                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              473677660                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260980                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -65,5 +65,40 @@ system.cpu.num_busy_cycles                      15225                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              3363                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   726      4.77%      4.77% # Class of executed instruction
+system.cpu.op_class::IntAlu                     10798     71.01%     75.78% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::MemRead                     2231     14.67%     90.45% # Class of executed instruction
+system.cpu.op_class::MemWrite                    1452      9.55%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                      15207                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 2ac6dbc74..853f97527 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000041                       # Nu
 sim_ticks                                    41368000                       # Number of ticks simulated
 final_tick                                   41368000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29571                       # Simulator instruction rate (inst/s)
-host_op_rate                                    29570                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               80676332                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 284172                       # Number of bytes of host memory used
-host_seconds                                     0.51                       # Real time elapsed on the host
+host_inst_rate                                 324057                       # Simulator instruction rate (inst/s)
+host_op_rate                                   323947                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              883591781                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269720                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -69,6 +69,41 @@ system.cpu.num_busy_cycles                      82736                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              3363                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                   726      4.77%      4.77% # Class of executed instruction
+system.cpu.op_class::IntAlu                     10798     71.01%     75.78% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     75.78% # Class of executed instruction
+system.cpu.op_class::MemRead                     2231     14.67%     90.45% # Class of executed instruction
+system.cpu.op_class::MemWrite                    1452      9.55%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                      15207                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           153.782734                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs               14928                       # Total number of references to valid blocks.
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 7012b3f19..8ec8c1281 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000111                       # Number of seconds simulated
-sim_ticks                                   110955500                       # Number of ticks simulated
-final_tick                                  110955500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   110872500                       # Number of ticks simulated
+final_tick                                  110872500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 120250                       # Simulator instruction rate (inst/s)
-host_op_rate                                   120250                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               12800201                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 288992                       # Number of bytes of host memory used
-host_seconds                                     8.67                       # Real time elapsed on the host
-sim_insts                                     1042358                       # Number of instructions simulated
-sim_ops                                       1042358                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 118027                       # Simulator instruction rate (inst/s)
+host_op_rate                                   118027                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               12557410                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 289008                       # Number of bytes of host memory used
+host_seconds                                     8.83                       # Real time elapsed on the host
+sim_insts                                     1042088                       # Number of instructions simulated
+sim_ops                                       1042088                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst            22784                       # Number of bytes read from this memory
@@ -36,29 +36,29 @@ system.physmem.num_reads::cpu2.data                20                       # Nu
 system.physmem.num_reads::cpu3.inst                 7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   659                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           205343584                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            96903714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst             5768078                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             7498502                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            41530163                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data            11536156                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             4037655                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7498502                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               380116353                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      205343584                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst        5768078                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       41530163                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        4037655                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          256679480                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          205343584                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           96903714                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            5768078                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            7498502                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           41530163                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data           11536156                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            4037655                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7498502                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              380116353                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           205497305                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            96976257                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst             5772396                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             7504115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst            41561253                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data            11544792                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             4040677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             7504115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               380400911                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      205497305                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst        5772396                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst       41561253                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        4040677                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          256871632                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          205497305                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           96976257                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst            5772396                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            7504115                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst           41561253                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data           11544792                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            4040677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            7504115                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              380400911                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           660                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         660                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                       110927500                       # Total gap between requests
+system.physmem.totGap                       110844500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -120,8 +120,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       409                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       188                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       403                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       194                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
@@ -216,35 +216,33 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           89                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      285.483146                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     186.878201                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     280.642368                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             28     31.46%     31.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           26     29.21%     60.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           13     14.61%     75.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            5      5.62%     80.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            5      5.62%     86.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      3.37%     89.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.25%     92.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.12%     93.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            6      6.74%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             89                       # Bytes accessed per row activation
-system.physmem.totQLat                        3793500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  17983500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          148                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      275.027027                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     186.656156                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     254.302887                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             45     30.41%     30.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           43     29.05%     59.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           21     14.19%     73.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           12      8.11%     81.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           10      6.76%     88.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            5      3.38%     91.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            5      3.38%     95.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      0.68%     95.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            6      4.05%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            148                       # Bytes accessed per row activation
+system.physmem.totQLat                        5597750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  17972750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      3300000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    10890000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        5747.73                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16500.00                       # Average bank access latency per DRAM burst
+system.physmem.avgQLat                        8481.44                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27247.73                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         380.69                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27231.44                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         380.98                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      380.69                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      380.98                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.97                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           2.98                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -252,10 +250,14 @@ system.physmem.readRowHits                        505                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   76.52                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       168071.97                       # Average gap between requests
+system.physmem.avgGap                       167946.21                       # Average gap between requests
 system.physmem.pageHitRate                      76.52                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               9.12                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    380116353                       # Throughput (bytes/s)
+system.physmem.memoryStateTime::IDLE         48028250                       # Time in different power states
+system.physmem.memoryStateTime::REF           3640000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          57613000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    380400911                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 529                       # Transaction distribution
 system.membus.trans_dist::ReadResp                528                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              287                       # Transaction distribution
@@ -268,26 +270,26 @@ system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port        42176
 system.membus.tot_pkt_size::total               42176                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  42176                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              925000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              925500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            6291924                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            6302174                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              5.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  417.123879                       # Cycle average of tags in use
+system.l2c.tags.tagsinuse                  417.213115                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       1443                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                      526                       # Sample count of references to valid blocks.
 system.l2c.tags.avg_refs                     2.743346                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.799384                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      285.051208                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       58.412458                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst        7.037952                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        0.694517                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst       55.368542                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        5.407900                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        3.619836                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.732082                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks       0.799585                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      285.091922                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       58.421534                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst        7.040102                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data        0.695019                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst       55.399606                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data        5.410902                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        3.621924                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        0.732522                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.004350                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.data       0.000891                       # Average percentage of cache occupancy
@@ -297,11 +299,11 @@ system.l2c.tags.occ_percent::cpu2.inst       0.000845                       # Av
 system.l2c.tags.occ_percent::cpu2.data       0.000083                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.inst       0.000055                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.000011                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.006365                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.006366                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024          526                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          180                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          179                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.008026                       # Percentage of cache occupancy per task id
 system.l2c.tags.tag_accesses                    18244                       # Number of tag accesses
 system.l2c.tags.data_accesses                   18244                       # Number of data accesses
@@ -373,38 +375,38 @@ system.l2c.overall_misses::cpu2.data               20                       # nu
 system.l2c.overall_misses::cpu3.inst               10                       # number of overall misses
 system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
 system.l2c.overall_misses::total                  674                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     24538000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data      5612000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst      1134000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst     24533250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data      5569000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst      1122250                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu1.data        74500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst      5318500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst      5286500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu2.data       495250                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu3.inst       658250                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu3.data        74500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       37905000                       # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data      6786000                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::total       37813500                       # number of ReadReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data      6780000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data       852250                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu2.data      1087000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       978750                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total      9704000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     24538000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data     12398000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      1134000                       # number of demand (read+write) miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data       943000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total      9662250                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     24533250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data     12349000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst      1122250                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.data       926750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst      5318500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst      5286500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu2.data      1582250                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu3.inst       658250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data      1053250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        47609000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     24538000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data     12398000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      1134000                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu3.data      1017500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        47475750                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     24533250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data     12349000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst      1122250                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.data       926750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst      5318500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst      5286500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu2.data      1582250                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu3.inst       658250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data      1053250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       47609000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data      1017500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       47475750                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::cpu0.inst            588                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.inst            428                       # number of ReadReq accesses(hits+misses)
@@ -481,38 +483,38 @@ system.l2c.overall_miss_rate::cpu2.data      0.800000                       # mi
 system.l2c.overall_miss_rate::cpu3.inst      0.023256                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          0.318375                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68350.974930                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst        75600                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68337.743733                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 75256.756757                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74816.666667                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.data        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69980.263158                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69559.210526                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu2.data        70750                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu3.inst        65825                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu3.data        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 69806.629834                       # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72191.489362                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 69638.121547                       # average ReadReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72127.659574                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81562.500000                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 74076.335878                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 68350.974930                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 73797.619048                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst        75600                       # average overall miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78583.333333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 73757.633588                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 68337.743733                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 73505.952381                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 74816.666667                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 69980.263158                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 69559.210526                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu3.inst        65825                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 81019.230769                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 70636.498516                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 68350.974930                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 73797.619048                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst        75600                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 78269.230769                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 70438.798220                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 68337.743733                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 73505.952381                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 74816.666667                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 69980.263158                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 69559.210526                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu3.inst        65825                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 81019.230769                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 70636.498516                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 78269.230769                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 70438.798220                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -573,43 +575,43 @@ system.l2c.overall_mshr_misses::cpu2.data           20                       # n
 system.l2c.overall_mshr_misses::cpu3.inst            7                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::total             660                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     19975750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data      4701500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       711000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     19962500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data      4657000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       698750                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.data        62500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      4193250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      4160750                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu2.data       408750                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       431250                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu3.data        62500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     30546500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total     30444000                       # number of ReadReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       220022                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       199518                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       160016                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       200020                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::total       779576                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5616500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5606500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       701750                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       928000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       828750                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      8075000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     19975750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     10318000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst       711000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       792500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      8028750                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     19962500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data     10263500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst       698750                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.data       764250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst      4193250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst      4160750                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu2.data      1336750                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu3.inst       431250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data       891250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     38621500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     19975750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     10318000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst       711000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data       855000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     38472750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     19962500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data     10263500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst       698750                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.data       764250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst      4193250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst      4160750                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu2.data      1336750                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu3.inst       431250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data       891250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     38621500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data       855000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     38472750                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for ReadReq accesses
@@ -647,45 +649,45 @@ system.l2c.overall_mshr_miss_rate::cpu2.data     0.800000
 system.l2c.overall_mshr_miss_rate::cpu3.inst     0.016279                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total     0.311762                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55954.481793                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        71100                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55917.366947                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62932.432432                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        69875                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58239.583333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57788.194444                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61607.142857                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 57743.856333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 57550.094518                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        10001                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        59750                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59643.617021                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 69062.500000                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 61641.221374                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55954.481793                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61416.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        71100                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 66041.666667                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61288.167939                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55917.366947                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61092.261905                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        69875                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58239.583333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57788.194444                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61607.142857                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 68557.692308                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 58517.424242                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55954.481793                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61416.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        71100                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65769.230769                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 58292.045455                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55917.366947                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61092.261905                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        69875                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58239.583333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57788.194444                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 68557.692308                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 58517.424242                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65769.230769                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 58292.045455                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.toL2Bus.throughput                  1688893295                       # Throughput (bytes/s)
+system.toL2Bus.throughput                  1690157613                       # Throughput (bytes/s)
 system.toL2Bus.trans_dist::ReadReq               2536                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp              2535                       # Transaction distribution
 system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
@@ -713,153 +715,153 @@ system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side
 system.toL2Bus.tot_pkt_size::total             135488                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.data_through_bus                135488                       # Total data (bytes)
 system.toL2Bus.snoop_data_through_bus           51904                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy            1624976                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.occupancy            1624477                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              1.5                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy           2704748                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy           2708498                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             2.4                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy           1464514                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy           1467012                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             1.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           1928496                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           1928746                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             1.7                       # Layer utilization (%)
 system.toL2Bus.respLayer3.occupancy           1148249                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             1.0                       # Layer utilization (%)
 system.toL2Bus.respLayer4.occupancy           1927493                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer4.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy           1209236                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy           1209237                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization             1.1                       # Layer utilization (%)
 system.toL2Bus.respLayer6.occupancy           1936745                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy           1133252                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy           1133003                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             1.0                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                  83023                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted            80825                       # Number of conditional branches predicted
+system.cpu0.branchPred.lookups                  82981                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted            80783                       # Number of conditional branches predicted
 system.cpu0.branchPred.condIncorrect             1218                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups               80352                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                  78307                       # Number of BTB hits
+system.cpu0.branchPred.BTBLookups               80310                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                  78265                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            97.454948                       # BTB Hit Percentage
+system.cpu0.branchPred.BTBHitPct            97.453617                       # BTB Hit Percentage
 system.cpu0.branchPred.usedRAS                    512                       # Number of times the RAS was used to get a target.
 system.cpu0.branchPred.RASInCorrect               132                       # Number of incorrect RAS predictions.
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          221912                       # number of cpu cycles simulated
+system.cpu0.numCycles                          221746                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles             17233                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        492726                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      83023                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             78819                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       161746                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.icacheStallCycles             17234                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        492474                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      82981                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             78777                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       161662                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu0.fetch.SquashCycles                   3811                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles                 13929                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.BlockedCycles                 13862                       # Number of cycles fetch has spent blocked
 system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu0.fetch.PendingTrapStallCycles         1512                       # Number of stall cycles due to pending traps
 system.cpu0.fetch.CacheLines                     5835                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  493                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples            196870                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.502799                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.215097                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.IcacheSquashes                  492                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples            196720                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.503426                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.215057                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   35124     17.84%     17.84% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   80120     40.70%     58.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     578      0.29%     58.83% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                     973      0.49%     59.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     477      0.24%     59.57% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   76224     38.72%     98.29% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     570      0.29%     98.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   35058     17.82%     17.82% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   80078     40.71%     58.53% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     578      0.29%     58.82% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                     973      0.49%     59.32% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     477      0.24%     59.56% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   76182     38.73%     98.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     570      0.29%     98.57% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::7                     349      0.18%     98.75% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::8                    2455      1.25%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              196870                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.374126                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.220367                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   17821                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                15547                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   160777                       # Number of cycles decode is running
+system.cpu0.fetch.rateDist::total              196720                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.374216                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.220892                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   17819                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                15483                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   160693                       # Number of cycles decode is running
 system.cpu0.decode.UnblockCycles                  280                       # Number of cycles decode is unblocking
 system.cpu0.decode.SquashCycles                  2445                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                489900                       # Number of instructions handled by decode
+system.cpu0.decode.DecodedInsts                489648                       # Number of instructions handled by decode
 system.cpu0.rename.SquashCycles                  2445                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   18476                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                    865                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         14063                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   160426                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                  595                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                487057                       # Number of instructions processed by rename
+system.cpu0.rename.IdleCycles                   18474                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                    866                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         14003                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   160341                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                  591                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                486805                       # Number of instructions processed by rename
 system.cpu0.rename.LSQFullEvents                  216                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands             333048                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups               971305                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          733660                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               320079                       # Number of HB maps that are committed
+system.cpu0.rename.RenamedOperands             332880                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups               970801                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups          733282                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               319911                       # Number of HB maps that are committed
 system.cpu0.rename.UndoneMaps                   12969                       # Number of HB maps that are undone due to squashing
 system.cpu0.rename.serializingInsts               866                       # count of serializing insts renamed
 system.cpu0.rename.tempSerializingInsts           886                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     3628                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              155827                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              78749                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            76001                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           75817                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    407304                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.rename.skidInsts                     3624                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              155743                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              78707                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            75959                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           75775                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    407094                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu0.iq.iqNonSpecInstsAdded                910                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   404579                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued              133                       # Number of squashed instructions issued
+system.cpu0.iq.iqInstsIssued                   404367                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued              132                       # Number of squashed instructions issued
 system.cpu0.iq.iqSquashedInstsExamined          10771                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined         9747                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedOperandsExamined         9755                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.iq.iqSquashedNonSpecRemoved           351                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       196870                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.055057                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.097769                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::samples       196720                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.055546                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.097437                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              34107     17.32%     17.32% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               4943      2.51%     19.84% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              77928     39.58%     59.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              77295     39.26%     98.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1579      0.80%     99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                650      0.33%     99.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              34036     17.30%     17.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               4955      2.52%     19.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              77877     39.59%     59.41% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              77259     39.27%     98.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1573      0.80%     99.48% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                652      0.33%     99.81% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                264      0.13%     99.95% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                 87      0.04%     99.99% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                 17      0.01%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         196870                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         196720                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     57     25.68%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    53     23.87%     49.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  112     50.45%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     57     25.79%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                    52     23.53%     49.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  112     50.68%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               171055     42.28%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               170970     42.28%     42.28% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.28% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.28% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.28% # Type of FU issued
@@ -888,23 +890,23 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.28% # Ty
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.28% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.28% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              155363     38.40%     80.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              78161     19.32%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              155279     38.40%     80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              78118     19.32%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                404579                       # Type of FU issued
-system.cpu0.iq.rate                          1.823151                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        222                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000549                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads           1006383                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           419039                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       402754                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                404367                       # Type of FU issued
+system.cpu0.iq.rate                          1.823559                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        221                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000547                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads           1005807                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           418829                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       402541                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                404801                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                404588                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           75529                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           75486                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.squashedLoads         2198                       # Number of loads squashed
 system.cpu0.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
@@ -913,15 +915,15 @@ system.cpu0.iew.lsq.thread0.squashedStores         1428                       #
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked           15                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
 system.cpu0.iew.iewSquashCycles                  2445                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                    405                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   36                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             484766                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              308                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               155827                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               78749                       # Number of dispatched store instructions
+system.cpu0.iew.iewBlockCycles                    400                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   35                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             484514                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              312                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               155743                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               78707                       # Number of dispatched store instructions
 system.cpu0.iew.iewDispNonSpecInsts               798                       # Number of dispatched non-speculative instructions
 system.cpu0.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
@@ -929,80 +931,115 @@ system.cpu0.iew.memOrderViolationEvents            54                       # Nu
 system.cpu0.iew.predictedTakenIncorrect           343                       # Number of branches that were predicted taken incorrectly
 system.cpu0.iew.predictedNotTakenIncorrect         1106                       # Number of branches that were predicted not taken incorrectly
 system.cpu0.iew.branchMispredicts                1449                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               403510                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               155033                       # Number of load instructions executed
+system.cpu0.iew.iewExecutedInsts               403298                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               154949                       # Number of load instructions executed
 system.cpu0.iew.iewExecSquashedInsts             1069                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        76552                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      233092                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   80162                       # Number of branches executed
-system.cpu0.iew.exec_stores                     78059                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.818333                       # Inst execution rate
-system.cpu0.iew.wb_sent                        403084                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       402754                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   238663                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   241120                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                        76510                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      232965                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   80120                       # Number of branches executed
+system.cpu0.iew.exec_stores                     78016                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.818739                       # Inst execution rate
+system.cpu0.iew.wb_sent                        402871                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       402541                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   238524                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   240975                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      1.814927                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.989810                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      1.815325                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.989829                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu0.commit.commitSquashedInsts          12269                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu0.commit.branchMispredicts             1218                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       194425                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.430089                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.136483                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::samples       194275                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.430668                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.136401                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        34537     17.76%     17.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        79950     41.12%     58.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         2378      1.22%     60.11% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          690      0.35%     60.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          530      0.27%     60.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        75328     38.74%     99.48% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          457      0.24%     99.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          248      0.13%     99.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          307      0.16%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        34469     17.74%     17.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        79913     41.13%     58.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         2377      1.22%     60.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          686      0.35%     60.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          532      0.27%     60.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        75283     38.75%     99.48% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          460      0.24%     99.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          250      0.13%     99.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          305      0.16%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       194425                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              472470                       # Number of instructions committed
-system.cpu0.commit.committedOps                472470                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total       194275                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts              472218                       # Number of instructions committed
+system.cpu0.commit.committedOps                472218                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        230950                       # Number of memory references committed
-system.cpu0.commit.loads                       153629                       # Number of loads committed
+system.cpu0.commit.refs                        230824                       # Number of memory references committed
+system.cpu0.commit.loads                       153545                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     79208                       # Number of branches committed
+system.cpu0.commit.branches                     79166                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   318410                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   318242                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events                  307                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::No_OpClass        75898     16.07%     16.07% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu          165412     35.03%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead         153629     32.53%     83.63% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite         77279     16.37%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::total           472218                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events                  305                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                      677696                       # The number of ROB reads
-system.cpu0.rob.rob_writes                     971940                       # The number of ROB writes
+system.cpu0.rob.rob_reads                      677296                       # The number of ROB reads
+system.cpu0.rob.rob_writes                     971436                       # The number of ROB writes
 system.cpu0.timesIdled                            327                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          25042                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     396446                       # Number of Instructions Simulated
-system.cpu0.committedOps                       396446                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total               396446                       # Number of Instructions Simulated
-system.cpu0.cpi                              0.559753                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.559753                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.786501                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.786501                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  721878                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 325337                       # number of integer regfile writes
+system.cpu0.idleCycles                          25026                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     396236                       # Number of Instructions Simulated
+system.cpu0.committedOps                       396236                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total               396236                       # Number of Instructions Simulated
+system.cpu0.cpi                              0.559631                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.559631                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.786891                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.786891                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  721496                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 325166                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 234915                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 234788                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
 system.cpu0.icache.tags.replacements              297                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          241.280038                       # Cycle average of tags in use
+system.cpu0.icache.tags.tagsinuse          241.323737                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs               5079                       # Total number of references to valid blocks.
 system.cpu0.icache.tags.sampled_refs              587                       # Sample count of references to valid blocks.
 system.cpu0.icache.tags.avg_refs             8.652470                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.280038                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471250                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.471250                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.323737                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471335                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.471335                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          290                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
@@ -1022,12 +1059,12 @@ system.cpu0.icache.demand_misses::cpu0.inst          756                       #
 system.cpu0.icache.demand_misses::total           756                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst          756                       # number of overall misses
 system.cpu0.icache.overall_misses::total          756                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     35676245                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     35676245                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     35676245                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     35676245                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     35676245                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     35676245                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     35655495                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     35655495                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     35655495                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     35655495                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     35655495                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     35655495                       # number of overall miss cycles
 system.cpu0.icache.ReadReq_accesses::cpu0.inst         5835                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total         5835                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.demand_accesses::cpu0.inst         5835                       # number of demand (read+write) accesses
@@ -1040,12 +1077,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst     0.129563
 system.cpu0.icache.demand_miss_rate::total     0.129563                       # miss rate for demand accesses
 system.cpu0.icache.overall_miss_rate::cpu0.inst     0.129563                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     0.129563                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47190.800265                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 47190.800265                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47190.800265                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 47190.800265                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47190.800265                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 47190.800265                       # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47163.353175                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 47163.353175                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47163.353175                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 47163.353175                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47163.353175                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 47163.353175                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1066,119 +1103,119 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst          588
 system.cpu0.icache.demand_mshr_misses::total          588                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu0.inst          588                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total          588                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     27430752                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     27430752                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     27430752                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     27430752                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     27430752                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     27430752                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     27420002                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     27420002                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     27420002                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     27420002                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     27420002                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     27420002                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.100771                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total     0.100771                       # mshr miss rate for demand accesses
 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total     0.100771                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46650.938776                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46650.938776                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46650.938776                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 46650.938776                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46650.938776                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 46650.938776                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46632.656463                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46632.656463                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46632.656463                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 46632.656463                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46632.656463                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 46632.656463                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          142.009454                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             155675                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          142.026535                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             155594                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              170                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           915.735294                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           915.258824                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.009454                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277362                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.277362                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.026535                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277396                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.277396                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.328125                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           627368                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          627368                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        79025                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          79025                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        76734                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         76734                       # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses           627036                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          627036                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data        78986                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          78986                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        76692                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         76692                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       155759                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          155759                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       155759                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         155759                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          418                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          418                       # number of ReadReq misses
+system.cpu0.dcache.demand_hits::cpu0.data       155678                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          155678                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       155678                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         155678                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          416                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          416                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data          545                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total          545                       # number of WriteReq misses
 system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
 system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          963                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           963                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          963                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          963                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     13454697                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     13454697                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     32621759                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     32621759                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data          961                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total           961                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data          961                       # number of overall misses
+system.cpu0.dcache.overall_misses::total          961                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     13375931                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     13375931                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     32683256                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     32683256                       # number of WriteReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       404750                       # number of SwapReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::total       404750                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     46076456                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     46076456                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     46076456                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     46076456                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        79443                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        79443                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        77279                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        77279                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu0.data     46059187                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     46059187                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     46059187                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     46059187                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        79402                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        79402                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        77237                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        77237                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       156722                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       156722                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       156722                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       156722                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005262                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.005262                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007052                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007052                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data       156639                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       156639                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       156639                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       156639                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005239                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.005239                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007056                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007056                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006145                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.006145                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006145                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.006145                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32188.270335                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 32188.270335                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59856.438532                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 59856.438532                       # average WriteReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006135                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.006135                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006135                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.006135                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32153.680288                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 32153.680288                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59969.277064                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 59969.277064                       # average WriteReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524                       # average SwapReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47846.787124                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 47846.787124                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47846.787124                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 47846.787124                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          524                       # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47928.394381                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 47928.394381                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47928.394381                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 47928.394381                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          512                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               20                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    26.200000                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    24.380952                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          230                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          230                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          228                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          228                       # number of ReadReq MSHR hits
 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          370                       # number of WriteReq MSHR hits
 system.cpu0.dcache.WriteReq_mshr_hits::total          370                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          600                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          600                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          600                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          600                       # number of overall MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          598                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          598                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          598                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          598                       # number of overall MSHR hits
 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          188                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_misses::total          188                       # number of ReadReq MSHR misses
 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          175                       # number of WriteReq MSHR misses
@@ -1189,122 +1226,122 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data          363
 system.cpu0.dcache.demand_mshr_misses::total          363                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu0.data          363                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::total          363                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6237508                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6237508                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7264228                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7264228                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6192510                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6192510                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7258228                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7258228                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       361250                       # number of SwapReq MSHR miss cycles
 system.cpu0.dcache.SwapReq_mshr_miss_latency::total       361250                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     13501736                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     13501736                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     13501736                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     13501736                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002366                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002366                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002265                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002265                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     13450738                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     13450738                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     13450738                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     13450738                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002368                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002368                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002266                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002266                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002316                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002316                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002316                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002316                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33178.234043                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33178.234043                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41509.874286                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41509.874286                       # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002317                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002317                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002317                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002317                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32938.882979                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32938.882979                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41475.588571                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41475.588571                       # average WriteReq mshr miss latency
 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952                       # average SwapReq mshr miss latency
 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37194.865014                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37194.865014                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37194.865014                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37194.865014                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37054.374656                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37054.374656                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37054.374656                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37054.374656                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                  49230                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted            46482                       # Number of conditional branches predicted
+system.cpu1.branchPred.lookups                  49222                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted            46474                       # Number of conditional branches predicted
 system.cpu1.branchPred.condIncorrect             1275                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups               43125                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                  42318                       # Number of BTB hits
+system.cpu1.branchPred.BTBLookups               43117                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                  42310                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            98.128696                       # BTB Hit Percentage
+system.cpu1.branchPred.BTBHitPct            98.128348                       # BTB Hit Percentage
 system.cpu1.branchPred.usedRAS                    644                       # Number of times the RAS was used to get a target.
 system.cpu1.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu1.numCycles                          177729                       # number of cpu cycles simulated
+system.cpu1.numCycles                          177641                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles             30707                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        271510                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      49230                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             42962                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                        98061                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.icacheStallCycles             30689                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        271480                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      49222                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             42954                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                        98036                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu1.fetch.SquashCycles                   3712                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles                 35852                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.BlockedCycles                 35816                       # Number of cycles fetch has spent blocked
 system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles         7757                       # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.NoActiveThreadStallCycles         7751                       # Number of stall cycles due to no active thread to fetch from
 system.cpu1.fetch.PendingTrapStallCycles          775                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    22354                       # Number of cache lines fetched
+system.cpu1.fetch.CacheLines                    22336                       # Number of cache lines fetched
 system.cpu1.fetch.IcacheSquashes                  259                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            175517                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.546916                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.089154                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::samples            175432                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.547494                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.089471                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   77456     44.13%     44.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   50516     28.78%     72.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    7423      4.23%     77.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3189      1.82%     78.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     704      0.40%     79.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   30974     17.65%     97.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1193      0.68%     97.69% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   77396     44.12%     44.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   50499     28.79%     72.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    7414      4.23%     77.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3189      1.82%     78.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     704      0.40%     79.35% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   30975     17.66%     97.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1193      0.68%     97.68% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::7                     759      0.43%     98.12% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::8                    3303      1.88%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              175517                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.276995                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.527663                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   37188                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                31008                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                    90874                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 6330                       # Number of cycles decode is unblocking
+system.cpu1.fetch.rateDist::total              175432                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.277087                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.528251                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   37161                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                30981                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    90858                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 6321                       # Number of cycles decode is unblocking
 system.cpu1.decode.SquashCycles                  2360                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                267842                       # Number of instructions handled by decode
+system.cpu1.decode.DecodedInsts                267812                       # Number of instructions handled by decode
 system.cpu1.rename.SquashCycles                  2360                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   37871                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  18552                       # Number of cycles rename is blocking
+system.cpu1.rename.IdleCycles                   37844                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  18525                       # Number of cycles rename is blocking
 system.cpu1.rename.serializeStallCycles         11702                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    84813                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                12462                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                265527                       # Number of instructions processed by rename
+system.cpu1.rename.RunCycles                    84806                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                12444                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                265497                       # Number of instructions processed by rename
 system.cpu1.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
 system.cpu1.rename.LSQFullEvents                   21                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands             184379                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               502490                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          391665                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               171551                       # Number of HB maps that are committed
+system.cpu1.rename.RenamedOperands             184374                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               502466                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          391647                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               171546                       # Number of HB maps that are committed
 system.cpu1.rename.UndoneMaps                   12828                       # Number of HB maps that are undone due to squashing
 system.cpu1.rename.serializingInsts              1100                       # count of serializing insts renamed
 system.cpu1.rename.tempSerializingInsts          1220                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    15186                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               73774                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              34232                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            35732                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           29187                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    218298                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               7639                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   221677                       # Number of instructions issued
+system.cpu1.rename.skidInsts                    15168                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               73767                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              34233                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            35724                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           29188                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    218285                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               7630                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   221655                       # Number of instructions issued
 system.cpu1.iq.iqSquashedInstsIssued               99                       # Number of squashed instructions issued
 system.cpu1.iq.iqSquashedInstsExamined          10737                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu1.iq.iqSquashedOperandsExamined        10712                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu1.iq.iqSquashedNonSpecRemoved           591                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       175517                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.262994                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.299330                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::samples       175432                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.263481                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.299438                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              74868     42.66%     42.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              26303     14.99%     57.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              34475     19.64%     77.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              35103     20.00%     97.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              74808     42.64%     42.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              26276     14.98%     57.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              34476     19.65%     77.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              35104     20.01%     97.28% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::4               3248      1.85%     99.13% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::5               1161      0.66%     99.80% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                252      0.14%     99.94% # Number of insts issued each cycle
@@ -1313,7 +1350,7 @@ system.cpu1.iq.issued_per_cycle::8                 57      0.03%    100.00% # Nu
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         175517                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         175432                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IntAlu                     12      4.51%      4.51% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IntMult                     0      0.00%      4.51% # attempts to use FU when none available
@@ -1349,7 +1386,7 @@ system.cpu1.iq.fu_full::MemWrite                  210     78.95%    100.00% # at
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               108767     49.07%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               108760     49.07%     49.07% # Type of FU issued
 system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.07% # Type of FU issued
 system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.07% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.07% # Type of FU issued
@@ -1378,23 +1415,23 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.07% # Ty
 system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.07% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.07% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               79372     35.81%     84.87% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              33538     15.13%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               79356     35.80%     84.87% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              33539     15.13%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                221677                       # Type of FU issued
-system.cpu1.iq.rate                          1.247275                       # Inst issue rate
+system.cpu1.iq.FU_type_0::total                221655                       # Type of FU issued
+system.cpu1.iq.rate                          1.247769                       # Inst issue rate
 system.cpu1.iq.fu_busy_cnt                        266                       # FU busy when requested
 system.cpu1.iq.fu_busy_rate                  0.001200                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            619236                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           236717                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       219849                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.int_inst_queue_reads            619107                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           236695                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       219827                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                221943                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                221921                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           28929                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           28930                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.squashedLoads         2394                       # Number of loads squashed
 system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
@@ -1408,10 +1445,10 @@ system.cpu1.iew.iewIdleCycles                       0                       # Nu
 system.cpu1.iew.iewSquashCycles                  2360                       # Number of cycles IEW is squashing
 system.cpu1.iew.iewBlockCycles                    686                       # Number of cycles IEW is blocking
 system.cpu1.iew.iewUnblockCycles                   42                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             262595                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispatchedInsts             262565                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts              349                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                73774                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               34232                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispLoadInsts                73767                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               34233                       # Number of dispatched store instructions
 system.cpu1.iew.iewDispNonSpecInsts              1056                       # Number of dispatched non-speculative instructions
 system.cpu1.iew.iewIQFullEvents                    42                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
@@ -1419,123 +1456,158 @@ system.cpu1.iew.memOrderViolationEvents            43                       # Nu
 system.cpu1.iew.predictedTakenIncorrect           467                       # Number of branches that were predicted taken incorrectly
 system.cpu1.iew.predictedNotTakenIncorrect          918                       # Number of branches that were predicted not taken incorrectly
 system.cpu1.iew.branchMispredicts                1385                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               220501                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                72766                       # Number of load instructions executed
+system.cpu1.iew.iewExecutedInsts               220479                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                72759                       # Number of load instructions executed
 system.cpu1.iew.iewExecSquashedInsts             1176                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        36658                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      106223                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   45902                       # Number of branches executed
-system.cpu1.iew.exec_stores                     33457                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.240659                       # Inst execution rate
-system.cpu1.iew.wb_sent                        220134                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       219849                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   122957                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   127616                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        36650                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      106217                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   45894                       # Number of branches executed
+system.cpu1.iew.exec_stores                     33458                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.241149                       # Inst execution rate
+system.cpu1.iew.wb_sent                        220112                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       219827                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   122951                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   127610                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      1.236990                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.963492                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      1.237479                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.963490                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu1.commit.commitSquashedInsts          12326                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           7048                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.commitNonSpecStalls           7039                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu1.commit.branchMispredicts             1275                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       165400                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.513005                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.970213                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::samples       165321                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.513546                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.970448                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        73929     44.70%     44.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        44053     26.63%     71.33% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         6103      3.69%     75.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         7962      4.81%     79.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1564      0.95%     80.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        29500     17.84%     98.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        73866     44.68%     44.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        44045     26.64%     71.32% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         6103      3.69%     75.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         7953      4.81%     79.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1564      0.95%     80.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        29501     17.84%     98.62% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::6          477      0.29%     98.90% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::7         1008      0.61%     99.51% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::8          804      0.49%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       165400                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              250251                       # Number of instructions committed
-system.cpu1.commit.committedOps                250251                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total       165321                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts              250221                       # Number of instructions committed
+system.cpu1.commit.committedOps                250221                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        104168                       # Number of memory references committed
-system.cpu1.commit.loads                        71380                       # Number of loads committed
-system.cpu1.commit.membars                       6331                       # Number of memory barriers committed
-system.cpu1.commit.branches                     45080                       # Number of branches committed
+system.cpu1.commit.refs                        104162                       # Number of memory references committed
+system.cpu1.commit.loads                        71373                       # Number of loads committed
+system.cpu1.commit.membars                       6322                       # Number of memory barriers committed
+system.cpu1.commit.branches                     45072                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   171367                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   171353                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass        35859     14.33%     14.33% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu          103878     41.51%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead          77695     31.05%     86.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite         32789     13.10%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::total           250221                       # Class of committed instruction
 system.cpu1.commit.bw_lim_events                  804                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                      426586                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     527520                       # The number of ROB writes
+system.cpu1.rob.rob_reads                      426477                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     527460                       # The number of ROB writes
 system.cpu1.timesIdled                            216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           2212                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       44181                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     208053                       # Number of Instructions Simulated
-system.cpu1.committedOps                       208053                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total               208053                       # Number of Instructions Simulated
-system.cpu1.cpi                              0.854249                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.854249                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.170619                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.170619                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  377223                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 176309                       # number of integer regfile writes
+system.cpu1.idleCycles                           2209                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                       44103                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                     208040                       # Number of Instructions Simulated
+system.cpu1.committedOps                       208040                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total               208040                       # Number of Instructions Simulated
+system.cpu1.cpi                              0.853879                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.853879                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.171126                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.171126                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  377205                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 176304                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 107781                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 107775                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu1.icache.tags.replacements              318                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           76.722565                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs              21879                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse           76.769709                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs              21861                       # Total number of references to valid blocks.
 system.cpu1.icache.tags.sampled_refs              428                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            51.119159                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            51.077103                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.722565                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149849                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.149849                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.769709                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149941                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.149941                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses            22782                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses           22782                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst        21879                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          21879                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        21879                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           21879                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        21879                       # number of overall hits
-system.cpu1.icache.overall_hits::total          21879                       # number of overall hits
+system.cpu1.icache.tags.tag_accesses            22764                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses           22764                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst        21861                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          21861                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        21861                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           21861                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        21861                       # number of overall hits
+system.cpu1.icache.overall_hits::total          21861                       # number of overall hits
 system.cpu1.icache.ReadReq_misses::cpu1.inst          475                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total          475                       # number of ReadReq misses
 system.cpu1.icache.demand_misses::cpu1.inst          475                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total           475                       # number of demand (read+write) misses
 system.cpu1.icache.overall_misses::cpu1.inst          475                       # number of overall misses
 system.cpu1.icache.overall_misses::total          475                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7157495                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      7157495                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      7157495                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      7157495                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      7157495                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      7157495                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        22354                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        22354                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        22354                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        22354                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        22354                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        22354                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021249                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.021249                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021249                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.021249                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021249                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.021249                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15068.410526                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15068.410526                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15068.410526                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15068.410526                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15068.410526                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15068.410526                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7146245                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total      7146245                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst      7146245                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total      7146245                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst      7146245                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total      7146245                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        22336                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        22336                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        22336                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        22336                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        22336                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        22336                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021266                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.021266                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021266                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.021266                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021266                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.021266                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15044.726316                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15044.726316                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15044.726316                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15044.726316                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15044.726316                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15044.726316                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
@@ -1556,49 +1628,49 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst          428
 system.cpu1.icache.demand_mshr_misses::total          428                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          428                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          428                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5706004                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      5706004                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5706004                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      5706004                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5706004                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      5706004                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.019146                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.019146                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.019146                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.019146                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.019146                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.019146                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13331.785047                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13331.785047                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13331.785047                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13331.785047                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13331.785047                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13331.785047                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5694254                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      5694254                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5694254                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      5694254                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5694254                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      5694254                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.019162                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.019162                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.019162                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.019162                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.019162                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.019162                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13304.331776                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13304.331776                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13304.331776                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13304.331776                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13304.331776                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13304.331776                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           23.630187                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              38790                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse           23.645460                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              38791                       # Total number of references to valid blocks.
 system.cpu1.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs          1385.357143                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs          1385.392857                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    23.630187                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.046153                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.046153                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    23.645460                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.046183                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.046183                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           306681                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          306681                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        43485                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          43485                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        32585                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         32585                       # number of WriteReq hits
+system.cpu1.dcache.tags.tag_accesses           306653                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          306653                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data        43477                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          43477                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        32586                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         32586                       # number of WriteReq hits
 system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
 system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        76070                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           76070                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        76070                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          76070                       # number of overall hits
+system.cpu1.dcache.demand_hits::cpu1.data        76063                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           76063                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        76063                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          76063                       # number of overall hits
 system.cpu1.dcache.ReadReq_misses::cpu1.data          336                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total          336                       # number of ReadReq misses
 system.cpu1.dcache.WriteReq_misses::cpu1.data          132                       # number of WriteReq misses
@@ -1609,46 +1681,46 @@ system.cpu1.dcache.demand_misses::cpu1.data          468                       #
 system.cpu1.dcache.demand_misses::total           468                       # number of demand (read+write) misses
 system.cpu1.dcache.overall_misses::cpu1.data          468                       # number of overall misses
 system.cpu1.dcache.overall_misses::total          468                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4179135                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      4179135                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4177635                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      4177635                       # number of ReadReq miss cycles
 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2763761                       # number of WriteReq miss cycles
 system.cpu1.dcache.WriteReq_miss_latency::total      2763761                       # number of WriteReq miss cycles
 system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       521507                       # number of SwapReq miss cycles
 system.cpu1.dcache.SwapReq_miss_latency::total       521507                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      6942896                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      6942896                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      6942896                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      6942896                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        43821                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        43821                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        32717                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        32717                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.demand_miss_latency::cpu1.data      6941396                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total      6941396                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data      6941396                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total      6941396                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        43813                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        43813                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        32718                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        32718                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.SwapReq_accesses::cpu1.data           71                       # number of SwapReq accesses(hits+misses)
 system.cpu1.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        76538                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        76538                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        76538                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        76538                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.007668                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.007668                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004035                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.004035                       # miss rate for WriteReq accesses
+system.cpu1.dcache.demand_accesses::cpu1.data        76531                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        76531                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        76531                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        76531                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.007669                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.007669                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004034                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.004034                       # miss rate for WriteReq accesses
 system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.802817                       # miss rate for SwapReq accesses
 system.cpu1.dcache.SwapReq_miss_rate::total     0.802817                       # miss rate for SwapReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006115                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     0.006115                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006115                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     0.006115                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12437.901786                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12437.901786                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12433.437500                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12433.437500                       # average ReadReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333                       # average WriteReq miss latency
 system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  9149.245614                       # average SwapReq miss latency
 system.cpu1.dcache.SwapReq_avg_miss_latency::total  9149.245614                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14835.247863                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14835.247863                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14835.247863                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14835.247863                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14832.042735                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14832.042735                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14832.042735                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14832.042735                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1675,16 +1747,16 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data          260
 system.cpu1.dcache.demand_mshr_misses::total          260                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.overall_mshr_misses::cpu1.data          260                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_misses::total          260                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1078019                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1078019                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1076519                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1076519                       # number of ReadReq MSHR miss cycles
 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1313739                       # number of WriteReq MSHR miss cycles
 system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1313739                       # number of WriteReq MSHR miss cycles
 system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       407493                       # number of SwapReq MSHR miss cycles
 system.cpu1.dcache.SwapReq_mshr_miss_latency::total       407493                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2391758                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      2391758                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2391758                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      2391758                       # number of overall MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2390258                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      2390258                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2390258                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      2390258                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003606                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003606                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003118                       # mshr miss rate for WriteReq accesses
@@ -1695,110 +1767,110 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003397
 system.cpu1.dcache.demand_mshr_miss_rate::total     0.003397                       # mshr miss rate for demand accesses
 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003397                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::total     0.003397                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  6822.905063                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  6822.905063                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  6813.411392                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  6813.411392                       # average ReadReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118                       # average WriteReq mshr miss latency
 system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data         7149                       # average SwapReq mshr miss latency
 system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total         7149                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  9199.069231                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total  9199.069231                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  9199.069231                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total  9199.069231                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  9193.300000                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total  9193.300000                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  9193.300000                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total  9193.300000                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups                  47736                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted            45029                       # Number of conditional branches predicted
+system.cpu2.branchPred.lookups                  47728                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted            45021                       # Number of conditional branches predicted
 system.cpu2.branchPred.condIncorrect             1300                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups               41576                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                  40869                       # Number of BTB hits
+system.cpu2.branchPred.BTBLookups               41568                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                  40861                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            98.299500                       # BTB Hit Percentage
+system.cpu2.branchPred.BTBHitPct            98.299172                       # BTB Hit Percentage
 system.cpu2.branchPred.usedRAS                    682                       # Number of times the RAS was used to get a target.
 system.cpu2.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                          177364                       # number of cpu cycles simulated
+system.cpu2.numCycles                          177276                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu2.fetch.icacheStallCycles             30843                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        263253                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      47736                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             41551                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                        94921                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.Insts                        263204                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      47728                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             41543                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                        94904                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu2.fetch.SquashCycles                   3824                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles                 35042                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.BlockedCycles                 35041                       # Number of cycles fetch has spent blocked
 system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles         7755                       # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.NoActiveThreadStallCycles         7749                       # Number of stall cycles due to no active thread to fetch from
 system.cpu2.fetch.PendingTrapStallCycles          807                       # Number of stall cycles due to pending traps
 system.cpu2.fetch.CacheLines                    21784                       # Number of cache lines fetched
 system.cpu2.fetch.IcacheSquashes                  264                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            171818                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.532162                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.088026                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::samples            171794                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.532091                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.088011                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   76897     44.75%     44.75% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   48842     28.43%     73.18% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   76890     44.76%     44.76% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   48833     28.43%     73.18% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::2                    7151      4.16%     77.34% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::3                    3183      1.85%     79.20% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::4                     686      0.40%     79.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   29853     17.37%     96.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1160      0.68%     97.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   29845     17.37%     96.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1160      0.68%     97.64% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::7                     777      0.45%     98.10% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::8                    3269      1.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              171818                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.269141                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.484253                       # Number of inst fetches per cycle
+system.cpu2.fetch.rateDist::total              171794                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.269230                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.484713                       # Number of inst fetches per cycle
 system.cpu2.decode.IdleCycles                   36742                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                30807                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    88098                       # Number of cycles decode is running
+system.cpu2.decode.BlockedCycles                30806                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                    88081                       # Number of cycles decode is running
 system.cpu2.decode.UnblockCycles                 5970                       # Number of cycles decode is unblocking
 system.cpu2.decode.SquashCycles                  2446                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                259780                       # Number of instructions handled by decode
+system.cpu2.decode.DecodedInsts                259729                       # Number of instructions handled by decode
 system.cpu2.rename.SquashCycles                  2446                       # Number of cycles rename is squashing
 system.cpu2.rename.IdleCycles                   37466                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  17719                       # Number of cycles rename is blocking
+system.cpu2.rename.BlockCycles                  17718                       # Number of cycles rename is blocking
 system.cpu2.rename.serializeStallCycles         12322                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    82368                       # Number of cycles rename is running
+system.cpu2.rename.RunCycles                    82351                       # Number of cycles rename is running
 system.cpu2.rename.UnblockCycles                11742                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                257506                       # Number of instructions processed by rename
+system.cpu2.rename.RenamedInsts                257457                       # Number of instructions processed by rename
 system.cpu2.rename.LSQFullEvents                   21                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands             179566                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               487666                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          380584                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               166435                       # Number of HB maps that are committed
+system.cpu2.rename.RenamedOperands             179534                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               487570                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          380512                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               166403                       # Number of HB maps that are committed
 system.cpu2.rename.UndoneMaps                   13131                       # Number of HB maps that are undone due to squashing
 system.cpu2.rename.serializingInsts              1114                       # count of serializing insts renamed
 system.cpu2.rename.tempSerializingInsts          1238                       # count of temporary serializing insts renamed
 system.cpu2.rename.skidInsts                    14439                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               71199                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              33061                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            34327                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           28016                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    212074                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.memDep0.insertedLoads               71183                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              33053                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            34319                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           28008                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    212034                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu2.iq.iqNonSpecInstsAdded               7370                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   214906                       # Number of instructions issued
+system.cpu2.iq.iqInstsIssued                   214866                       # Number of instructions issued
 system.cpu2.iq.iqSquashedInstsIssued              106                       # Number of squashed instructions issued
 system.cpu2.iq.iqSquashedInstsExamined          11214                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu2.iq.iqSquashedOperandsExamined        11199                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu2.iq.iqSquashedNonSpecRemoved           648                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       171818                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.250777                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.303706                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::samples       171794                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.250719                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.303691                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              74494     43.36%     43.36% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              25338     14.75%     58.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              33284     19.37%     77.48% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              33913     19.74%     97.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3241      1.89%     99.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1161      0.68%     99.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              74486     43.36%     43.36% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              25336     14.75%     58.11% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              33280     19.37%     77.48% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              33902     19.73%     97.21% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3243      1.89%     99.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1160      0.68%     99.77% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::6                274      0.16%     99.93% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::7                 56      0.03%     99.97% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         171818                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         171794                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IntAlu                     17      6.18%      6.18% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.18% # attempts to use FU when none available
@@ -1834,7 +1906,7 @@ system.cpu2.iq.fu_full::MemWrite                  210     76.36%    100.00% # at
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               106166     49.40%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               106150     49.40%     49.40% # Type of FU issued
 system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.40% # Type of FU issued
 system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.40% # Type of FU issued
 system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.40% # Type of FU issued
@@ -1863,23 +1935,23 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.40% # Ty
 system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.40% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.40% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               76377     35.54%     84.94% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              32363     15.06%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               76361     35.54%     84.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              32355     15.06%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                214906                       # Type of FU issued
-system.cpu2.iq.rate                          1.211666                       # Inst issue rate
+system.cpu2.iq.FU_type_0::total                214866                       # Type of FU issued
+system.cpu2.iq.rate                          1.212042                       # Inst issue rate
 system.cpu2.iq.fu_busy_cnt                        275                       # FU busy when requested
 system.cpu2.iq.fu_busy_rate                  0.001280                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            602011                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           230706                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       213087                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.int_inst_queue_reads            601907                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           230666                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       213047                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                215181                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                215141                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           27728                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           27720                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.squashedLoads         2543                       # Number of loads squashed
 system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
@@ -1891,12 +1963,12 @@ system.cpu2.iew.lsq.thread0.rescheduledLoads            0
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
 system.cpu2.iew.iewSquashCycles                  2446                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                    917                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewBlockCycles                    916                       # Number of cycles IEW is blocking
 system.cpu2.iew.iewUnblockCycles                   52                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             254656                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispatchedInsts             254607                       # Number of instructions dispatched to IQ
 system.cpu2.iew.iewDispSquashedInsts              365                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                71199                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               33061                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispLoadInsts                71183                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               33053                       # Number of dispatched store instructions
 system.cpu2.iew.iewDispNonSpecInsts              1074                       # Number of dispatched non-speculative instructions
 system.cpu2.iew.iewIQFullEvents                    52                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
@@ -1904,81 +1976,116 @@ system.cpu2.iew.memOrderViolationEvents            48                       # Nu
 system.cpu2.iew.predictedTakenIncorrect           458                       # Number of branches that were predicted taken incorrectly
 system.cpu2.iew.predictedNotTakenIncorrect          967                       # Number of branches that were predicted not taken incorrectly
 system.cpu2.iew.branchMispredicts                1425                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               213756                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                70098                       # Number of load instructions executed
+system.cpu2.iew.iewExecutedInsts               213716                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                70082                       # Number of load instructions executed
 system.cpu2.iew.iewExecSquashedInsts             1150                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        35212                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      102378                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   44395                       # Number of branches executed
-system.cpu2.iew.exec_stores                     32280                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.205183                       # Inst execution rate
-system.cpu2.iew.wb_sent                        213374                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       213087                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   119148                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   123853                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        35203                       # number of nop insts executed
+system.cpu2.iew.exec_refs                      102354                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   44387                       # Number of branches executed
+system.cpu2.iew.exec_stores                     32272                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.205555                       # Inst execution rate
+system.cpu2.iew.wb_sent                        213334                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       213047                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                   119124                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                   123829                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.201411                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.962011                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.201781                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.962004                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts          12898                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitSquashedInsts          12897                       # The number of squashed insts skipped by commit
 system.cpu2.commit.commitNonSpecStalls           6722                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu2.commit.branchMispredicts             1300                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       161617                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.495857                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.966536                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::samples       161599                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.495727                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.966465                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        73208     45.30%     45.30% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        42532     26.32%     71.61% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        73205     45.30%     45.30% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        42525     26.32%     71.62% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::2         6095      3.77%     75.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         7628      4.72%     80.10% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         7628      4.72%     80.11% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::4         1558      0.96%     81.07% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        28303     17.51%     98.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          470      0.29%     98.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        28296     17.51%     98.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          469      0.29%     98.87% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::7         1001      0.62%     99.49% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::8          822      0.51%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       161617                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              241756                       # Number of instructions committed
-system.cpu2.commit.committedOps                241756                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total       161599                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts              241708                       # Number of instructions committed
+system.cpu2.commit.committedOps                241708                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                        100248                       # Number of memory references committed
-system.cpu2.commit.loads                        68656                       # Number of loads committed
+system.cpu2.commit.refs                        100224                       # Number of memory references committed
+system.cpu2.commit.loads                        68640                       # Number of loads committed
 system.cpu2.commit.membars                       6003                       # Number of memory barriers committed
-system.cpu2.commit.branches                     43556                       # Number of branches committed
+system.cpu2.commit.branches                     43548                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   165922                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   165890                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        34333     14.20%     14.20% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu          101148     41.85%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead          74643     30.88%     86.93% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite         31584     13.07%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::total           241708                       # Class of committed instruction
 system.cpu2.commit.bw_lim_events                  822                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                      414862                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     511759                       # The number of ROB writes
+system.cpu2.rob.rob_reads                      414795                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     511661                       # The number of ROB writes
 system.cpu2.timesIdled                            225                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           5546                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       44546                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     201412                       # Number of Instructions Simulated
-system.cpu2.committedOps                       201412                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total               201412                       # Number of Instructions Simulated
-system.cpu2.cpi                              0.880603                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.880603                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.135586                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.135586                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  365854                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 171387                       # number of integer regfile writes
+system.cpu2.idleCycles                           5482                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                       44468                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                     201372                       # Number of Instructions Simulated
+system.cpu2.committedOps                       201372                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total               201372                       # Number of Instructions Simulated
+system.cpu2.cpi                              0.880341                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.880341                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.135924                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.135924                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  365782                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 171355                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 103940                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                 103916                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu2.icache.tags.replacements              317                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           82.194037                       # Cycle average of tags in use
+system.cpu2.icache.tags.tagsinuse           82.236907                       # Cycle average of tags in use
 system.cpu2.icache.tags.total_refs              21297                       # Total number of references to valid blocks.
 system.cpu2.icache.tags.sampled_refs              425                       # Sample count of references to valid blocks.
 system.cpu2.icache.tags.avg_refs            50.110588                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    82.194037                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.160535                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.160535                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    82.236907                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.160619                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.160619                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_task_id_blocks::1024          108                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
@@ -1997,12 +2104,12 @@ system.cpu2.icache.demand_misses::cpu2.inst          487                       #
 system.cpu2.icache.demand_misses::total           487                       # number of demand (read+write) misses
 system.cpu2.icache.overall_misses::cpu2.inst          487                       # number of overall misses
 system.cpu2.icache.overall_misses::total          487                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     11553239                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total     11553239                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst     11553239                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total     11553239                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst     11553239                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total     11553239                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     11521239                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total     11521239                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst     11521239                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total     11521239                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst     11521239                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total     11521239                       # number of overall miss cycles
 system.cpu2.icache.ReadReq_accesses::cpu2.inst        21784                       # number of ReadReq accesses(hits+misses)
 system.cpu2.icache.ReadReq_accesses::total        21784                       # number of ReadReq accesses(hits+misses)
 system.cpu2.icache.demand_accesses::cpu2.inst        21784                       # number of demand (read+write) accesses
@@ -2015,12 +2122,12 @@ system.cpu2.icache.demand_miss_rate::cpu2.inst     0.022356
 system.cpu2.icache.demand_miss_rate::total     0.022356                       # miss rate for demand accesses
 system.cpu2.icache.overall_miss_rate::cpu2.inst     0.022356                       # miss rate for overall accesses
 system.cpu2.icache.overall_miss_rate::total     0.022356                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23723.283368                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 23723.283368                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23723.283368                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 23723.283368                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23723.283368                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 23723.283368                       # average overall miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23657.574949                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 23657.574949                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23657.574949                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 23657.574949                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23657.574949                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 23657.574949                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs           85                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -2041,50 +2148,50 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst          425
 system.cpu2.icache.demand_mshr_misses::total          425                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.overall_mshr_misses::cpu2.inst          425                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_misses::total          425                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      9258007                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      9258007                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      9258007                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      9258007                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      9258007                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      9258007                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      9226007                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      9226007                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      9226007                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      9226007                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      9226007                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      9226007                       # number of overall MSHR miss cycles
 system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.019510                       # mshr miss rate for ReadReq accesses
 system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.019510                       # mshr miss rate for ReadReq accesses
 system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.019510                       # mshr miss rate for demand accesses
 system.cpu2.icache.demand_mshr_miss_rate::total     0.019510                       # mshr miss rate for demand accesses
 system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.019510                       # mshr miss rate for overall accesses
 system.cpu2.icache.overall_mshr_miss_rate::total     0.019510                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21783.545882                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21783.545882                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21783.545882                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 21783.545882                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21783.545882                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 21783.545882                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21708.251765                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21708.251765                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21708.251765                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 21708.251765                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21708.251765                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 21708.251765                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           26.156826                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              37738                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse           26.169210                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              37730                       # Total number of references to valid blocks.
 system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1301.310345                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs          1301.034483                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.156826                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051088                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.051088                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.169210                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051112                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.051112                       # Average percentage of cache occupancy
 system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           296038                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          296038                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        42011                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          42011                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        31379                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         31379                       # number of WriteReq hits
+system.cpu2.dcache.tags.tag_accesses           295974                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          295974                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data        42003                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          42003                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        31371                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         31371                       # number of WriteReq hits
 system.cpu2.dcache.SwapReq_hits::cpu2.data           14                       # number of SwapReq hits
 system.cpu2.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        73390                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           73390                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        73390                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          73390                       # number of overall hits
+system.cpu2.dcache.demand_hits::cpu2.data        73374                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           73374                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        73374                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          73374                       # number of overall hits
 system.cpu2.dcache.ReadReq_misses::cpu2.data          342                       # number of ReadReq misses
 system.cpu2.dcache.ReadReq_misses::total          342                       # number of ReadReq misses
 system.cpu2.dcache.WriteReq_misses::cpu2.data          140                       # number of WriteReq misses
@@ -2095,46 +2202,46 @@ system.cpu2.dcache.demand_misses::cpu2.data          482                       #
 system.cpu2.dcache.demand_misses::total           482                       # number of demand (read+write) misses
 system.cpu2.dcache.overall_misses::cpu2.data          482                       # number of overall misses
 system.cpu2.dcache.overall_misses::total          482                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5441573                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      5441573                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5435581                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      5435581                       # number of ReadReq miss cycles
 system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3139010                       # number of WriteReq miss cycles
 system.cpu2.dcache.WriteReq_miss_latency::total      3139010                       # number of WriteReq miss cycles
 system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       574505                       # number of SwapReq miss cycles
 system.cpu2.dcache.SwapReq_miss_latency::total       574505                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      8580583                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      8580583                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      8580583                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      8580583                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        42353                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        42353                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        31519                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        31519                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.demand_miss_latency::cpu2.data      8574591                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total      8574591                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data      8574591                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total      8574591                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        42345                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        42345                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        31511                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        31511                       # number of WriteReq accesses(hits+misses)
 system.cpu2.dcache.SwapReq_accesses::cpu2.data           73                       # number of SwapReq accesses(hits+misses)
 system.cpu2.dcache.SwapReq_accesses::total           73                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        73872                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        73872                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        73872                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        73872                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.008075                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.008075                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004442                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.004442                       # miss rate for WriteReq accesses
+system.cpu2.dcache.demand_accesses::cpu2.data        73856                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        73856                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        73856                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        73856                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.008077                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.008077                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004443                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.004443                       # miss rate for WriteReq accesses
 system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.808219                       # miss rate for SwapReq accesses
 system.cpu2.dcache.SwapReq_miss_rate::total     0.808219                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.006525                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.006525                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.006525                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.006525                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15911.032164                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 15911.032164                       # average ReadReq miss latency
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.006526                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.006526                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.006526                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.006526                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15893.511696                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 15893.511696                       # average ReadReq miss latency
 system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22421.500000                       # average WriteReq miss latency
 system.cpu2.dcache.WriteReq_avg_miss_latency::total 22421.500000                       # average WriteReq miss latency
 system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  9737.372881                       # average SwapReq miss latency
 system.cpu2.dcache.SwapReq_avg_miss_latency::total  9737.372881                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17802.039419                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 17802.039419                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17802.039419                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 17802.039419                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17789.607884                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 17789.607884                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17789.607884                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 17789.607884                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2161,123 +2268,123 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data          271
 system.cpu2.dcache.demand_mshr_misses::total          271                       # number of demand (read+write) MSHR misses
 system.cpu2.dcache.overall_mshr_misses::cpu2.data          271                       # number of overall MSHR misses
 system.cpu2.dcache.overall_mshr_misses::total          271                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1516779                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1516779                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1515278                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1515278                       # number of ReadReq MSHR miss cycles
 system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1527990                       # number of WriteReq MSHR miss cycles
 system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1527990                       # number of WriteReq MSHR miss cycles
 system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       456495                       # number of SwapReq MSHR miss cycles
 system.cpu2.dcache.SwapReq_mshr_miss_latency::total       456495                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3044769                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3044769                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3044769                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3044769                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003896                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003896                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003363                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003363                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3043268                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      3043268                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3043268                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      3043268                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003897                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003897                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003364                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003364                       # mshr miss rate for WriteReq accesses
 system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.808219                       # mshr miss rate for SwapReq accesses
 system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.808219                       # mshr miss rate for SwapReq accesses
 system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003669                       # mshr miss rate for demand accesses
 system.cpu2.dcache.demand_mshr_miss_rate::total     0.003669                       # mshr miss rate for demand accesses
 system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003669                       # mshr miss rate for overall accesses
 system.cpu2.dcache.overall_mshr_miss_rate::total     0.003669                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9192.600000                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9192.600000                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9183.503030                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9183.503030                       # average ReadReq mshr miss latency
 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        14415                       # average WriteReq mshr miss latency
 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        14415                       # average WriteReq mshr miss latency
 system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  7737.203390                       # average SwapReq mshr miss latency
 system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  7737.203390                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11235.309963                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11235.309963                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11235.309963                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11235.309963                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11229.771218                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11229.771218                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11229.771218                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11229.771218                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups                  53969                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted            51237                       # Number of conditional branches predicted
+system.cpu3.branchPred.lookups                  53964                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted            51232                       # Number of conditional branches predicted
 system.cpu3.branchPred.condIncorrect             1265                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups               47879                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                  47122                       # Number of BTB hits
+system.cpu3.branchPred.BTBLookups               47874                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                  47117                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            98.418931                       # BTB Hit Percentage
+system.cpu3.branchPred.BTBHitPct            98.418766                       # BTB Hit Percentage
 system.cpu3.branchPred.usedRAS                    645                       # Number of times the RAS was used to get a target.
 system.cpu3.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu3.numCycles                          177018                       # number of cpu cycles simulated
+system.cpu3.numCycles                          176930                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles             27849                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        302683                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      53969                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             47767                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       106238                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.icacheStallCycles             27837                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        302665                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      53964                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             47762                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                       106222                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu3.fetch.SquashCycles                   3643                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles                 30687                       # Number of cycles fetch has spent blocked
+system.cpu3.fetch.BlockedCycles                 30631                       # Number of cycles fetch has spent blocked
 system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles         7755                       # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.NoActiveThreadStallCycles         7749                       # Number of stall cycles due to no active thread to fetch from
 system.cpu3.fetch.PendingTrapStallCycles          799                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    19589                       # Number of cache lines fetched
+system.cpu3.fetch.CacheLines                    19577                       # Number of cache lines fetched
 system.cpu3.fetch.IcacheSquashes                  266                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            175633                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.723383                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.153093                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::samples            175543                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.724164                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.153360                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   69395     39.51%     39.51% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   53961     30.72%     70.24% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    6037      3.44%     73.67% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3206      1.83%     75.50% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     696      0.40%     75.89% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   37090     21.12%     97.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   69321     39.49%     39.49% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   53950     30.73%     70.22% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    6031      3.44%     73.66% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3206      1.83%     75.48% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                     696      0.40%     75.88% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   37091     21.13%     97.01% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::6                    1217      0.69%     97.70% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::7                     754      0.43%     98.13% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::8                    3277      1.87%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              175633                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.304879                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.709900                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   32991                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                27180                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                   100358                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 5049                       # Number of cycles decode is unblocking
+system.cpu3.fetch.rateDist::total              175543                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.305002                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       1.710648                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   32973                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                27130                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                   100348                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 5043                       # Number of cycles decode is unblocking
 system.cpu3.decode.SquashCycles                  2300                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                299127                       # Number of instructions handled by decode
+system.cpu3.decode.DecodedInsts                299109                       # Number of instructions handled by decode
 system.cpu3.rename.SquashCycles                  2300                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   33666                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  14636                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         11796                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    95593                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                 9887                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                297010                       # Number of instructions processed by rename
+system.cpu3.rename.IdleCycles                   33648                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  14616                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         11766                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    95589                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                 9875                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                296992                       # Number of instructions processed by rename
 system.cpu3.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
 system.cpu3.rename.LSQFullEvents                   23                       # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands             207704                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               570857                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          442944                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               195081                       # Number of HB maps that are committed
+system.cpu3.rename.RenamedOperands             207702                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               570845                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          442935                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               195079                       # Number of HB maps that are committed
 system.cpu3.rename.UndoneMaps                   12623                       # Number of HB maps that are undone due to squashing
 system.cpu3.rename.serializingInsts              1101                       # count of serializing insts renamed
 system.cpu3.rename.tempSerializingInsts          1224                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    12502                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               84726                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              40382                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            40460                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           35337                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    246420                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               6261                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   248749                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued               57                       # Number of squashed instructions issued
+system.cpu3.rename.skidInsts                    12490                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               84722                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              40383                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            40455                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           35338                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    246413                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               6255                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   248738                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued               58                       # Number of squashed instructions issued
 system.cpu3.iq.iqSquashedInstsExamined          10413                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined         9956                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedOperandsExamined         9948                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu3.iq.iqSquashedNonSpecRemoved           566                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       175633                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.416300                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.309117                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::samples       175543                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.416963                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.309147                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              66575     37.91%     37.91% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              22292     12.69%     50.60% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              40685     23.16%     73.76% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              41298     23.51%     97.28% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3252      1.85%     99.13% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              66501     37.88%     37.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              22275     12.69%     50.57% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              40683     23.18%     73.75% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              41300     23.53%     97.27% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3253      1.85%     99.13% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::5               1166      0.66%     99.79% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::6                259      0.15%     99.94% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::7                 47      0.03%     99.97% # Number of insts issued each cycle
@@ -2285,43 +2392,43 @@ system.cpu3.iq.issued_per_cycle::8                 59      0.03%    100.00% # Nu
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         175633                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         175543                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     17      6.46%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      6.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    36     13.69%     20.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  210     79.85%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     17      6.44%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      6.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    37     14.02%     20.45% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  210     79.55%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               119915     48.21%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               119912     48.21%     48.21% # Type of FU issued
 system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.21% # Type of FU issued
 system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.21% # Type of FU issued
 system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.21% # Type of FU issued
@@ -2350,23 +2457,23 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.21% # Ty
 system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.21% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.21% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               89111     35.82%     84.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              39723     15.97%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               89101     35.82%     84.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              39725     15.97%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                248749                       # Type of FU issued
-system.cpu3.iq.rate                          1.405219                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        263                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001057                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            673451                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           263132                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       246950                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                248738                       # Type of FU issued
+system.cpu3.iq.rate                          1.405855                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        264                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001061                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            673341                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           263119                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       246940                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                249012                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                249002                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           35153                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           35155                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.squashedLoads         2247                       # Number of loads squashed
 system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
@@ -2378,12 +2485,12 @@ system.cpu3.iew.lsq.thread0.rescheduledLoads            0
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
 system.cpu3.iew.iewSquashCycles                  2300                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                    645                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewBlockCycles                    643                       # Number of cycles IEW is blocking
 system.cpu3.iew.iewUnblockCycles                   39                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             294144                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispatchedInsts             294126                       # Number of instructions dispatched to IQ
 system.cpu3.iew.iewDispSquashedInsts              354                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                84726                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               40382                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispLoadInsts                84722                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               40383                       # Number of dispatched store instructions
 system.cpu3.iew.iewDispNonSpecInsts              1060                       # Number of dispatched non-speculative instructions
 system.cpu3.iew.iewIQFullEvents                    38                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
@@ -2391,93 +2498,128 @@ system.cpu3.iew.memOrderViolationEvents            38                       # Nu
 system.cpu3.iew.predictedTakenIncorrect           459                       # Number of branches that were predicted taken incorrectly
 system.cpu3.iew.predictedNotTakenIncorrect          919                       # Number of branches that were predicted not taken incorrectly
 system.cpu3.iew.branchMispredicts                1378                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               247595                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                83855                       # Number of load instructions executed
+system.cpu3.iew.iewExecutedInsts               247584                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                83851                       # Number of load instructions executed
 system.cpu3.iew.iewExecSquashedInsts             1154                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        41463                       # number of nop insts executed
-system.cpu3.iew.exec_refs                      123509                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   50804                       # Number of branches executed
-system.cpu3.iew.exec_stores                     39654                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.398700                       # Inst execution rate
-system.cpu3.iew.wb_sent                        247239                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       246950                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   140249                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   144916                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        41458                       # number of nop insts executed
+system.cpu3.iew.exec_refs                      123507                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   50799                       # Number of branches executed
+system.cpu3.iew.exec_stores                     39656                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.399333                       # Inst execution rate
+system.cpu3.iew.wb_sent                        247229                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       246940                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   140247                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   144914                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      1.395056                       # insts written-back per cycle
+system.cpu3.iew.wb_rate                      1.395693                       # insts written-back per cycle
 system.cpu3.iew.wb_fanout                    0.967795                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu3.commit.commitSquashedInsts          11951                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           5695                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.commitNonSpecStalls           5689                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu3.commit.branchMispredicts             1265                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       165578                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.704170                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     2.038930                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::samples       165494                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.704926                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     2.039126                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        64386     38.89%     38.89% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        48906     29.54%     68.42% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         6087      3.68%     72.10% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         6642      4.01%     76.11% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1574      0.95%     77.06% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        35662     21.54%     98.60% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        64312     38.86%     38.86% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        48901     29.55%     68.41% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         6087      3.68%     72.09% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         6636      4.01%     76.10% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1574      0.95%     77.05% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        35663     21.55%     98.60% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::6          504      0.30%     98.90% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::7          999      0.60%     99.51% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::8          818      0.49%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       165578                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              282173                       # Number of instructions committed
-system.cpu3.commit.committedOps                282173                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total       165494                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts              282155                       # Number of instructions committed
+system.cpu3.commit.committedOps                282155                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                        121476                       # Number of memory references committed
-system.cpu3.commit.loads                        82479                       # Number of loads committed
-system.cpu3.commit.membars                       4985                       # Number of memory barriers committed
-system.cpu3.commit.branches                     49947                       # Number of branches committed
+system.cpu3.commit.refs                        121473                       # Number of memory references committed
+system.cpu3.commit.loads                        82475                       # Number of loads committed
+system.cpu3.commit.membars                       4979                       # Number of memory barriers committed
+system.cpu3.commit.branches                     49942                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   193548                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   193540                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
+system.cpu3.commit.op_class_0::No_OpClass        40736     14.44%     14.44% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu          114967     40.75%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult              0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv               0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead          87454     31.00%     86.18% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite         38998     13.82%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::total           282155                       # Class of committed instruction
 system.cpu3.commit.bw_lim_events                  818                       # number cycles where commit BW limit reached
 system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads                      458297                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     590554                       # The number of ROB writes
+system.cpu3.rob.rob_reads                      458195                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     590518                       # The number of ROB writes
 system.cpu3.timesIdled                            210                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           1385                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       44892                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     236447                       # Number of Instructions Simulated
-system.cpu3.committedOps                       236447                       # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total               236447                       # Number of Instructions Simulated
-system.cpu3.cpi                              0.748658                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        0.748658                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              1.335723                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        1.335723                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  429146                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 199911                       # number of integer regfile writes
+system.cpu3.idleCycles                           1387                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                       44814                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                     236440                       # Number of Instructions Simulated
+system.cpu3.committedOps                       236440                       # Number of Ops (including micro ops) Simulated
+system.cpu3.committedInsts_total               236440                       # Number of Instructions Simulated
+system.cpu3.cpi                              0.748308                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.748308                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.336348                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.336348                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  429141                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 199912                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                 125103                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                 125101                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu3.icache.tags.replacements              319                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           80.480006                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs              19114                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.tagsinuse           80.524551                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs              19102                       # Total number of references to valid blocks.
 system.cpu3.icache.tags.sampled_refs              430                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs            44.451163                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs            44.423256                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    80.480006                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.157188                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.157188                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    80.524551                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.157275                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.157275                       # Average percentage of cache occupancy
 system.cpu3.icache.tags.occ_task_id_blocks::1024          111                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
 system.cpu3.icache.tags.occ_task_id_percent::1024     0.216797                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses            20019                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses           20019                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst        19114                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          19114                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        19114                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           19114                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        19114                       # number of overall hits
-system.cpu3.icache.overall_hits::total          19114                       # number of overall hits
+system.cpu3.icache.tags.tag_accesses            20007                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses           20007                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst        19102                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          19102                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        19102                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           19102                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        19102                       # number of overall hits
+system.cpu3.icache.overall_hits::total          19102                       # number of overall hits
 system.cpu3.icache.ReadReq_misses::cpu3.inst          475                       # number of ReadReq misses
 system.cpu3.icache.ReadReq_misses::total          475                       # number of ReadReq misses
 system.cpu3.icache.demand_misses::cpu3.inst          475                       # number of demand (read+write) misses
@@ -2490,18 +2632,18 @@ system.cpu3.icache.demand_miss_latency::cpu3.inst      6525745
 system.cpu3.icache.demand_miss_latency::total      6525745                       # number of demand (read+write) miss cycles
 system.cpu3.icache.overall_miss_latency::cpu3.inst      6525745                       # number of overall miss cycles
 system.cpu3.icache.overall_miss_latency::total      6525745                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        19589                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        19589                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        19589                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        19589                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        19589                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        19589                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.024248                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.024248                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.024248                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.024248                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.024248                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.024248                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        19577                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        19577                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        19577                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        19577                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        19577                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        19577                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.024263                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.024263                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.024263                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.024263                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.024263                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.024263                       # miss rate for overall accesses
 system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526                       # average ReadReq miss latency
 system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526                       # average ReadReq miss latency
 system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526                       # average overall miss latency
@@ -2534,12 +2676,12 @@ system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5298255
 system.cpu3.icache.demand_mshr_miss_latency::total      5298255                       # number of demand (read+write) MSHR miss cycles
 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5298255                       # number of overall MSHR miss cycles
 system.cpu3.icache.overall_mshr_miss_latency::total      5298255                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.021951                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.021951                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.021951                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.021951                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.021951                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.021951                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.021965                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.021965                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.021965                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.021965                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.021965                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.021965                       # mshr miss rate for overall accesses
 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256                       # average ReadReq mshr miss latency
 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256                       # average ReadReq mshr miss latency
 system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256                       # average overall mshr miss latency
@@ -2548,29 +2690,29 @@ system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256
 system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           24.751493                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              44991                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse           24.706550                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              44992                       # Total number of references to valid blocks.
 system.cpu3.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1606.821429                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs          1606.857143                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.751493                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.048343                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.048343                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.706550                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.048255                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.048255                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           350966                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          350966                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        48333                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          48333                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        38794                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         38794                       # number of WriteReq hits
+system.cpu3.dcache.tags.tag_accesses           350946                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          350946                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data        48327                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          48327                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        38795                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         38795                       # number of WriteReq hits
 system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
 system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        87127                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           87127                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        87127                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          87127                       # number of overall hits
+system.cpu3.dcache.demand_hits::cpu3.data        87122                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           87122                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        87122                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          87122                       # number of overall hits
 system.cpu3.dcache.ReadReq_misses::cpu3.data          351                       # number of ReadReq misses
 system.cpu3.dcache.ReadReq_misses::total          351                       # number of ReadReq misses
 system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
@@ -2581,28 +2723,28 @@ system.cpu3.dcache.demand_misses::cpu3.data          490                       #
 system.cpu3.dcache.demand_misses::total           490                       # number of demand (read+write) misses
 system.cpu3.dcache.overall_misses::cpu3.data          490                       # number of overall misses
 system.cpu3.dcache.overall_misses::total          490                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4639136                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      4639136                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3479012                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      3479012                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       512008                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       512008                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      8118148                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      8118148                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      8118148                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      8118148                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        48684                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        48684                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        38933                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        38933                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4621144                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      4621144                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3311512                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      3311512                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       513008                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       513008                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data      7932656                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total      7932656                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data      7932656                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total      7932656                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        48678                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        48678                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        38934                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        38934                       # number of WriteReq accesses(hits+misses)
 system.cpu3.dcache.SwapReq_accesses::cpu3.data           64                       # number of SwapReq accesses(hits+misses)
 system.cpu3.dcache.SwapReq_accesses::total           64                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        87617                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        87617                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        87617                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        87617                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007210                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.007210                       # miss rate for ReadReq accesses
+system.cpu3.dcache.demand_accesses::cpu3.data        87612                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        87612                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        87612                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        87612                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007211                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.007211                       # miss rate for ReadReq accesses
 system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003570                       # miss rate for WriteReq accesses
 system.cpu3.dcache.WriteReq_miss_rate::total     0.003570                       # miss rate for WriteReq accesses
 system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.812500                       # miss rate for SwapReq accesses
@@ -2611,16 +2753,16 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005593
 system.cpu3.dcache.demand_miss_rate::total     0.005593                       # miss rate for demand accesses
 system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005593                       # miss rate for overall accesses
 system.cpu3.dcache.overall_miss_rate::total     0.005593                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13216.911681                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 13216.911681                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25028.863309                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 25028.863309                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9846.307692                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  9846.307692                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16567.648980                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 16567.648980                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16567.648980                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 16567.648980                       # average overall miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13165.652422                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 13165.652422                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23823.827338                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 23823.827338                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9865.538462                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total  9865.538462                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16189.093878                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 16189.093878                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16189.093878                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 16189.093878                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2647,36 +2789,36 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data          260
 system.cpu3.dcache.demand_mshr_misses::total          260                       # number of demand (read+write) MSHR misses
 system.cpu3.dcache.overall_mshr_misses::cpu3.data          260                       # number of overall MSHR misses
 system.cpu3.dcache.overall_mshr_misses::total          260                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1051018                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1051018                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1439238                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1439238                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       407992                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       407992                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2490256                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      2490256                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2490256                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      2490256                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003163                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003163                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1052517                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1052517                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1403488                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1403488                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       408992                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       408992                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2456005                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      2456005                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2456005                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      2456005                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003164                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003164                       # mshr miss rate for ReadReq accesses
 system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002723                       # mshr miss rate for WriteReq accesses
 system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002723                       # mshr miss rate for WriteReq accesses
 system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.812500                       # mshr miss rate for SwapReq accesses
 system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.812500                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002967                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.002967                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002967                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.002967                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6824.792208                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6824.792208                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13577.716981                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13577.716981                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data         7846                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total         7846                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9577.907692                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9577.907692                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9577.907692                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9577.907692                       # average overall mshr miss latency
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002968                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.002968                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002968                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.002968                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6834.525974                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6834.525974                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13240.452830                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13240.452830                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  7865.230769                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  7865.230769                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9446.173077                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9446.173077                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9446.173077                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9446.173077                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 728e876c6..3bc9d35ce 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                    87707000                       # Number of ticks simulated
 final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 202617                       # Simulator instruction rate (inst/s)
-host_op_rate                                   202616                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               26236566                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 297428                       # Number of bytes of host memory used
-host_seconds                                     3.34                       # Real time elapsed on the host
+host_inst_rate                                1618143                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1618081                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              209518099                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 283888                       # Number of bytes of host memory used
+host_seconds                                     0.42                       # Real time elapsed on the host
 sim_insts                                      677327                       # Number of instructions simulated
 sim_ops                                        677327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -274,6 +274,41 @@ system.cpu0.num_busy_cycles                    175415                       # Nu
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.Branches                            29689                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                26416     15.06%     15.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu                    66491     37.91%     52.97% # Class of executed instruction
+system.cpu0.op_class::IntMult                       0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     52.97% # Class of executed instruction
+system.cpu0.op_class::MemRead                   54675     31.17%     84.15% # Class of executed instruction
+system.cpu0.op_class::MemWrite                  27806     15.85%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                    175388                       # Class of executed instruction
 system.cpu0.icache.tags.replacements              215                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          222.772698                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs             174921                       # Total number of references to valid blocks.
@@ -411,6 +446,41 @@ system.cpu1.num_busy_cycles              165421.275663                       # N
 system.cpu1.not_idle_fraction                0.954565                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.045435                       # Percentage of idle cycles
 system.cpu1.Branches                            34390                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                25177     15.04%     15.04% # Class of executed instruction
+system.cpu1.op_class::IntAlu                    73170     43.70%     58.74% # Class of executed instruction
+system.cpu1.op_class::IntMult                       0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     58.74% # Class of executed instruction
+system.cpu1.op_class::MemRead                   56341     33.65%     92.39% # Class of executed instruction
+system.cpu1.op_class::MemWrite                  12742      7.61%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                    167430                       # Class of executed instruction
 system.cpu1.icache.tags.replacements              278                       # number of replacements
 system.cpu1.icache.tags.tagsinuse           76.751702                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs             167072                       # Total number of references to valid blocks.
@@ -545,6 +615,41 @@ system.cpu2.num_busy_cycles              165358.048783                       # N
 system.cpu2.not_idle_fraction                0.954200                       # Percentage of non-idle cycles
 system.cpu2.idle_fraction                    0.045800                       # Percentage of idle cycles
 system.cpu2.Branches                            32652                       # Number of branches fetched
+system.cpu2.op_class::No_OpClass                23444     14.01%     14.01% # Class of executed instruction
+system.cpu2.op_class::IntAlu                    74873     44.74%     58.74% # Class of executed instruction
+system.cpu2.op_class::IntMult                       0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::IntDiv                        0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::FloatAdd                      0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::FloatCmp                      0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::FloatCvt                      0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::FloatMult                     0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::FloatDiv                      0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::FloatSqrt                     0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdAdd                       0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdAddAcc                    0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdAlu                       0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdCmp                       0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdCvt                       0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdMisc                      0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdMult                      0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdMultAcc                   0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdShift                     0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdShiftAcc                  0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdSqrt                      0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAdd                  0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAlu                  0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCmp                  0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCvt                  0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdFloatDiv                  0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMisc                 0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMult                 0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     58.74% # Class of executed instruction
+system.cpu2.op_class::MemRead                   52874     31.59%     90.34% # Class of executed instruction
+system.cpu2.op_class::MemWrite                  16175      9.66%    100.00% # Class of executed instruction
+system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu2.op_class::total                    167366                       # Class of executed instruction
 system.cpu2.icache.tags.replacements              278                       # number of replacements
 system.cpu2.icache.tags.tagsinuse           74.781015                       # Cycle average of tags in use
 system.cpu2.icache.tags.total_refs             167008                       # Total number of references to valid blocks.
@@ -679,6 +784,41 @@ system.cpu3.num_busy_cycles              165292.880154                       # N
 system.cpu3.not_idle_fraction                0.953829                       # Percentage of non-idle cycles
 system.cpu3.idle_fraction                    0.046171                       # Percentage of idle cycles
 system.cpu3.Branches                            33511                       # Number of branches fetched
+system.cpu3.op_class::No_OpClass                24299     14.52%     14.52% # Class of executed instruction
+system.cpu3.op_class::IntAlu                    73982     44.22%     58.75% # Class of executed instruction
+system.cpu3.op_class::IntMult                       0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::IntDiv                        0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::FloatAdd                      0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::FloatCmp                      0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::FloatCvt                      0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::FloatMult                     0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::FloatDiv                      0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::FloatSqrt                     0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdAdd                       0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdAddAcc                    0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdAlu                       0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdCmp                       0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdCvt                       0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdMisc                      0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdMult                      0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdMultAcc                   0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdShift                     0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdShiftAcc                  0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdSqrt                      0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAdd                  0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAlu                  0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCmp                  0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCvt                  0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdFloatDiv                  0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMisc                 0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMult                 0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     58.75% # Class of executed instruction
+system.cpu3.op_class::MemRead                   54586     32.63%     91.37% # Class of executed instruction
+system.cpu3.op_class::MemWrite                  14434      8.63%    100.00% # Class of executed instruction
+system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu3.op_class::total                    167301                       # Class of executed instruction
 system.cpu3.icache.tags.replacements              279                       # number of replacements
 system.cpu3.icache.tags.tagsinuse           72.874497                       # Cycle average of tags in use
 system.cpu3.icache.tags.total_refs             166942                       # Total number of references to valid blocks.
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 036213a3d..704fea740 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000263                       # Nu
 sim_ticks                                   262794500                       # Number of ticks simulated
 final_tick                                  262794500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 160692                       # Simulator instruction rate (inst/s)
-host_op_rate                                   160691                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63638702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 297424                       # Number of bytes of host memory used
-host_seconds                                     4.13                       # Real time elapsed on the host
+host_inst_rate                                 985745                       # Simulator instruction rate (inst/s)
+host_op_rate                                   985721                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              390370221                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 283880                       # Number of bytes of host memory used
+host_seconds                                     0.67                       # Real time elapsed on the host
 sim_insts                                      663567                       # Number of instructions simulated
 sim_ops                                        663567                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -561,6 +561,41 @@ system.cpu0.num_busy_cycles                    525589                       # Nu
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.Branches                            26897                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                23624     14.89%     14.89% # Class of executed instruction
+system.cpu0.op_class::IntAlu                    60907     38.39%     53.29% # Class of executed instruction
+system.cpu0.op_class::IntMult                       0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::MemRead                   49091     30.95%     84.23% # Class of executed instruction
+system.cpu0.op_class::MemWrite                  25014     15.77%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                    158636                       # Class of executed instruction
 system.cpu0.icache.tags.replacements              215                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          212.401822                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs             158170                       # Total number of references to valid blocks.
@@ -794,6 +829,41 @@ system.cpu1.num_busy_cycles              456241.130205                       # N
 system.cpu1.not_idle_fraction                0.868058                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.131942                       # Percentage of idle cycles
 system.cpu1.Branches                            31528                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                22316     13.65%     13.65% # Class of executed instruction
+system.cpu1.op_class::IntAlu                    75095     45.93%     59.58% # Class of executed instruction
+system.cpu1.op_class::IntMult                       0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.58% # Class of executed instruction
+system.cpu1.op_class::MemRead                   49612     30.34%     89.92% # Class of executed instruction
+system.cpu1.op_class::MemWrite                  16480     10.08%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                    163503                       # Class of executed instruction
 system.cpu1.icache.tags.replacements              280                       # number of replacements
 system.cpu1.icache.tags.tagsinuse           70.017504                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs             163138                       # Total number of references to valid blocks.
@@ -1026,6 +1096,41 @@ system.cpu2.num_busy_cycles              455984.130695                       # N
 system.cpu2.not_idle_fraction                0.867570                       # Percentage of non-idle cycles
 system.cpu2.idle_fraction                    0.132430                       # Percentage of idle cycles
 system.cpu2.Branches                            31596                       # Number of branches fetched
+system.cpu2.op_class::No_OpClass                22386     13.58%     13.58% # Class of executed instruction
+system.cpu2.op_class::IntAlu                    75723     45.92%     59.50% # Class of executed instruction
+system.cpu2.op_class::IntMult                       0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::IntDiv                        0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::FloatAdd                      0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::FloatCmp                      0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::FloatCvt                      0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::FloatMult                     0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::FloatDiv                      0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::FloatSqrt                     0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdAdd                       0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdAlu                       0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdCmp                       0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdCvt                       0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdMisc                      0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdMult                      0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdShift                     0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdSqrt                      0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.50% # Class of executed instruction
+system.cpu2.op_class::MemRead                   49752     30.17%     89.67% # Class of executed instruction
+system.cpu2.op_class::MemWrite                  17037     10.33%    100.00% # Class of executed instruction
+system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu2.op_class::total                    164898                       # Class of executed instruction
 system.cpu2.icache.tags.replacements              280                       # number of replacements
 system.cpu2.icache.tags.tagsinuse           67.624960                       # Cycle average of tags in use
 system.cpu2.icache.tags.total_refs             164533                       # Total number of references to valid blocks.
@@ -1258,6 +1363,41 @@ system.cpu3.num_busy_cycles              455718.131202                       # N
 system.cpu3.not_idle_fraction                0.867063                       # Percentage of non-idle cycles
 system.cpu3.idle_fraction                    0.132937                       # Percentage of idle cycles
 system.cpu3.Branches                            39890                       # Number of branches fetched
+system.cpu3.op_class::No_OpClass                30652     17.35%     17.35% # Class of executed instruction
+system.cpu3.op_class::IntAlu                    73353     41.52%     58.86% # Class of executed instruction
+system.cpu3.op_class::IntMult                       0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::IntDiv                        0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::FloatAdd                      0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::FloatCmp                      0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::FloatCvt                      0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::FloatMult                     0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::FloatDiv                      0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::FloatSqrt                     0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdAdd                       0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdAddAcc                    0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdAlu                       0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdCmp                       0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdCvt                       0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdMisc                      0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdMult                      0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdMultAcc                   0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdShift                     0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdShiftAcc                  0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdSqrt                      0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAdd                  0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAlu                  0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCmp                  0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCvt                  0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdFloatDiv                  0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMisc                 0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMult                 0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     58.86% # Class of executed instruction
+system.cpu3.op_class::MemRead                   66272     37.51%     96.37% # Class of executed instruction
+system.cpu3.op_class::MemWrite                   6411      3.63%    100.00% # Class of executed instruction
+system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu3.op_class::total                    176688                       # Class of executed instruction
 system.cpu3.icache.tags.replacements              281                       # number of replacements
 system.cpu3.icache.tags.tagsinuse           65.598437                       # Cycle average of tags in use
 system.cpu3.icache.tags.total_refs             176322                       # Total number of references to valid blocks.
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
index c44d33a13..bc520582f 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
@@ -4,93 +4,99 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            24940417343                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228644                       # Number of bytes of host memory used
-host_seconds                                     4.01                       # Real time elapsed on the host
+host_tick_rate                            14337554787                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228672                       # Number of bytes of host memory used
+host_seconds                                     6.97                       # Real time elapsed on the host
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu              213331136                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            213331136                       # Number of bytes read from this memory
-system.physmem.num_reads::cpu                 3333299                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               3333299                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu                2133311360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2133311360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu               2133311360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2133311360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       3333300                       # Number of read requests accepted
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                     3333300                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                213331200                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 213331200                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu              106798016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            106798016                       # Number of bytes read from this memory
+system.physmem.bytes_written::cpu           106535680                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         106535680                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu                 1668719                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1668719                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu                1664620                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1664620                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu                1067980160                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1067980160                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu               1065356800                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1065356800                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu               2133336960                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2133336960                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1668720                       # Number of read requests accepted
+system.physmem.writeReqs                      1664620                       # Number of write requests accepted
+system.physmem.readBursts                     1668720                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1664620                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                106797184                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       896                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 106533952                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 106798080                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              106535680                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       14                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       8                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              217600                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              217600                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              217600                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              217600                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              210100                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             204800                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             204800                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              104195                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              104188                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              104541                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              104589                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              103994                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              104203                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              104803                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              104557                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              104630                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              104040                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             104372                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             104177                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             103805                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             104138                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             103922                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             104552                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              103587                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              104082                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              103950                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              104334                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              104264                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              104509                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              103927                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104060                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              104076                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              104072                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             104151                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             104328                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             103712                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             103871                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             103773                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             103897                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     99999960000                       # Total gap between requests
+system.physmem.totGap                     99999960227                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 3333300                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1668720                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   2967921                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    224361                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     12823                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     15990                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     17049                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     13879                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     17179                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     12823                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     15990                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     17049                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    12820                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     5416                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1664620                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    766507                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    779035                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     72986                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     24510                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     10942                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7167                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4128                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      2045                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       890                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       388                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       97                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
@@ -110,48 +116,48 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    21583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    26179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    48990                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                   101142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   110031                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   109380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   103714                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   100305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   100049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   122199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   111635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   105240                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   100495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    98624                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    98614                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    98524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    98476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    98391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2040                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
@@ -174,49 +180,89 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       195487                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean            1024                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1024.000000                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       195487    100.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         195487                       # Bytes accessed per row activation
-system.physmem.totQLat                    27932046800                       # Total ticks spent queuing
-system.physmem.totMemAccLat               91374259300                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  16666500000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 46775712500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8379.70                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14032.85                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::samples      3296563                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       64.713043                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      64.189923                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      23.988602                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3288788     99.76%     99.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         5620      0.17%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           32      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           32      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           32      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           32      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           32      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           32      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1963      0.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        3296563                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         97746                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        17.071819                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       15.727304                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      106.831001                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          97745    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32768-34815            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           97746                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         97746                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.029781                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.939241                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.836351                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              73134     74.82%     74.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                545      0.56%     75.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                655      0.67%     76.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1612      1.65%     77.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20              16208     16.58%     94.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21               5168      5.29%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                147      0.15%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 85      0.09%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 66      0.07%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 49      0.05%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 29      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 26      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 16      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  4      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           97746                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    58049969454                       # Total ticks spent queuing
+system.physmem.totMemAccLat               89338206954                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8343530000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       34787.42                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27412.55                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        2133.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     2133.31                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53537.42                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1067.97                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                        1065.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1067.98                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                     1065.36                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                          16.67                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      16.67                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.33                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    3112095                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.36                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        30000.29                       # Average gap between requests
-system.physmem.pageHitRate                      93.36                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.11                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   2133311360                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             3333300                       # Transaction distribution
-system.membus.trans_dist::ReadResp            3333299                       # Transaction distribution
-system.membus.pkt_count_system.monitor-master::system.physmem.port      6666599                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6666599                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.monitor-master::system.physmem.port    213331136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           213331136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              213331136                       # Total data (bytes)
-system.membus.reqLayer0.occupancy          6333270000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               6.3                       # Layer utilization (%)
-system.membus.respLayer0.occupancy        17200626050                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             17.2                       # Layer utilization (%)
-system.monitor.readBurstLengthHist::samples      3333300                       # Histogram of burst lengths of transmitted packets
+system.physmem.busUtilRead                       8.34                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      8.32                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.68                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.19                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      32203                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                      4525                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                    1.93                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                   0.27                       # Row buffer hit rate for writes
+system.physmem.avgGap                        29999.93                       # Average gap between requests
+system.physmem.pageHitRate                       1.10                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE          5508849                       # Time in different power states
+system.physmem.memoryStateTime::REF        3339180000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       96654451752                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   2133336960                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1668720                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1668719                       # Transaction distribution
+system.membus.trans_dist::WriteReq            1664620                       # Transaction distribution
+system.membus.trans_dist::WriteResp           1664620                       # Transaction distribution
+system.membus.pkt_count_system.monitor-master::system.physmem.port      6666679                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6666679                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.monitor-master::system.physmem.port    213333696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           213333696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              213333696                       # Total data (bytes)
+system.membus.reqLayer0.occupancy         11669983278                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              11.7                       # Layer utilization (%)
+system.membus.respLayer0.occupancy        11409038076                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             11.4                       # Layer utilization (%)
+system.monitor.readBurstLengthHist::samples      1668720                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::mean           64                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::gmean    64.000000                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::stdev            0                       # Histogram of burst lengths of transmitted packets
@@ -236,40 +282,40 @@ system.monitor.readBurstLengthHist::48-51            0      0.00%      0.00% # H
 system.monitor.readBurstLengthHist::52-55            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::56-59            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::60-63            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::64-67      3333300    100.00%    100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::64-67      1668720    100.00%    100.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::68-71            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::72-75            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::76-79            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::total      3333300                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::samples            0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::mean          nan                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::gmean          nan                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::stdev          nan                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::0              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::1              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::2              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::3              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::4              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::5              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::6              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::7              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::8              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::9              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::10             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::11             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::12             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::13             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::14             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::15             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::16             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::17             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::18             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::19             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::total            0                       # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::total      1668720                       # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::samples      1664620                       # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::mean           64                       # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::gmean    64.000000                       # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::stdev            0                       # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::0-3            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::4-7            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::8-11            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::12-15            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::16-19            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::20-23            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::24-27            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::28-31            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::32-35            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::36-39            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::40-43            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::44-47            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::48-51            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::52-55            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::56-59            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::60-63            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::64-67      1664620    100.00%    100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::68-71            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::72-75            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::76-79            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::total      1664620                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBandwidthHist::samples          100                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::mean     2133311360                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean  2133311357.360062                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev  106664.726883                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::mean     1067980160                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::gmean  1064651766.271052                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::stdev  107759819.009425                       # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::0-1.34218e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
@@ -277,172 +323,172 @@ system.monitor.readBandwidthHist::4.02653e+08-5.36871e+08            0      0.00
 system.monitor.readBandwidthHist::5.36871e+08-6.71089e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::6.71089e+08-8.05306e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::8.05306e+08-9.39524e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::9.39524e+08-1.07374e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.07374e+09-1.20796e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.20796e+09-1.34218e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.34218e+09-1.4764e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.4764e+09-1.61061e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.61061e+09-1.74483e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.74483e+09-1.87905e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.87905e+09-2.01327e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.01327e+09-2.14748e+09          100    100.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::9.39524e+08-1.07374e+09           99     99.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.07374e+09-1.20796e+09            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.20796e+09-1.34218e+09            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.34218e+09-1.4764e+09            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.4764e+09-1.61061e+09            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.61061e+09-1.74483e+09            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.74483e+09-1.87905e+09            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.87905e+09-2.01327e+09            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::2.01327e+09-2.14748e+09            1      1.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.14748e+09-2.2817e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.2817e+09-2.41592e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::total           100                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.averageReadBandwidth        2133311360      0.00%      0.00% # Average read bandwidth (bytes/s)
-system.monitor.totalReadBytes               213331136                       # Number of bytes read
+system.monitor.averageReadBandwidth        1067980160      0.00%      0.00% # Average read bandwidth (bytes/s)
+system.monitor.totalReadBytes               106798016                       # Number of bytes read
 system.monitor.writeBandwidthHist::samples          100                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::mean             0                       # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::mean    1065356800                       # Histogram of write bandwidth (bytes/s)
 system.monitor.writeBandwidthHist::gmean            0                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::stdev            0                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::0              100    100.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::3                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::4                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::5                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::6                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::7                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::8                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::9                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::10               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::11               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::12               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::13               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::14               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::15               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::16               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::17               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::18               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::19               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::stdev 107770982.104450                       # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::0-6.71089e+07            1      1.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::6.71089e+07-1.34218e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::1.34218e+08-2.01327e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::2.01327e+08-2.68435e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::2.68435e+08-3.35544e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::3.35544e+08-4.02653e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::4.02653e+08-4.69762e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::4.69762e+08-5.36871e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::5.36871e+08-6.0398e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::6.0398e+08-6.71089e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::6.71089e+08-7.38198e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::7.38198e+08-8.05306e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::8.05306e+08-8.72415e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::8.72415e+08-9.39524e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::9.39524e+08-1.00663e+09            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::1.00663e+09-1.07374e+09           29     29.00%     30.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::1.07374e+09-1.14085e+09           70     70.00%    100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::1.14085e+09-1.20796e+09            0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::1.20796e+09-1.27507e+09            0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::1.27507e+09-1.34218e+09            0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
 system.monitor.writeBandwidthHist::total          100                       # Histogram of write bandwidth (bytes/s)
-system.monitor.averageWriteBandwidth                0                       # Average write bandwidth (bytes/s)
-system.monitor.totalWrittenBytes                    0                       # Number of bytes written
-system.monitor.readLatencyHist::samples       3333299                       # Read request-response latency
-system.monitor.readLatencyHist::mean     47438.751234                       # Read request-response latency
-system.monitor.readLatencyHist::gmean    42490.722724                       # Read request-response latency
-system.monitor.readLatencyHist::stdev    40033.411924                       # Read request-response latency
-system.monitor.readLatencyHist::0-32767             0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::32768-65535      3182634     95.48%     95.48% # Read request-response latency
-system.monitor.readLatencyHist::65536-98303        17049      0.51%     95.99% # Read request-response latency
-system.monitor.readLatencyHist::98304-131071        18238      0.55%     96.54% # Read request-response latency
-system.monitor.readLatencyHist::131072-163839        15993      0.48%     97.02% # Read request-response latency
-system.monitor.readLatencyHist::163840-196607        17049      0.51%     97.53% # Read request-response latency
-system.monitor.readLatencyHist::196608-229375        18238      0.55%     98.08% # Read request-response latency
-system.monitor.readLatencyHist::229376-262143        15990      0.48%     98.56% # Read request-response latency
-system.monitor.readLatencyHist::262144-294911        17052      0.51%     99.07% # Read request-response latency
-system.monitor.readLatencyHist::294912-327679        13881      0.42%     99.48% # Read request-response latency
-system.monitor.readLatencyHist::327680-360447        17175      0.52%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::360448-393215            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::393216-425983            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::425984-458751            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::458752-491519            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::491520-524287            0      0.00%    100.00% # Read request-response latency
+system.monitor.averageWriteBandwidth       1065356800      0.00%      0.00% # Average write bandwidth (bytes/s)
+system.monitor.totalWrittenBytes            106535680                       # Number of bytes written
+system.monitor.readLatencyHist::samples       1668719                       # Read request-response latency
+system.monitor.readLatencyHist::mean     73576.537902                       # Read request-response latency
+system.monitor.readLatencyHist::gmean    68507.812375                       # Read request-response latency
+system.monitor.readLatencyHist::stdev    39270.153648                       # Read request-response latency
+system.monitor.readLatencyHist::0-32767            14      0.00%      0.00% # Read request-response latency
+system.monitor.readLatencyHist::32768-65535       454232     27.22%     27.22% # Read request-response latency
+system.monitor.readLatencyHist::65536-98303      1043171     62.51%     89.73% # Read request-response latency
+system.monitor.readLatencyHist::98304-131071        73085      4.38%     94.11% # Read request-response latency
+system.monitor.readLatencyHist::131072-163839        46931      2.81%     96.93% # Read request-response latency
+system.monitor.readLatencyHist::163840-196607        12458      0.75%     97.67% # Read request-response latency
+system.monitor.readLatencyHist::196608-229375         7854      0.47%     98.14% # Read request-response latency
+system.monitor.readLatencyHist::229376-262143         7990      0.48%     98.62% # Read request-response latency
+system.monitor.readLatencyHist::262144-294911         8124      0.49%     99.11% # Read request-response latency
+system.monitor.readLatencyHist::294912-327679         7849      0.47%     99.58% # Read request-response latency
+system.monitor.readLatencyHist::327680-360447         4246      0.25%     99.83% # Read request-response latency
+system.monitor.readLatencyHist::360448-393215         1108      0.07%     99.90% # Read request-response latency
+system.monitor.readLatencyHist::393216-425983          866      0.05%     99.95% # Read request-response latency
+system.monitor.readLatencyHist::425984-458751          601      0.04%     99.99% # Read request-response latency
+system.monitor.readLatencyHist::458752-491519          183      0.01%    100.00% # Read request-response latency
+system.monitor.readLatencyHist::491520-524287            7      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::524288-557055            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::557056-589823            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::589824-622591            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::622592-655359            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::total         3333299                       # Read request-response latency
-system.monitor.writeLatencyHist::samples            0                       # Write request-response latency
-system.monitor.writeLatencyHist::mean             nan                       # Write request-response latency
-system.monitor.writeLatencyHist::gmean            nan                       # Write request-response latency
-system.monitor.writeLatencyHist::stdev            nan                       # Write request-response latency
-system.monitor.writeLatencyHist::0                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::1                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::2                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::3                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::4                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::5                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::6                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::7                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::8                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::9                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::10                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::11                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::12                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::13                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::14                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::15                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::16                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::17                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::18                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::19                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::total              0                       # Write request-response latency
-system.monitor.ittReadRead::samples           3333299                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::mean         30000.297003                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::stdev           54.497186                       # Read-to-read inter transaction time
+system.monitor.readLatencyHist::total         1668719                       # Read request-response latency
+system.monitor.writeLatencyHist::samples      1664620                       # Write request-response latency
+system.monitor.writeLatencyHist::mean    10570.968616                       # Write request-response latency
+system.monitor.writeLatencyHist::gmean   10511.906115                       # Write request-response latency
+system.monitor.writeLatencyHist::stdev    1198.829619                       # Write request-response latency
+system.monitor.writeLatencyHist::0-1023             0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::1024-2047            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::2048-3071            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::3072-4095            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::4096-5119            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::5120-6143            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::6144-7167            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::7168-8191            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::8192-9215            0      0.00%      0.00% # Write request-response latency
+system.monitor.writeLatencyHist::9216-10239      1266039     76.06%     76.06% # Write request-response latency
+system.monitor.writeLatencyHist::10240-11263        92649      5.57%     81.62% # Write request-response latency
+system.monitor.writeLatencyHist::11264-12287       113174      6.80%     88.42% # Write request-response latency
+system.monitor.writeLatencyHist::12288-13311        92637      5.57%     93.99% # Write request-response latency
+system.monitor.writeLatencyHist::13312-14335        63204      3.80%     97.78% # Write request-response latency
+system.monitor.writeLatencyHist::14336-15359        32757      1.97%     99.75% # Write request-response latency
+system.monitor.writeLatencyHist::15360-16383         4158      0.25%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::16384-17407            2      0.00%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::17408-18431            0      0.00%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::18432-19455            0      0.00%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::19456-20479            0      0.00%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::total        1664620                       # Write request-response latency
+system.monitor.ittReadRead::samples           1668719                       # Read-to-read inter transaction time
+system.monitor.ittReadRead::mean         59926.183034                       # Read-to-read inter transaction time
+system.monitor.ittReadRead::stdev        42757.593151                       # Read-to-read inter transaction time
 system.monitor.ittReadRead::underflows              0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::1-5000                  0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::5001-10000              0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::10001-15000             0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::15001-20000             0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::20001-25000             0      0.00%      0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::25001-30000       3333200    100.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::30001-35000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::35001-40000            99      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::40001-45000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::45001-50000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::50001-55000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::55001-60000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::60001-65000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::65001-70000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::70001-75000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::75001-80000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::80001-85000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::85001-90000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::90001-95000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::95001-100000            0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::overflows               0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::min_value           30000                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::max_value           40000                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::total             3333299                       # Read-to-read inter transaction time
-system.monitor.ittWriteWrite::samples               0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::mean                nan                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::stdev               nan                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::underflows            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::1-5000                0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::5001-10000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::10001-15000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::15001-20000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::20001-25000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::25001-30000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::30001-35000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::35001-40000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::40001-45000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::45001-50000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::50001-55000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::55001-60000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::60001-65000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::65001-70000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::70001-75000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::75001-80000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::80001-85000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::85001-90000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::90001-95000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::95001-100000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::overflows             0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::min_value             0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::max_value             0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::total                 0                       # Write-to-write inter transaction time
-system.monitor.ittReqReq::samples             3333299                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::mean           30000.297003                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::stdev             54.497186                       # Request-to-request inter transaction time
+system.monitor.ittReadRead::25001-30000        438300     26.27%     26.27% # Read-to-read inter transaction time
+system.monitor.ittReadRead::30001-35000        404751     24.26%     50.52% # Read-to-read inter transaction time
+system.monitor.ittReadRead::35001-40000             3      0.00%     50.52% # Read-to-read inter transaction time
+system.monitor.ittReadRead::40001-45000             3      0.00%     50.52% # Read-to-read inter transaction time
+system.monitor.ittReadRead::45001-50000             0      0.00%     50.52% # Read-to-read inter transaction time
+system.monitor.ittReadRead::50001-55000             3      0.00%     50.52% # Read-to-read inter transaction time
+system.monitor.ittReadRead::55001-60000        204975     12.28%     62.80% # Read-to-read inter transaction time
+system.monitor.ittReadRead::60001-65000        204546     12.26%     75.06% # Read-to-read inter transaction time
+system.monitor.ittReadRead::65001-70000             3      0.00%     75.06% # Read-to-read inter transaction time
+system.monitor.ittReadRead::70001-75000             3      0.00%     75.06% # Read-to-read inter transaction time
+system.monitor.ittReadRead::75001-80000             2      0.00%     75.06% # Read-to-read inter transaction time
+system.monitor.ittReadRead::80001-85000           527      0.03%     75.09% # Read-to-read inter transaction time
+system.monitor.ittReadRead::85001-90000        102490      6.14%     81.24% # Read-to-read inter transaction time
+system.monitor.ittReadRead::90001-95000        102495      6.14%     87.38% # Read-to-read inter transaction time
+system.monitor.ittReadRead::95001-100000          551      0.03%     87.41% # Read-to-read inter transaction time
+system.monitor.ittReadRead::overflows          210067     12.59%    100.00% # Read-to-read inter transaction time
+system.monitor.ittReadRead::min_value           28000                       # Read-to-read inter transaction time
+system.monitor.ittReadRead::max_value         1041420                       # Read-to-read inter transaction time
+system.monitor.ittReadRead::total             1668719                       # Read-to-read inter transaction time
+system.monitor.ittWriteWrite::samples         1664619                       # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::mean       59472.389997                       # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::stdev      41840.398153                       # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::underflows            0      0.00%      0.00% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::1-5000                0      0.00%      0.00% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::5001-10000            0      0.00%      0.00% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::10001-15000            0      0.00%      0.00% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::15001-20000            0      0.00%      0.00% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::20001-25000            0      0.00%      0.00% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::25001-30000       419825     25.22%     25.22% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::30001-35000       419112     25.18%     50.40% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::35001-40000            4      0.00%     50.40% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::40001-45000            6      0.00%     50.40% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::45001-50000            6      0.00%     50.40% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::50001-55000            6      0.00%     50.40% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::55001-60000       208578     12.53%     62.93% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::60001-65000       207985     12.49%     75.42% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::65001-70000            3      0.00%     75.42% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::70001-75000            3      0.00%     75.42% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::75001-80000            3      0.00%     75.42% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::80001-85000          552      0.03%     75.46% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::85001-90000       102802      6.18%     81.63% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::90001-95000       102817      6.18%     87.81% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::95001-100000          552      0.03%     87.84% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::overflows        202365     12.16%    100.00% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::min_value         28000                       # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::max_value        598079                       # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::total           1664619                       # Write-to-write inter transaction time
+system.monitor.ittReqReq::samples             3333339                       # Request-to-request inter transaction time
+system.monitor.ittReqReq::mean           29999.937068                       # Request-to-request inter transaction time
+system.monitor.ittReqReq::stdev           1278.967916                       # Request-to-request inter transaction time
 system.monitor.ittReqReq::underflows                0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::1-5000                    0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::5001-10000                0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::10001-15000               0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::15001-20000               0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::20001-25000               0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::25001-30000         3333200    100.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::30001-35000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::35001-40000              99      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::40001-45000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::45001-50000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::50001-55000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::55001-60000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::60001-65000               0      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::25001-30000         1684541     50.54%     50.54% # Request-to-request inter transaction time
+system.monitor.ittReqReq::30001-35000         1648718     49.46%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::35001-40000              18      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::40001-45000              15      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::45001-50000              11      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::50001-55000              20      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::55001-60000              13      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::60001-65000               2      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::65001-70000               0      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::70001-75000               0      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::75001-80000               0      0.00%    100.00% # Request-to-request inter transaction time
@@ -450,22 +496,22 @@ system.monitor.ittReqReq::80001-85000               0      0.00%    100.00% # Re
 system.monitor.ittReqReq::85001-90000               0      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::90001-95000               0      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::95001-100000              0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::overflows                 0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::min_value             30000                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::max_value             40000                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::total               3333299                       # Request-to-request inter transaction time
+system.monitor.ittReqReq::overflows                 1      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::min_value             28000                       # Request-to-request inter transaction time
+system.monitor.ittReqReq::max_value           1041420                       # Request-to-request inter transaction time
+system.monitor.ittReqReq::total               3333339                       # Request-to-request inter transaction time
 system.monitor.outstandingReadsHist::samples          100                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean     1.290000                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::gmean     1.120561                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev     1.139688                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::0              0      0.00%      0.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1             92     92.00%     92.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2              2      2.00%     94.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::3              0      0.00%     94.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::4              3      3.00%     97.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::5              0      0.00%     97.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::6              0      0.00%     97.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::7              3      3.00%    100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::mean     1.030000                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::gmean            0                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::stdev     0.881402                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::0             28     28.00%     28.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::1             47     47.00%     75.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::2             21     21.00%     96.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::3              3      3.00%     99.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::4              0      0.00%     99.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::5              1      1.00%    100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::6              0      0.00%    100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::7              0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::8              0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::9              0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::10             0      0.00%    100.00% # Outstanding read transactions
@@ -480,11 +526,11 @@ system.monitor.outstandingReadsHist::18             0      0.00%    100.00% # Ou
 system.monitor.outstandingReadsHist::19             0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::total          100                       # Outstanding read transactions
 system.monitor.outstandingWritesHist::samples          100                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::mean            0                       # Outstanding write transactions
+system.monitor.outstandingWritesHist::mean     0.150000                       # Outstanding write transactions
 system.monitor.outstandingWritesHist::gmean            0                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::stdev            0                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::0           100    100.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::1             0      0.00%    100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::stdev     0.358870                       # Outstanding write transactions
+system.monitor.outstandingWritesHist::0            85     85.00%     85.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::1            15     15.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::2             0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::3             0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::4             0      0.00%    100.00% # Outstanding write transactions
@@ -505,9 +551,9 @@ system.monitor.outstandingWritesHist::18            0      0.00%    100.00% # Ou
 system.monitor.outstandingWritesHist::19            0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::total          100                       # Outstanding write transactions
 system.monitor.readTransHist::samples             100                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::mean              33333                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::gmean      33333.000000                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::stdev                 0                       # Histogram of read transactions per sample period
+system.monitor.readTransHist::mean       16687.200000                       # Histogram of read transactions per sample period
+system.monitor.readTransHist::gmean      16635.188141                       # Histogram of read transactions per sample period
+system.monitor.readTransHist::stdev       1683.853859                       # Histogram of read transactions per sample period
 system.monitor.readTransHist::0-2047                0      0.00%      0.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::2048-4095             0      0.00%      0.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::4096-6143             0      0.00%      0.00% # Histogram of read transactions per sample period
@@ -515,46 +561,46 @@ system.monitor.readTransHist::6144-8191             0      0.00%      0.00% # Hi
 system.monitor.readTransHist::8192-10239            0      0.00%      0.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::10240-12287            0      0.00%      0.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::12288-14335            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::14336-16383            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::16384-18431            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::18432-20479            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::20480-22527            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::22528-24575            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::24576-26623            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::26624-28671            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::28672-30719            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::30720-32767            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::32768-34815          100    100.00%    100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::14336-16383            5      5.00%      5.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::16384-18431           94     94.00%     99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::18432-20479            0      0.00%     99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::20480-22527            0      0.00%     99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::22528-24575            0      0.00%     99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::24576-26623            0      0.00%     99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::26624-28671            0      0.00%     99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::28672-30719            0      0.00%     99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::30720-32767            0      0.00%     99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::32768-34815            1      1.00%    100.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::34816-36863            0      0.00%    100.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::36864-38911            0      0.00%    100.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::38912-40959            0      0.00%    100.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::total               100                       # Histogram of read transactions per sample period
 system.monitor.writeTransHist::samples            100                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::mean                 0                       # Histogram of read transactions per sample period
+system.monitor.writeTransHist::mean      16646.200000                       # Histogram of read transactions per sample period
 system.monitor.writeTransHist::gmean                0                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::stdev                0                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::0                  100    100.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::1                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::2                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::3                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::4                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::5                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::6                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::7                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::8                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::9                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::10                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::11                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::12                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::13                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::14                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::15                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::16                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::17                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::18                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::19                   0      0.00%    100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::stdev      1683.921595                       # Histogram of read transactions per sample period
+system.monitor.writeTransHist::0-1023               1      1.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::1024-2047            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::2048-3071            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::3072-4095            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::4096-5119            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::5120-6143            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::6144-7167            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::7168-8191            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::8192-9215            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::9216-10239            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::10240-11263            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::11264-12287            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::12288-13311            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::13312-14335            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::14336-15359            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::15360-16383            0      0.00%      1.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::16384-17407           99     99.00%    100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::17408-18431            0      0.00%    100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::18432-19455            0      0.00%    100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::19456-20479            0      0.00%    100.00% # Histogram of read transactions per sample period
 system.monitor.writeTransHist::total              100                       # Histogram of read transactions per sample period
-system.cpu.numPackets                         3333300                       # Number of packets generated
+system.cpu.numPackets                         3333340                       # Number of packets generated
 system.cpu.numRetries                               0                       # Number of retries
 system.cpu.retryTicks                               0                       # Time spent waiting due to back-pressure (ticks)
 
-- 
2.30.2